Device packaging structure

Abstract

The embodiment of the utility model discloses a device packaging structure. The device packaging structure comprises a PCB base, a radio frequency bare chip, a plurality of single-layer capacitor banks and a top cover, the PCB base comprises a top-layer PCB, a bottom-layer PCB and a middle dielectric layer; a first heat dissipation bonding pad, a plurality of first pin bonding pads, an input port bonding pad and an output port bonding pad are arranged on the top-layer PCB, and the first pin bonding pads, the input port bonding pad and the output port bonding pad are distributed around the first heat dissipation bonding pad; the radio frequency bare chip and the plurality of single-layer capacitor groups are welded on the first heat dissipation bonding pad; a second heat dissipation bonding pad and a plurality of second pin bonding pads distributed around the second heat dissipation bonding pad are arranged on the bottom layer PCB; and the top cover is arranged on the PCB base. The PCB base is designed on the basis of a PCB standard manufacturing process, the input port bonding pad and the output port bonding pad which are adaptive to the specific characteristics of the radio frequency bare chip can be preset, the impedance matching of input and output is improved, the signal transmission performance is optimized, and the product performance after device packaging is improved.

Description

Technical Field

[0001] The embodiments of the utility model relate to the field of semiconductor packaging technology, and in particular to a device packaging structure. Background Art

[0002] In integrated circuits, the device package secures the chip, protects internal components, transmits electrical signals, and dissipates heat. The RF bare chip, a single integrated circuit chip cut from a wafer, is the core component of a semiconductor device. In related technologies, device packaging involves soldering the RF bare chip to the lead frame of the package base, followed by plastic sealing or ceramic sealing. The lead frame primarily consists of chip pads, which support and secure the RF bare chip, and pins, which connect to external circuits.

[0003] However, since the aforementioned device package is not optimized for the specific characteristics of the RF bare chip, as the operating frequency increases, it will be affected by the parasitic parameters of the package base, resulting in a decrease in the input and output impedance matching performance, affecting the device performance. Utility Model Content

[0004] An embodiment of the utility model provides a device packaging structure, which solves the problem in the related art that the device package is not optimized for the specific characteristics of the radio frequency bare chip, is easily affected by the parasitic parameters of the package base, resulting in a decrease in the input and output impedance matching performance, and affects the device performance. It realizes the design of the PCB base based on the standard PCB process technology, and can pre-set the input port pads and output port pads adapted to the specific characteristics of the radio frequency bare chip, thereby improving the input and output impedance matching, optimizing the signal transmission performance, and improving the product performance after the device is packaged.

[0005] In a first aspect, an embodiment of the present invention provides a device packaging structure, comprising:

[0006] PCB base, RF bare chip, multiple single-layer capacitor groups and top cover;

[0007] The PCB base includes a top PCB board, a bottom PCB board and an intermediate dielectric layer, wherein the intermediate dielectric layer is located between the top PCB board and the bottom PCB board;

[0008] The top PCB board is provided with a first heat dissipation pad, and a plurality of first pin pads, an input port pad, and an output port pad distributed around the first heat dissipation pad, and a first solder resist layer is provided in an area between each of the first heat dissipation pad, the plurality of first pin pads, the input port pad, and the output port pad;

[0009] The radio frequency bare chip and multiple single-layer capacitor groups are welded on the first heat dissipation pad;

[0010] The voltage input port of the power amplification unit in the RF bare chip is connected to the corresponding single-layer capacitor group, the single-layer capacitor group is connected to the corresponding first pin pad, the RF input port in the RF bare chip is connected to the input port pad, and the RF output port in the RF bare chip is connected to the output port pad;

[0011] The bottom PCB board is provided with a second heat dissipation pad and a plurality of second pin pads distributed around the second heat dissipation pad, a second solder resist layer is provided in an area between the second heat dissipation pad and the plurality of second pin pads, the second heat dissipation pad is connected to the first heat dissipation pad, and the plurality of first pin pads, the input port pad, and the output port pad are respectively connected to the corresponding second pin pads;

[0012] The top cover is mounted on the PCB base.

[0013] Optionally, the input port pad and the output port pad are T-shaped pads.

[0014] Optionally, the second heat dissipation pad is connected to the first heat dissipation pad through a metal via passing through the intermediate dielectric layer.

[0015] Optionally, the second heat dissipation pad is connected to the first heat dissipation pad via a copper block located inside the intermediate dielectric layer.

[0016] Optionally, the voltage input port includes a drain voltage port and a gate voltage port.

[0017] Optionally, the single-layer capacitor group includes a first single-layer capacitor and a second single-layer capacitor, the capacitance of the first single-layer capacitor is smaller than the capacitance of the second single-layer capacitor, the voltage input port of the power amplification unit in the RF bare chip is connected to the first single-layer capacitor, the first single-layer capacitor is connected to the second single-layer capacitor, and the second single-layer capacitor is connected to the corresponding first pin pad.

[0018] Optionally, a debugging metal block is provided in an area of ​​the top PCB board adjacent to the input port pad and the output port pad respectively.

[0019] Optionally, the plurality of first pin pads, input port pads and output port pads are respectively connected to corresponding second pin pads through copper plating on the side of the PCB base.

[0020] Optionally, the top cover is a ceramic cover, and the top cover is adhered to the PCB base by applying high-temperature glue to the surface edge of the top PCB board.

[0021] Optionally, the top cover is a metal cover, which is pre-fixed through fixing holes provided at diagonal corners of the surface of the top PCB board and welded to the metal cover welding area of ​​the PCB base.

[0022] In an embodiment of the present utility model, the device packaging structure includes a PCB base, a radio frequency bare chip, a plurality of single-layer capacitor groups and a top cover; the PCB base includes a top PCB board, a bottom PCB board and an intermediate dielectric layer, and the intermediate dielectric layer is located between the top PCB board and the bottom PCB board; a first heat dissipation pad is provided on the top PCB board, and a plurality of first pin pads, input port pads and output port pads are distributed around the first heat dissipation pad, and a first solder resist layer is provided in the area between the first heat dissipation pad, the plurality of first pin pads, the input port pads and the output port pads; the radio frequency bare chip and the plurality of single-layer capacitor groups are welded on the first heat dissipation pad; the power amplification unit in the radio frequency bare chip The voltage input port is connected to the corresponding single-layer capacitor group, the single-layer capacitor group is connected to the corresponding first pin pad, the RF input port in the RF bare chip is connected to the input port pad, and the RF output port in the RF bare chip is connected to the output port pad; a second heat dissipation pad and a plurality of second pin pads distributed around the second heat dissipation pad are provided on the bottom PCB board, a second solder resist layer is provided in the area between the second heat dissipation pad and the plurality of second pin pads, the second heat dissipation pad is connected to the first heat dissipation pad, the plurality of first pin pads, input port pad and output port pad are respectively connected to the corresponding second pin pads; the top cover is installed on the PCB base. The PCB base is designed based on the standard PCB process technology, and the input port pad and output port pad adapted to the specific characteristics of the RF bare chip can be pre-set to improve the impedance matching of input and output, optimize the signal transmission performance, and improve the product performance after the device is packaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic structural diagram of a device packaging structure provided by an embodiment of the present utility model;

[0024] Figure 2 A schematic structural diagram of a PCB base provided in an embodiment of the present utility model;

[0025] Figure 3 A schematic structural diagram of a top PCB board provided in an embodiment of the present utility model;

[0026] Figure 4 A schematic diagram of a radio frequency bare chip and multiple single-layer capacitor groups soldered to a top PCB board provided by an embodiment of the present utility model;

[0027] Figure 5A schematic diagram of copper plating on the side of a PCB base provided by an embodiment of the present utility model;

[0028] Figure 6 A schematic diagram of a first single-layer capacitor and a second single-layer capacitor soldered to a top PCB board according to an embodiment of the present invention;

[0029] Figure 7 A schematic diagram of another RF bare chip and multiple single-layer capacitor groups soldered to a top PCB board provided by an embodiment of the present utility model;

[0030] Figure 8 A schematic structural diagram of a bottom PCB board provided in an embodiment of the present utility model;

[0031] Figure 9 A schematic diagram of a bottom PCB board provided with metal vias according to an embodiment of the present invention;

[0032] Figure 10 A schematic diagram of a bottom PCB board provided with a copper block according to an embodiment of the present utility model;

[0033] Figure 11 A schematic structural diagram of another top PCB board provided in an embodiment of the present utility model;

[0034] Figure 12 A schematic structural diagram of a PCB base coated with high-temperature adhesive provided in an embodiment of the present utility model;

[0035] Figure 13 A schematic structural diagram of a PCB base provided with fixing holes and a metal cover welding area provided in an embodiment of the present utility model. DETAILED DESCRIPTION

[0036] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions of the embodiments of the present invention, rather than all structures.

[0037] The terms "first," "second," and the like in the specification and claims of the present invention are used to distinguish similar objects, not to describe a specific order or precedence. It should be understood that such terms are interchangeable where appropriate, so that embodiments of the present invention can be implemented in an order other than that illustrated or described herein. The terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object can be one or more, and should not be construed as indicating or implying relative importance. Furthermore, the terms "and / or" in the specification and claims refer to at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the connected objects. Furthermore, unless otherwise expressly specified or limited, the terms "disposed," "mounted," "connected," "connected," and "in series" should be interpreted broadly, meaning, for example, fixed, removable, or integral; mechanically or electrically; directly or indirectly through an intermediary; or internally between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention.

[0038] In the related art, the device package is to weld the RF bare chip to the lead frame of the package base, and then perform plastic sealing, ceramic sealing, etc. Since the device package adopts a standard universal package and is not optimized for the specific characteristics of the RF bare chip, as the operating frequency increases, it will be affected by the parasitic parameters of the package base, resulting in a decrease in the input and output impedance matching performance, causing the performance of the packaged device to be degraded, such as power, gain, efficiency, etc. Based on this, the embodiment of the present utility model provides a device packaging structure, which aims to solve the problem in the related art that the device package is not optimized for the specific characteristics of the RF bare chip, is easily affected by the parasitic parameters of the package base, resulting in a decrease in the input and output impedance matching performance, and affects the device performance.

[0039] Figure 1 A schematic diagram of a device packaging structure provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the device packaging structure includes a PCB base 101, a radio frequency bare chip 102, a plurality of single-layer capacitor groups 103 and a top cover 104, and the top cover 104 is installed on the PCB base 101.

[0040] Among them, the RF bare chip is an unpackaged RF chip. As one of the core components of the RF system, the RF bare chip can be used in integrated circuits that generate, transmit and receive RF signals. RF signals generally refer to electromagnetic waves with a frequency range of 3KHz to 300GHz, and are mainly used for wireless communication and data transmission. Specifically, the RF bare chip can integrate multiple functional modules, such as a low-noise amplifier unit, a power amplifier unit, an RF switch, a mixing unit and a control unit. Since the RF bare chip is not packaged, its surface is exposed and is easily affected by the temperature, impurities and physical forces of the external environment. Therefore, the embodiment of the utility model aims to provide a device packaging structure for packaging RF bare chips and can be optimized for the specific characteristics of the RF bare chip. The PCB base is designed based on the standard PCB process technology and has the advantages of convenience, low cost and high performance. The single-layer capacitor group can be used for power supply filtering of the power supply line. The top cover can be used to protect the internal RF bare chip, the single-layer capacitor group and the gold wire that provides the connection.

[0041] Specifically, Figure 2 A schematic diagram of the structure of a PCB base provided by an embodiment of the present utility model is shown as follows: Figure 2 As shown, the PCB base includes a top PCB board 1011 , a bottom PCB board 1012 and an intermediate dielectric layer 1013 . The intermediate dielectric layer 1013 is located between the top PCB board 1011 and the bottom PCB board 1012 .

[0042] The intermediate dielectric layer can be selected based on the frequency requirements of a specific application scenario, and the present invention does not limit this.

[0043] in, Figure 3 A schematic diagram of the structure of a top PCB board provided in an embodiment of the present utility model is shown as follows: Figure 3 As shown, a first heat dissipation pad 10111 and a plurality of first pin pads 10112, an input port pad 10113 and an output port pad 10114 are provided on the top PCB board, and a first solder resist layer 10115 is provided in the area between the first heat dissipation pad 10111, the plurality of first pin pads 10112, the input port pad 10113 and the output port pad 10114. Figure 4 A schematic diagram of a radio frequency bare chip and multiple single-layer capacitor groups soldered to a top PCB board provided by an embodiment of the present invention is shown in FIG. Figure 4As shown, the RF bare chip 102 and multiple single-layer capacitor groups 103 are welded on the first heat dissipation pad 10111; the voltage input port 1021 of the power amplification unit (not shown in the figure) in the RF bare chip 102 is connected to the corresponding single-layer capacitor group 103, the single-layer capacitor group 103 is connected to the corresponding first pin pad 10112, the RF input port 1022 in the RF bare chip 102 is connected to the input port pad 10113, and the RF output port 1023 in the RF bare chip 102 is connected to the output port pad 10114.

[0044] Specifically, the PCB base can be used as a carrier for the RF bare chip, and the corresponding circuit structure can be designed according to the specific characteristics of the RF bare chip to achieve electrical connection between the internal circuit lead-out end of the chip and the external circuit. At the same time, the heat generated by the chip during operation can be conducted away to prevent the chip from being damaged due to overheating. Specifically, the first heat dissipation pad of the top PCB board can be used for welding the RF bare chip and the single-layer capacitor group. The first pin pad can be set in corresponding quantity and distribution position according to the functional pins of the RF bare chip and the actual welding requirements. Thus, a part of the first pin pad can be used to connect to the pins of the RF bare chip, while the other part of the first pin pad does not need to be connected to the pins of the RF bare chip and can be used as a reserved pad for welding and fixing. The first solder mask layer can be used to isolate between the pads. The voltage input port of the power amplifier unit in the RF bare chip can be connected to the single-layer capacitor group through a gold wire, and the single-layer capacitor group can be connected to the corresponding first pin pad through a gold wire. Thus, the external voltage can be filtered by the single-layer capacitor group before driving the RF bare chip to work. In addition, the RF input port of the RF bare chip can be connected to the input port pad via gold wire, and the RF output port of the RF bare chip can be connected to the output port pad via gold wire, thereby establishing a signal transmission channel. It should be noted that the input port pad and the output port pad are matching circuits designed for the specific input and output characteristics of the RF bare chip.

[0045] In one embodiment, Figure 5 A schematic diagram of copper plating on the side of a PCB base provided by an embodiment of the present invention, such as Figure 5 As shown, multiple first pin pads 10112, input port pads (not shown in the figure) and output port pads (not shown in the figure) are respectively connected to corresponding second pin pads 10122 through the copper plating 1014 on the side of the PCB base.

[0046] Optionally, the voltage input port includes a drain voltage port and a gate voltage port, and the drain voltage port and the gate voltage port of the power amplification unit of the RF bare chip are led out through the first pin pad, which can be used to receive external power supply.

[0047] In one embodiment, Figure 6 A schematic diagram of a first single-layer capacitor and a second single-layer capacitor soldered to a top PCB board according to an embodiment of the present invention is shown in FIG. Figure 6 As shown, the single-layer capacitor group 103 includes a first single-layer capacitor 1031 and a second single-layer capacitor 1032. The capacitance of the first single-layer capacitor 1031 is smaller than that of the second single-layer capacitor 1032. The voltage input port 1021 of the power amplification unit (not shown in the figure) in the RF bare chip 102 is connected to the first single-layer capacitor 1031, the first single-layer capacitor 1031 is connected to the second single-layer capacitor 1032, and the second single-layer capacitor 1032 is connected to the corresponding first pin pad 10112.

[0048] It should be noted that the capacitance of the first single-layer capacitor is smaller than that of the second single-layer capacitor. The first single-layer capacitor can be used to filter high-frequency clutter, while the second single-layer capacitor can be used to filter low-frequency clutter. The voltage input port of the power amplifier unit in the RF bare chip is connected to the first single-layer capacitor via a gold wire, the first single-layer capacitor is connected to the second single-layer capacitor via a gold wire, and the second single-layer capacitor is connected to the corresponding first pin pad via a gold wire.

[0049] In one embodiment, Figure 7 A schematic diagram of another RF bare chip and multiple single-layer capacitor groups soldered to a top PCB board provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the input port pad and the output port pad are T-shaped pads.

[0050] It's worth noting that in the microwave field, the design of microstrip transmission lines is particularly important. On the top PCB, the input and output port pads act as microstrip transmission lines. The characteristic impedance of the input and output port pads is primarily determined by their line width and the specific PCB material. For example, input and output port pads with a characteristic impedance of 50 ohms can transmit signals well. However, if the characteristic impedance deviates from 50 ohms, signal loss increases. Therefore, the specific shape of the input and output port pads must be adjusted to suit the input and output characteristics of the RF bare chip to achieve impedance matching and reduce signal loss. Since the voltage input port of the RF bare chip is connected to the input and output port pads via gold wire, the parasitic parameters of the gold wire and the circuit at microwave frequencies can affect the input and output matching, leading to device performance degradation. For example, the gain of the power amplifier unit may not meet the standard device specifications. In order to offset the influence of parasitic parameters, the specific shapes of the input port pads and the output port pads can be adjusted, which is equivalent to adding a matching circuit to achieve impedance matching, so that the signal is better transmitted. The PCB base designed by the above-mentioned PCB standard process technology can be easily realized. After the PCB material is determined, the impedance of the input port pads and the output port pads is mainly determined by the line width, such as Figure 6 As shown, you can first design with 50 ohm impedance. At this time, the shape of the input port pad and the output port pad is a straight pad. Then, you can combine the performance parameters of the RF bare chip, the binding method (number of binding wires, length and curvature) and the lid parameters to perform a three-dimensional performance simulation of the high-frequency structure. It is understandable that since the parasitic parameters introduced by the binding wires and the package base have been simulated during the simulation, the performance level of the device after it is finished can be simulated. When the performance simulation does not meet the indicators, the shape of the input port pad and the output port pad is redesigned. For example, Figure 7 For Figure 6 On this basis, the shape of the input port pad and the output port pad is adjusted from a straight pad to a T-shaped pad, which is equivalent to adding distributed capacitance or distributed inductance to the original input and output lines. This can ensure that the impedance of the designed input port pad and output port pad can be well matched in a wide bandwidth, thereby achieving the purpose of optimizing device performance. The specific line width can be set differently according to different RF bare chips, which is not limited by the present invention. The following Table 1 shows the output power data and gain data of the device before and after the shape optimization of the input port pad and the output port pad. Among them, the RF bare chip is a bare chip in the 11GHz frequency band. The input port pad and the output port pad before optimization are as follows. Figure 6 As shown, the optimized input port pads and output port pads are as follows Figure 7 shown.

[0051] Table 1

[0052]

[0053] As can be seen from Table 1, due to the influence of metal binding wires and parasitic parameters, the power gain of the device before optimization cannot reach the conventional value of 24dB. However, after the optimized design, the power gain of the device can reach the conventional value of 24dB or above.

[0054] Specifically, Figure 8 A schematic diagram of the structure of a bottom PCB board provided in an embodiment of the present utility model is shown as follows: Figure 8 As shown, the bottom PCB is provided with a second heat dissipation pad 10121 and a plurality of second pin pads 10122 distributed around the second heat dissipation pad 10121. A second solder resist layer 10123 is provided in the area between the second heat dissipation pad 10121 and the plurality of second pin pads 10122. It should be noted that the second heat dissipation pad is connected to the first heat dissipation pad, and the plurality of first pin pads, input port pads, and output port pads are respectively connected to corresponding second pin pads.

[0055] In one embodiment, Figure 9 A schematic diagram of a bottom PCB board provided with metal vias according to an embodiment of the present invention is shown in FIG. Figure 9 As shown, a metal via 10124 is provided on the second heat dissipation pad 10121 of the bottom PCB. Specifically, the second heat dissipation pad can be connected to the first heat dissipation pad via a metal via that passes through the intermediate dielectric layer. The metal via is a via with a metal plating. It is understood that heat from the top PCB can be transferred to the bottom PCB through the metal via, achieving the purpose of chip heat dissipation.

[0056] In one embodiment, Figure 10 A schematic diagram of a bottom PCB board provided with a copper block according to an embodiment of the present invention is shown as follows: Figure 10 As shown, a copper block 10125 is provided on the second heat dissipation pad 10121 of the bottom PCB board. Specifically, the second heat dissipation pad can be connected to the first heat dissipation pad through a copper block located inside the intermediate dielectric layer. It should be noted that when the heat generated by the RF bare chip is high, the second heat dissipation pad transfers heat to the first heat dissipation pad through the metal via, which may have a low efficiency problem and cannot meet the requirement of rapid heat transfer to the outside. Therefore, in order to better dissipate heat, a copper embedding process can be adopted to mill out a copper embedding area at the preset positions corresponding to the first heat dissipation pad, the second heat dissipation pad and the intermediate dielectric layer in the PCB base, and embed the copper block. In this way, the second heat dissipation pad is connected to the first heat dissipation pad through the copper block located inside the intermediate dielectric layer, thereby optimizing the heat transfer path and achieving the purpose of rapid heat dissipation of the chip.

[0057] In one embodiment, Figure 11 A schematic diagram of the structure of another top PCB board provided in an embodiment of the present invention is shown as follows: Figure 11 As shown, a debugging metal block 10115 is provided in the area adjacent to the input port pad 10113 and the output port pad 10114 on the top PCB board.

[0058] It is worth noting that device-level testing can be performed before the device is capped. If performance deviations are detected, wire-binding debugging can be performed on the reserved debugging metal block to determine an optimization solution.

[0059] In one embodiment, Figure 12 A schematic diagram of the structure of a PCB base coated with high-temperature glue provided by an embodiment of the present invention, wherein the top cover is a ceramic cover, such as Figure 12 As shown, the surface edge of the top PCB board is coated with high temperature glue 105. Thus, the top cover can be pasted on the PCB base by the high temperature glue 105 coated on the surface edge of the top PCB board.

[0060] The ceramic cover's high-temperature resistance, stability, corrosion resistance, sealing, and heat dissipation properties ensure that high-frequency, high-power electronic components maintain stable operating conditions in a variety of operating environments, improving device reliability and service life. Therefore, ceramic covers are a popular choice for device packaging.

[0061] In one embodiment, Figure 13 A schematic structural diagram of a PCB base provided with fixing holes and a metal cover welding area according to an embodiment of the present invention, wherein the top cover is a metal cover, such as Figure 13 As shown, the top PCB board is provided with fixing holes 106 and metal cover welding area 107. Thus, the top cover can be pre-fixed through the fixing holes provided at the diagonal corners of the surface of the top PCB board and welded to the metal cover welding area of ​​the PCB base.

[0062] Metal covers offer excellent protection, shielding, and thermal conductivity, effectively protecting electronic components from external environmental damage while blocking external signal interference, ensuring the proper functioning of high-frequency, high-power electronic components. Therefore, metal covers are a popular choice for device packaging.

[0063] The above-mentioned method realizes the design of the PCB base based on the standard PCB process technology, and can pre-set the input port pads and output port pads adapted to the specific characteristics of the RF bare chip, thereby improving the impedance matching of the input and output, optimizing the signal transmission performance, and improving the product performance after the device is packaged.

[0064] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0065] Note that the above are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions are readily apparent to those skilled in the art without departing from the scope of protection of the present invention. Therefore, while the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the appended claims.

Claims

1. A device packaging structure, characterized in that: include: PCB base, RF bare chip, multiple single-layer capacitor groups and top cover; The PCB base includes a top PCB board, a bottom PCB board and an intermediate dielectric layer, wherein the intermediate dielectric layer is located between the top PCB board and the bottom PCB board; The top PCB board is provided with a first heat dissipation pad, and a plurality of first pin pads, an input port pad, and an output port pad distributed around the first heat dissipation pad, and a first solder resist layer is provided in an area between each of the first heat dissipation pad, the plurality of first pin pads, the input port pad, and the output port pad; The radio frequency bare chip and multiple single-layer capacitor groups are welded on the first heat dissipation pad; The voltage input port of the power amplification unit in the RF bare chip is connected to the corresponding single-layer capacitor group, the single-layer capacitor group is connected to the corresponding first pin pad, the RF input port in the RF bare chip is connected to the input port pad, and the RF output port in the RF bare chip is connected to the output port pad; The bottom PCB board is provided with a second heat dissipation pad and a plurality of second pin pads distributed around the second heat dissipation pad, a second solder resist layer is provided in an area between the second heat dissipation pad and the plurality of second pin pads, the second heat dissipation pad is connected to the first heat dissipation pad, and the plurality of first pin pads, the input port pad, and the output port pad are respectively connected to the corresponding second pin pads; The top cover is mounted on the PCB base.

2. The device packaging structure according to claim 1, wherein: The input port pad and the output port pad are T-shaped pads.

3. The device packaging structure according to claim 1, wherein: The second heat dissipation pad is connected to the first heat dissipation pad through a metal via that passes through the intermediate dielectric layer.

4. The device packaging structure according to claim 1, wherein: The second heat dissipation pad is connected to the first heat dissipation pad via a copper block located inside the intermediate dielectric layer.

5. The device packaging structure according to claim 1, wherein: The voltage input port includes a drain voltage port and a gate voltage port.

6. The device packaging structure according to claim 1, wherein: The single-layer capacitor group includes a first single-layer capacitor and a second single-layer capacitor, the capacitance of the first single-layer capacitor is smaller than the capacitance of the second single-layer capacitor, the voltage input port of the power amplification unit in the RF bare chip is connected to the first single-layer capacitor, the first single-layer capacitor is connected to the second single-layer capacitor, and the second single-layer capacitor is connected to the corresponding first pin pad.

7. The device packaging structure according to claim 1, wherein: A debugging metal block is provided in an area of ​​the top PCB board adjacent to the input port pad and the output port pad respectively.

8. The device packaging structure according to claim 1, wherein: The plurality of first pin pads, input port pads and output port pads are respectively connected to corresponding second pin pads through copper plating on the side of the PCB base.

9. The device packaging structure according to claim 1, wherein: The top cover is a ceramic cover, and is adhered to the PCB base by applying high-temperature glue on the surface edge of the top PCB board.

10. The device packaging structure according to claim 1, wherein: The top cover is a metal cover, which is pre-fixed through fixing holes provided at diagonal corners on the surface of the top PCB board and is welded to the metal cover welding area of ​​the PCB base.

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