Electronic component

Abstract

The utility model provides an electronic component which has the following structure or characteristics. The diode is formed in the active region. The diode includes a P-type composition embedded in a first portion of the active region, an N-type composition embedded in a second portion of the active region, and an undoped composition located between the P-type composition and the N-type composition. An interconnect structure is formed on the first side of the diode. Different portions of the interconnect structure are electrically coupled with the P-type composition and the N-type composition, respectively. One or more openings are etched in the dielectric structure disposed on a second side of the diode opposite the first side. The doping material is implanted into the active region through the one or more openings. The one or more openings are filled with a conductive material. The manner of the present disclosure can reduce harmful effects associated with positively charged plasma and can improve device performance. Other advantages may include compatibility with existing processes as well as ease of implementation and low cost.

Description

TECHNICAL FIELD

[0001] The present utility model relates to an electronic component, in particular to an electronic component with a doped region for neutralizing electrons in diode structure. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. The technological advances that have resulted in IC materials and design have produced generations of ICs, each having greater functionality and smaller geometry (i.e., smaller features) than the last. As the dimensions of the features become smaller, the number of features that can be formed on a die increases. The increased functionality and complexity of ICs has resulted in an increased demand for even greater functionality and complexity.

[0003] However, as the microfabrication process continues, it presents some manufacturing challenges. For example, the fabrication of a diode structure can result in the presence of positively charged particles in the dielectric structure. The presence of these positively charged particles can attract electrons close to the dielectric structure, which can result in poor component performance and is therefore undesirable.

[0004] Thus, while certain diode processes have generally been adequate for their intended purpose, they have not been wholly satisfactory in all respects. SUMMARY

[0005] Embodiments of the present utility model provide an electronic component. The electronic component includes a diode, an interconnect structure, a plurality of conductive vias, and one or more doped regions. The diode includes a P-type region, an N-type region, and an undoped intrinsic region between the P-type region and the N-type region. The interconnect structure is on a first side of the diode. The plurality of conductive vias is on a second side of the diode. The second side is different from the first side. The one or more doped regions are disposed between the diode and the conductive vias.

[0006] An embodiment of the present invention provides an electronic component. The electronic component includes an active region, a PIN diode, a first conductive contact, a second conductive contact, a dielectric structure, and one or more doped regions. The active region includes a plurality of interlaced first and second semiconductor layers. The PIN diode is formed in the active region. The PIN diode includes a P-type composition, an N-type composition, and an undoped composition located between the P-type composition and the N-type composition. The first conductive contact and the second conductive contact are located on a first side of the PIN diode. The first conductive contact and the second conductive contact are electrically coupled to the P-type composition and the N-type composition, respectively. The dielectric structure is located on a second side of the PIN diode. The second side is opposite to the first side. One or more doped regions are located between the PIN diode and the dielectric structure. Each of the one or more doped regions includes a P-type dopant.

[0007] Based on the above, various processes may involve the use of positively charged plasmas, which may cause positively charged particles to enter the dielectric structures of IC components, including diodes. The presence of the positively charged particles may then attract electrons on or near the surface of the dielectric structures, which may adversely affect the performance and / or intended operation of the diodes. The disclosed approach can reduce the harmful effects associated with positively charged plasmas and improve device performance. Other advantages may include compatibility with existing processes and ease and low cost of implementation.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A three-dimensional view of a FinFET device is depicted.

[0010] Figure 1B A top view of a FinFET device is shown.

[0011] Figure 1C A three-dimensional perspective view of a multi-channel gate-all-around (GAA) device is shown.

[0012] Figure 2A is a top view of the diode structure.

[0013] Figure 2B It is a cross-sectional view of the diode structure.

[0014] Figure 2C It is a three-dimensional perspective diagram of the diode structure.

[0015] Figure 3-Figure 12 A series of side cross-sectional views of an IC device at various stages of fabrication are shown according to various aspects of the present disclosure.

[0016] Figure 13 is a block diagram of a manufacturing system according to various aspects of the present disclosure.

[0017] Figure 14-15 is a flow chart illustrating a method for manufacturing an IC according to various aspects of the present disclosure.

[0018] Description of reference numerals:

[0019] 90: IC components (Integrated Circuit devices);

[0020] 110: substrate;

[0021] 120: active region, fin structure, fin;

[0022] 122: source / drain components;

[0023] 130: isolation structure;

[0024] 140: Gate structure;

[0025] 150: GAA components (gate-all-around device), GAA transistors (gate-all-around transistor);

[0026] 155: layer;

[0027] 160: Gate spacer structure;

[0028] 165: capping layer;

[0029] 170: nanostructure;

[0030] 175: dielectric inner spacer;

[0031] 180: source / drain contacts;

[0032] 185: interlayer dielectric (ILD);

[0033] 200: PIN diode;

[0034] 210: active region;

[0035] 220, 230: semiconductor layer;

[0036] 200A: P-type component, P-type doped component;

[0037] 200B: N-type component, N-type doped component;

[0038] 270, 271, 272: lateral dimension;

[0039] 250: dielectric structure;

[0040] 300: IC device;

[0041] 305: isolation structure;

[0042] 310: Gate structure;

[0043] 320A, 320B: conductive contact;

[0044] 350: positively charged plasma;

[0045] 360: positively charged particles;

[0046] 370: electrons;

[0047] 400: CPEC structure (charge potential equivalence control structure, CPECstructure);

[0048] 410A, 410B, 410C, 410D, 410E, 411A, 411B: conductive vias;

[0049] 420A, 421A, 420B, 421B: metal line;

[0050] 430, 431: side;

[0051] 450A, 450B: conductive pad;

[0052] 460A, 460B: electrical interconnection structure;

[0053] 500, 550: interconnect structure;

[0054] 510A, 511A, 512A, 513A, 514A, 510B, 511B, 512B, 513B, 514B: conductive vias;

[0055] 520A, 521A, 522A, 523A, 524A, 520B, 521B, 522B, 523B, 524B: metal lines;

[0056] 560: carrier wafer;

[0057] 570: bonding layer;

[0058] 580: etching process;

[0059] 590A, 590B, 590C, 590D, 590E: via trench opening;

[0060] 600A, 600B: doped regions;

[0061] 610: dopant implantation process;

[0062] 620: depth;

[0063] 630: deposition process;

[0064] 700: GAA transistor;

[0065] 720: gate structure;

[0066] 730: source / drain components;

[0067] 750: source / drain vias;

[0068] 900: Integrated circuit fabrication system, fabrication system;

[0069] 918: Communication network (network);

[0070] 902, 904, 906, 908, 910, 912, 914, 916, ..., N: entity;

[0071] 1000, 1100: method;

[0072] 1010, 1020, 1030, 1040, 1050, 1110, 1120, 1130, 1140, 1150: steps. DETAILED DESCRIPTION

[0073] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes that a first characteristic component is formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the embodiments of the present invention may repeat the use of numbers and / or text in each example. This repetition is for the purpose of brevity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0074] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0075] Further, when a numerical or a numerical range is described with a term "about", "substantially" or the like, the term is intended to encompass numbers that are within a reasonable range of the number, including the number, such as within + / - 10% of the number, or other values as understood by one of ordinary skill in the art. For example, the term "about 5 nanometers (nm)" encompasses a range of sizes from 4.5 nm to 5.5 nm.

[0076] The present disclosure is generally directed to improving performance of integrated circuit (IC) elements including diode structures. More specifically, diode structures can be formed as a type of passive IC element. For example, a diode structure can be formed by doping a portion of a semiconductor material with P-type dopants and doping another portion of the semiconductor material with N-type dopants. In this manner, a P-N junction of a diode can be formed. Diode structures can also include PIN diodes, where the P-type and N-type components of the diode structure are separated by an undoped semiconductor component (also referred to as an intrinsic component).

[0077] As semiconductor devices continue to shrink, three-dimensional transistor devices, such as fin field-effect transistors (FinFETs) or multi-channel gate-all-around (GAA) devices, have gained widespread adoption in recent years. To ensure compatibility with the fabrication of these three-dimensional transistors, fin diodes (compatible with FinFET fabrication) or lateral PIN diodes (compatible with GAA fabrication) can be formed on the integrated circuits (ICs) forming the three-dimensional transistors. However, the fabrication of these diodes still presents some challenges. For example, in lateral PIN diodes fabricated alongside GAA transistors, dielectric structures may be placed near the lateral PIN diodes. The fabrication of GAA transistors may involve various etching processes, which may use positively charged plasma. Positively charged plasma may enter the portion of the integrated circuit where the lateral PIN diode structure is formed. For example, some positively charged particles may enter the dielectric structure located near the lateral PIN diode. The presence of positively charged particles in the dielectric structure may attract electrons. Unfortunately, when sufficient electrons accumulate near the surface of the dielectric structure, the performance of the lateral PIN diode may be adversely affected. For example, these electrons may cause undesirable voltage fluctuations. Diode junction capacitance and / or diode reverse current may also be affected, resulting in degradation of device performance.

[0078] The present disclosure implements various charge potential equivalence control (CPEC) structures to address the issues discussed above. In certain embodiments, the CPEC structure may include additional electrical interconnect structures. These additional electrical interconnect structures, such as vias and metal lines, may be used to prevent positively charged plasma from entering IC components, which in turn prevents electrons from concentrating near dielectric structures. In this way, the additional electrical interconnect structures (as one embodiment of a CPEC structure) may eliminate or reduce potential damage caused by the presence of plasma. In other embodiments, the CPEC structure may include one or more additional P-type doped regions formed between the PIN diode and the dielectric structure. The P-type doped regions attract electrons that would otherwise be attracted to the surface of the dielectric structure. The electrons attracted to the P-type doped regions may cancel each other out (e.g., cancel each other out in terms of charge). In this way, the problem of excessive electron concentration near the dielectric structure may be alleviated, which in turn may improve device performance.

[0079] Now refer to Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 2A 、 Figure 2B 、 Figure 2C as well as Figure 3-Figure 15 , discusses various aspects of the present disclosure in more detail. More specifically, Figure 1A-1B An exemplary FinFET device is shown, and Figure 1C An exemplary GAA device is shown. Figure 2A-2C A top view, a cross-sectional side view, and a three-dimensional perspective view of the diode are depicted. Figure 3-Figure 12 Cross-sectional side views of a portion of an IC device at various stages of fabrication are shown according to an embodiment of the present disclosure. Figure 13 A semiconductor manufacturing system that may be used to manufacture the IC devices of the present disclosure is shown. Figure 14-15 Methods of manufacturing IC devices according to various aspects of the present disclosure are shown.

[0080] See now Figure 1A and Figure 1B , which respectively depict a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) component 90. The IC component 90 is implemented using field effect transistors (FETs), such as three-dimensional fin-line FETs (FinFETs). A FinFET component has a semiconductor fin structure that protrudes vertically out of a substrate. The fin structure is an active region from which source / drain regions and / or channel regions are formed. The source / drain region may refer to a source or a drain, which may be referred to independently or collectively depending on the context. The source / drain region may also refer to an area that provides a source and / or drain for multiple components. A gate structure partially surrounds the fin structure. In recent years, FinFET components have become increasingly popular due to their enhanced performance compared to traditional planar transistors.

[0081] like Figure 1AAs shown, IC component 90 includes a substrate 110. Substrate 110 may include a base (single element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; or an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, and / or other suitable materials. Substrate 110 may be a single layer of material having a uniform composition. Alternatively, substrate 110 may include multiple layers of materials having similar or different compositions, which are suitable for IC component fabrication. For example, substrate 110 may be a silicon-on-insulator (SOI) substrate, which has a semiconductor silicon layer formed on a silicon oxide layer. In another example, substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source / drain regions, may be formed on or in substrate 110. These doped regions can be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron, depending on design requirements. The doped regions can be formed directly on the substrate 110, or in a p-well structure, an n-well structure, a double-well structure, or using a riser structure. The doped regions can be formed by implanting dopant atoms, epitaxial growth with in-situ doping, and / or other appropriate techniques.

[0082] A three-dimensional active region 120 is formed on a substrate 110. The active region 120 may include an elongated fin-shaped structure protruding from the substrate 110. Therefore, the active region 120 may be referred to interchangeably as a fin structure 120 or fin 120 hereinafter. The fin structure 120 may be manufactured using suitable processes, including a photolithography process and an etching process. The photolithography process may include forming a photoresist layer on the substrate 110, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element (not shown) including the photoresist. The mask element is then used to etch a recess in the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by a double patterning process or a multiple patterning process. Generally, the double patterning process or the multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having, for example, smaller pitches than can be achieved using a single, direct photolithography process. For example, a layer can be formed on a substrate and patterned using a photolithography process. Spacers can be formed next to the patterned layer using a self-aligned process. The layer is then removed, and the remaining spacers or mandrels can be used to pattern the fin structure 120.

[0083] IC component 90 also includes a source / drain component 122 formed on fin structure 120. Source / drain component 122 (also referred to as a source region / drain region) may refer to the source or drain of a transistor, which may be referred to individually or collectively depending on the context. Source / drain component 122 may include an epitaxial layer grown epitaxially on fin structure 120. IC component 90 further includes an isolation structure 130 formed on substrate 110. Isolation structure 130 electrically isolates the various components of IC component 90. Isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric material, and / or other suitable materials. In some embodiments, isolation structure 130 may include a shallow trench isolation (STI) feature. In one embodiment, isolation structure 130 is formed by etching a trench in substrate 110 during the formation of fin structure 120. The trenches may then be filled with the aforementioned isolation material, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, may also be implemented as isolation structure 130. Alternatively, isolation structure 130 may include a multi-layer structure, for example, having one or more thermal oxide liners.

[0084] The IC device 90 also includes a gate structure 140 formed on three sides of the channel region of each fin 120 and joined to the fin structure 120. In other words, the gate structures 140 each surround a plurality of fin structures 120. The gate structure 140 may be a dummy gate structure (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or may be a high-k metal gate (HKMG) structure including a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not shown here, the gate structure 140 may include additional material layers, such as an interface layer, a capping layer, other suitable layers, or a combination thereof, on the fin structure 120.

[0085] Reference Figure 1A-1B The plurality of fin structures 120 are each arranged longitudinally along the X-direction, and the plurality of gate structures 140 are each arranged longitudinally along the Y-direction, i.e., substantially perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional features, such as gate spacers disposed along the sidewalls of the gate structures 140, a hard shield layer disposed on the gate structures 140, and many other features.

[0086] Figure 1C A three-dimensional perspective view of an exemplary multi-channel gate-all-around (multi-channel GAA) device 150 is shown. The GAA device has multiple longitudinal nanostructured channels, which can be implemented as nanotubes, nanosheets, or nanowires. For consistency and clarity, Figure 1C and Figure 1A-1B Similar components in the fin structure 120 are labeled the same. For example, the active region of the fin structure 120 rises vertically upward from the substrate 110 in the Z direction. The isolation structure 130 provides electrical isolation between the fin structures 120. The gate structure 140 is located above the fin structure 120 and the isolation structure 130. A layer 155 is located above the gate structure 140, and a gate spacer structure 160 is located on the sidewalls of the gate structure 140. During the formation of the isolation structure 130, a capping layer 165 is formed on the fin structure 120 to protect the fin structure 120 from oxidation.

[0087] A plurality of nanostructures 170 are disposed above each fin structure 120. Nanostructures 170 may comprise nanosheets, nanotubes, nanowires, or other types of nanostructures, extending horizontally in the X-direction. The portion of nanostructures 170 beneath gate structure 140 may serve as a channel for GAA device 150. Dielectric interspacers 175 may be disposed between nanostructures 170. Furthermore, although not shown for simplicity, each stack of nanostructures 170 may be surrounded by a gate dielectric and a gate electrode. In the illustrated embodiment, the portion of nanostructures 170 outside gate structure 140 may serve as a source / drain feature for GAA device 150. However, in some embodiments, continuous source / drain features may be epitaxially grown on the portion of fin structure 120 outside gate structure 140. Regardless, conductive source / drain contacts 180 may be formed on the source / drain features to provide electrical connection. An interlayer dielectric (ILD) 185 is formed on the isolation structure 130 and around the gate structure 140 and the source / drain contacts 180. The ILD 185 may be referred to as an ILD0 layer. In some embodiments, the ILD 185 may include silicon oxide, silicon nitride, or a low-k dielectric material.

[0088] like Figure 1A-1B FinFET components and Figure 1CGAA elements can be used to implement circuits having various functions, such as, by way of non-limiting examples, memory elements (e.g., static random access memory (SRAM) elements), logic circuits, input / output (I / O) elements, application specific integrated circuit (ASIC) elements, radio frequency (RF) circuits, drivers, microcontrollers, central processing units (CPUs), image sensors, etc. At the same time, the process flow used to fabricate FinFET elements or GAA elements can also be used to form certain types of passive elements, such as diodes. These diodes can be formed on the same wafer as the FinFET elements or GAA elements. As noted above, during the fabrication of the diodes, positively charged plasma can enter the wafer, which can cause damage and / or degrade element performance. According to various aspects of the present disclosure, a charged potential equivalent control (CPEC) structure can be implemented to mitigate potential problems caused by positively charged plasma entering the wafer, as discussed in detail below.

[0089] Figure 2A , Figure 2B , Figure 2C FIGS. 1A, IB, and 1C respectively illustrate a planar top view, a side cross-sectional view, and a three-dimensional perspective view of a PIN diode 200 as an example diode formed according to various aspects of the present disclosure. The PIN diode 200 includes an active region 210 (also referred to as an OD), which can be formed as a fin structure (in the case of a FinFET element) or as a stack of alternating semiconductor layers (in the case of a GAA element). By way of non-limiting example, the active region 210 here is formed using a process that forms a GAA element, such as the GAA element 150 discussed above with reference to FIG. 1. Thus, the active region 210 includes a stack of interleaved semiconductor layers 220 and semiconductor layers 230. The semiconductor layers 220 and semiconductor layers 230 have different material compositions. For example, the semiconductor layers 220 can include silicon, while the semiconductor layers 230 can include silicon germanium, or vice versa. It should be understood that the active region 210 here is formed at the same time as the active region of the GAA element (i.e., using the same process that forms the GAA element). Figure 1C

[0090] ​As described above, the active region 210 formed by these interlaced semiconductor layers 220 and semiconductor layers 230 can be used to define the channel region and / or source / drain region of a GAA transistor. However, in the case of the PIN diode 200, the active region 210 provides a region in which the P-type composition, N-type composition, and intrinsic composition of the PIN diode 200 can be formed. In more detail, an implantation process can be performed to implant a P-type dopant (e.g., boron) into a portion of the active region 210, thereby forming a P-type composition 200A. Another implantation process can be performed to implant an N-type dopant (e.g., arsenic or phosphorus) into another portion of the active region 210, thereby forming an N-type composition 200B. The P-type composition 200A and the N-type composition 200B of the PIN diode 200 are separated by an undoped portion of the active region 210, which can also be referred to as the intrinsic composition of the PIN diode 200.

[0091] like Figure 2A As shown, the P-type component 200A, the N-type component 200B, and the intrinsic portion (e.g., the portion of the undoped active region 210 between the P-type component 200A and the N-type component 200B) have different lateral dimensions 270, lateral dimension 271, and lateral dimension 272, respectively. In some embodiments, lateral dimension 271 is greater than lateral dimension 272, which in turn is greater than lateral dimension 270. For example, the ratio between lateral dimension 270 and lateral dimension 271 may be in the range of approximately 1:3 and approximately 1:3.4, while the ratio between lateral dimension 270 and lateral dimension 272 may be in the range of approximately 1:2.6 and approximately 1:3. These ratios may be dictated by design rules to accommodate GAA device fabrication.

[0092] like Figure 2B and Figure 2C As shown, dielectric structure 250 is disposed below PIN diode 200. In some embodiments, dielectric structure 250 comprises a silicon nitride layer. In some embodiments, dielectric structure 250 comprises multiple dielectric layers, such as a silicon nitride layer and a silicon oxide layer. As described above and described in further detail below, positively charged plasma may enter dielectric structure 250, thereby attracting electrons around the interface between dielectric structure 250 and PIN diode 200. These electrons may affect the voltage potential, increase parasitic capacitance, and / or degrade other diode performance parameters. Therefore, the present disclosure implements a CPEC structure to eliminate or at least reduce the presence of these electrons, thereby improving device performance.

[0093] Figure 3 FIG. 2 is a side cross-sectional view of a portion of an IC device 300 including a PIN diode 200 . Figure 3This helps illustrate the aforementioned issues related to positively charged plasma. Specifically, the PIN diode 200 includes a P-type component 200A, an N-type component 200B, and an undoped portion of the active region 210. The P-type component 200A and the N-type component 200B each extend vertically through a plurality of interleaved pairs of semiconductor layers 220 and 230. Note that the plurality of isolation structures 305 are also present. Figure 3 PIN diode 200 is formed between isolation structures 305.

[0094] Since the PIN diode 200 is manufactured using the same method as that used in manufacturing GAA devices (e.g., Figure 1C Because the same process flow is used for the GAA transistor (similar to the GAA transistor 150 in FIG. 1 , but formed in another portion of the IC device 300), other components associated with the GAA process may also be formed in the region of the IC device 300 that includes the PIN diode 200. For example, the gate structure 310 may be formed on an intrinsic portion of the PIN diode 200 (e.g., on the portion of the active region 210 between the P-type component 200A and the N-type component 200B). Furthermore, conductive contacts 320A and 320B may be formed on the P-type component 200A and the N-type component 200B of the PIN diode 200, respectively. In the GAA portion of the IC device 300, the counterparts of conductive contacts 320A and 320B may function as source / sink contacts. However, conductive contacts 320A and 320B may function as conduits, allowing charge to enter the IC device 300.

[0095] In detail, during the manufacturing process of GAA components, multiple etching processes may be performed. Some of these etching processes may involve the application of positively charged plasma, such as Figure 3 denoted by reference numeral 350. Since conductive contacts 320A and 320B are electrically conductive, they may provide a path for positively charged plasma 350 to easily enter IC component 300. For example, positively charged plasma 350 may enter dielectric structure 250 through conductive contacts 320A and 320B, and / or other conductive components. As a result, dielectric structure 250 may become positively charged. Figure 3In the embodiment of the present invention, this is represented by a plurality of positively charged particles 360 in the dielectric structure 250. The presence of positively charged particles 360 in the dielectric structure 250 may attract electrons 370 located at or near the interface between the dielectric structure 250 and the active region 210 (e.g., a portion of the silicon substrate). The presence of electrons 370 may cause unexpected voltage fluctuations and / or degradation of the diode junction capacitance or reverse current of the PIN diode 200, which may be undesirable.

[0096] Figure 4 A conceptual block diagram of a CPEC structure 400 for mitigating issues associated with positively charged plasma 350 is shown, according to a first embodiment of the present disclosure. Specifically, CPEC structure 400 includes conductive vias 410A and 410B, electrically coupled to P-type component 200A and N-type component 200B, respectively, of PIN diode 200. Conductive contacts 320A and 320B are formed on side 430 of PIN diode 200, while conductive vias 410A and 410B are formed on side 431 of PIN diode 200 opposite side 430. Conductive contacts 320A and 410A are electrically coupled together via a set of electrical interconnect structures (e.g., vias and metal lines) 460A, enabling a first voltage to be applied to conductive contacts 320A and 410A via conductive pads 450A. In this manner, both sides (eg, side 430 and side 431 ) of the P-type component 200A of the PIN diode 200 are forced to reach the same voltage potential, thereby preventing the positively charged plasma 350 from entering the IC device 300 through the P-type component 200A.

[0097] Similarly, the conductive contact 320B and the conductive via 410B are electrically coupled together via a set of electrical interconnect structures (e.g., vias and metal lines) 460B. Thus, a second voltage can be applied simultaneously to the conductive contact 320B and the conductive via 410B via the conductive pad 450B. Again, both sides (e.g., side 430 and side 431) of the N-type component 200B of the PIN diode 200 reach the same voltage potential, thereby preventing the positively charged plasma 350 from entering the IC device 300 through the N-type component 200B.

[0098] Figure 5 A side cross-sectional view of a portion of an IC component 300 is shown in which a Figure 4CPEC structure 400. More specifically, interconnect structure 500 is formed on side surface 430 of PIN diode 200. Interconnect structure 500 includes multiple metal layers including metal lines, and these metal layers are connected together by multiple conductive vias. For example, interconnect structure 500 includes conductive vias 510A-conductive vias 514A and conductive vias 510B-conductive vias 514B, as well as metal lines 520A-metal lines 524A and metal lines 520B-metal lines 524B. It should be understood that Figure 5 The conductive vias and metal lines of the interconnect structure 500 shown in FIG. 5 are merely provided as a simplified example and are not intended to be limiting unless otherwise stated.

[0099] A subset of interconnect structure 500 provides electrical connections for P-type component 200A of PIN diode 200, while another subset of interconnect structure 500 provides electrical connections for N-type component 200B of PIN diode 200. For example, conductive vias 510A-514A and metal lines 520A-524A are electrically coupled to P-type component 200A of PIN diode 200 via conductive contact 320A. Similarly, conductive vias 510B-514B and metal lines 520B-524B are electrically coupled to N-type component 200B of PIN diode 200 via conductive contact 320B.

[0100] At the same time, interconnect structure 550 is formed on side 431 of PIN diode 200. Interconnect structure 500 may also include multiple metal layers, including metal lines and conductive vias. For example, interconnect structure 550 includes conductive vias 410A-conductive vias 411A and conductive vias 410B-conductive vias 411B, each of which vertically passes through dielectric structure 250. Interconnect structure 550 also includes metal lines 420A-metal lines 421A and metal lines 420B-metal lines 421B, as well as the above-mentioned Figure 4 The related conductive pads 450A and 450B. The metal lines 420A-421A and the conductive vias 411A can be considered as Figure 4 In one embodiment of the electrical interconnect structure 460A, the metal lines 420B-421B and the conductive through-holes 411B can be considered as Figure 4 Again, unless otherwise stated, it is understood that Figure 5 The conductive vias and metal lines of the interconnect structure 550 shown in FIG. 5 are merely provided as a simplified example and are not intended to be limiting.

[0101] As before with Figure 4In related discussion, conductive via 410A provides an electrical connection to P-type component 200A of PIN diode 200. Since conductive pad 450A is electrically coupled to conductive via 410A via metal lines 420A, 421A, and conductive via 411A, a voltage can be applied to P-type component 200A via conductive pad 450A during operation of IC device 300. Similarly, conductive via 410B provides an electrical connection to N-type component 200B of PIN diode 200. Since conductive pad 450B is electrically coupled to conductive via 410B via metal lines 420B, 421B, and conductive via 411B, a voltage can be applied to N-type component 200B via conductive pad 450B during operation of IC device 300.

[0102] According to various aspects of the present disclosure, interconnect structures 500 and 550 are electrically coupled together such that the same first voltage can be applied simultaneously to side 430 and side 431 of P-type component 200A, and the same second voltage can be applied simultaneously to side 430 and side 431 of N-type component 200B. For example, metal line 420A of interconnect structure 550 is electrically coupled to a portion of interconnect structure 500 that includes conductive via 510A, conductive via 514A, and metal line 520A, metal line 524A. In other words, although not specifically illustrated for simplicity, multiple metal lines and conductive vias may exist between metal line 420A and metal line 524A. Metal line 420A is also electrically coupled to conductive via 410A, which is electrically coupled from side 431 to P-type component 200A. Therefore, when a first voltage is applied to conductive pad 450A, the same first voltage will be felt at metal line 420A, as well as conductive via 410A and conductive contact 320A (through electrical coupling with conductive vias 510A-514A and metal lines 520A-524A).

[0103] Similarly, when a second voltage is applied to conductive pad 450B, the same second voltage will be felt by metal line 420B, as well as conductive via 410B and conductive contact 320B (via electrical coupling with conductive vias 510B-514B and metal lines 520B-524B). In other words, the first voltage may have two paths to reach P-type component 200A, via side 430 and side 431, and the second voltage may have two paths to reach N-type component 200B, via side 430 and side 431, but the voltage potentials of these paths are the same. Therefore, positively charged plasma has a difficult time entering IC device 300 because the voltage potentials of the two circuits are substantially the same, effectively preventing the entry of charged particles. In this way, it can be said that CPEC structure 400—which includes portions of the two interconnect structures 500 and 550—can prevent positively charged plasma from entering IC device 300, which in turn reduces damage caused by positively charged plasma and improves device performance.

[0104] It should be understood that Figure 5 The portion of IC device 300 shown is at an intermediate stage of fabrication. For example, at this stage, the interconnect structure 500 of IC device 300 is tightly bonded to carrier wafer 560 through bonding layer 570. Subsequent processing may require the IC device 300 to be removed from carrier wafer 560 (and bonding layer 570).

[0105] Figure 4-Figure 5 A first embodiment of a CPEC structure 400 according to various aspects of the present disclosure is illustrated. Figure 6-Figure 9 A second embodiment of a CPEC structure 400 according to various aspects of the present disclosure is shown. According to the second embodiment, the CPEC structure 400 does not utilize additional interconnect components to balance the voltage potentials of the side 430 and the side 431 of the PIN diode 200. Instead, Figure 6-Figure 9 The CPEC structure 400 of the second embodiment includes one or more doped regions formed in a substrate (eg, a silicon substrate) of the active region 210. The formation of the one or more doped regions will be discussed below with reference to Figure 6-Figure 9 Again, for reasons of clarity and consistency, the Figure 4-Figure 5 Similar components in Figure 6-Figure 9 Marked as the same.

[0106] In detail, Figure 6-Figure 8 FIG. 1 is a side cross-sectional view of a portion of an IC device 300 at various stages of processing according to a second embodiment of the present disclosure. Figure 6One or more etch processes 580 are performed on the IC element 300 from the side 431. The one or more etch processes 580 can include a dry etch process in some embodiments, or a wet etch process in other embodiments. It is to be understood that the one or more etch processes 580 can also be performed on another portion of the IC element 300 at the same time, which includes a GAA transistor, in order to form via trench openings from the side 431 to establish electrical connectivity for the GAA transistor. For the portion of the IC element 300 illustrated in Figure 6 , the etch processes 580 etch one or more via trench openings, such as via trench openings 590A and 590B. The via trench openings 590A and 590B each vertically pass through the dielectric structure 250, and a portion of the active region 210. However, the via trench openings 590A and 590B are not etched deep enough to expose the P-type component 200A or the N-type component 200B of the PIN diode 200 from the side 431. Note that the positively charged particles 360 can already be present in the dielectric structure 250 at this process stage, which can attract the electrons 370 to gather near the interface between the dielectric structure 250 and the active region 210.

[0107] Referring now to Figure 7 , a dopant implant process 610 is performed to implant dopants into the active region 210 from the via trench openings 590A and 590B through the side 431. In some embodiments, the dopant implant process 610 implants P-type dopant species (e.g., boron) into the active region 210. The implanted dopant species forms one or more doped regions in the active region, depending on the number (and / or size) of the via trench openings that the dopant implant is performed from. In the embodiment illustrated in Figure 7 , the doped regions 600A and 600B (e.g., P-type doped regions containing boron) are formed in the active region 210 as part of the CPEC structure 400. Since the dopant implant process 610 is performed from the side 431, the doped regions 600A and 600B each extend from the side 431 to the side 410. In Figure 7 embodiments, the doped regions 600A and 600B can laterally merge into one, although it is to be understood that they can be spaced apart from each other in other embodiments.

[0108] Doped regions 600A and 600B are disposed above conductive vias 410A and 410B, respectively. This is because via trench openings 590A and 590B are aligned with conductive vias 410A and 410B, respectively. According to various aspects of the present disclosure, because doped regions 600A and 600B include P-type dopants, they attract and neutralize at least a portion of electrons 370 that would otherwise be attracted to the interface between dielectric structure 250 and the substrate of active region 210. In this way, even if dielectric structure 250 still includes positively charged particles 360, the presence of doped regions 600A and 600B reduces the number of electrons 370 that accumulate near dielectric structure 250. In this way, potential damage to IC device 300 may be reduced and / or the performance of IC device 300 may be improved.

[0109] It should be understood that the positions and / or sizes of the doped regions 600A and 600B can be flexibly configured by adjusting various process parameters disclosed herein. For example, the positions of the doped regions 600A and 600B may be substantially determined by the positions of the through-hole trench openings 590A and 590B through which the dopant is implanted. In other words, the doped region 600A may be substantially aligned with the through-hole trench openings 590A in the vertical direction, and the doped region 600B may be substantially aligned with the through-hole trench openings 590B in the vertical direction.

[0110] The widths (lateral dimensions) of doped regions 600A and 600B are also related to the widths of through-hole trench openings 590A and 590B. Therefore, adjusting the widths of through-hole trench openings 590A and 590B may also affect the widths of doped regions 600A and 600B. However, it should be understood that the widths of through-hole trench openings 590A and 590B are typically set based on the design and / or manufacturing specifications of transistors (e.g., GAA transistors) in different parts of IC device 300. In other words, the process used to etch (and subsequently fill) through-hole trench openings 590A and 590B is the same process used to form the conductive through vias of a GAA device (e.g., as a different part of IC device 300) on the same wafer. Because GAA processing may be a primary concern, the dimensions of through-hole trench openings 590A and 590B may also be primarily inherited from the processing of GAA transistors.

[0111] However, the number of through-hole trench openings 590A and through-hole trench openings 590B can still be configured to effectively adjust the width of the overall doped region 600A-doped region 600B because when a sufficient number of through-hole trench openings are formed, the doped region 600A-doped region 600B may merge with each other, and when the fusion occurs, the doped region 600A-doped region 600B may be regarded as a single doped region. Figure 7 In certain embodiments, the combined doped region 600A and the combined doped region 600B may extend laterally from one isolation structure 305 to an adjacent isolation structure 305. Therefore, the combined width of the doped region 600A and the combined doped region 600B may be wider than the P-type doped component 200A and / or the N-type doped component 200B of the PIN diode 200. The wider width of the doped region 600A and the combined doped region 600B may be more advantageous in attracting and neutralizing electrons 370. However, the size of the doped region 600A and the combined doped region 600B is not so large as to interfere with the normal operation of the PIN diode 200.

[0112] The depth 620 (e.g., vertical dimension) of the doped regions 600A and 600B can also be configured by adjusting the parameters of the dopant implantation process. For example, by changing the implantation energy, the depth of the doped regions 600A and 600B can be changed. The depth of the through-hole trench opening - which may also be determined by the corresponding GAA process - may also affect the depth of the doped regions 600A and 600B. Figure 7 In the embodiment, the depth 620 of the doped regions 600A and 600B extends into the substrate of the active region 210 but does not reach the P-type doped composition 200A or the N-type doped composition 200B of the PIN diode 200. This helps ensure that the doped regions 600A and 600B do not adversely affect the normal operation of the PIN diode 200.

[0113] Now refer to Figure 8From side 431 , IC component 300 is subjected to a deposition process 630 to fill through-hole trench opening 590A and through-hole trench opening 590B with one or more conductive materials. In some embodiments, deposition process 630 may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination thereof. A planarization process, such as a chemical mechanical polishing (CMP) process, may also be performed to planarize the surface of the deposited conductive material in through-hole trench opening 590A and through-hole trench opening 590B and the surface of dielectric structure 250 facing side 431 . Thus, conductive through-holes 410A and 410B are formed in through-hole trench opening 590A and through-hole trench opening 590B. As described above, conductive through-holes similar to conductive through-holes 410A and 410B are also formed in areas of IC component 300 that include GAA elements. Therefore, it can be seen that the present disclosure utilizes the process of the GAA region of the IC device 300 to implement additional targets customized for the non-GAA region of the IC device 300 (eg, the PIN diode 200 region), thereby saving process cost and process time.

[0114] Figure 9 A side cross-sectional view of a portion of an IC component 300 is shown, wherein Figure 8 The CPEC structure is 400. For example, Figure 9 The CPEC structure 400 shown in FIG. 4 further includes a doped region 600A and a doped region 600B doped with a P-type dopant. Figure 8 There are 400 different structures in CPEC, Figure 9 The CPEC structure 400 is configured such that the doped region 600A and the doped region 600B are not merged into one, but are separated by a portion of the active region 210. The doped region 600A and the doped region 600B, and their corresponding conductive through vias 410A and 410B, are vertically aligned with the P-type component 200A and the N-type component 200B of the PIN diode 200, respectively.

[0115] As described above, the doped regions 600A and 600B help to attract and neutralize the electrons that are attracted by the positively charged plasma and thus accumulate on the upper surface of the dielectric structure 250. Therefore, although the IC device 300 does not use the additional connection components (e.g., Figure 5 The voltage potential of the PIN diode 200 is balanced by using the metal lines 420A and 420B in the circuit, but the harmful effects caused by the positively charged plasma can still be greatly alleviated. It should be understood that the positively charged particles 360 and electrons 370 in the circuit are Figure 9 It is not specifically shown in the figure for the sake of simplicity.

[0116] To provide additional information about the second embodiment of the present disclosure, Figure 10-12 The side cross-sectional view of the GAA portion of the IC device 300 is shown during a series of processes corresponding to the formation of the conductive through vias 410A and 410B described above. Again, for the sake of clarity and consistency, the Figure 4-Figure 9 Similar components in Figure 10-12 are marked as identical. Note also that Figure 10-12 The side 430 and the side 431 in Figure 4-Figure 9 The side 430 and the side 431 are flipped in the vertical direction.

[0117] Now refer to Figure 10 The GAA portion of the IC element 300 includes a plurality of GAA transistors 700, as referenced above. Figure 1C 1 . Each GAA transistor 700 may be formed at least in part using the active region 210 discussed above. For example, each GAA transistor 700 may include a stack of nanostructure channels (e.g., nanosheets, nanorods, nanotubes, nanowires, etc.) formed using the semiconductor layer 220. The semiconductor layer 230 is removed and replaced with a metal-containing gate structure 720. For example, each metal-containing gate structure 720 may include a high-k gate dielectric and a metal gate electrode. Another portion of the metal-containing gate structure 720 may be disposed on the edge 431 of the stack of nanostructure channels.

[0118] The source / drain formation 730 may also be formed laterally on both sides of the gate structure 720. It should be understood that the source / drain formation 730 may refer to the source or the drain, individually or collectively, depending on the context. In some embodiments, the source / drain formation 730 may be formed by one or more epitaxial growth processes. A source / drain via 750 may be formed from the side 430 of the IC element 300 to provide an electrical connection to the source / drain formation 730 from the side 430. At the same time, at this stage of the process, no electrical connection has yet been formed from the side 431 of the GAA transistor 700. Figure 10 At this stage of the process shown, a dielectric structure 250 may be disposed over the GAA transistor 700 . The dielectric structure 250 may include a dielectric layer 250A (eg, silicon oxide) and a dielectric layer 250B (eg, silicon nitride).

[0119] Now refer to Figure 11 , the above Figure 6The one or more etching processes 580 discussed above are also used for this portion of the IC device 300. The one or more etching processes 580 also etch through the dielectric layer 250A and the dielectric layer 250B, as well as a portion of the active region 210 to expose the source / drain composition 730. In this way, a through-hole trench opening 590C, a through-hole trench opening 590D, and a through-hole trench opening 590E are formed. As described above, Figure 11 The through-hole trench opening 590C, the through-hole trench opening 590D and the through-hole trench opening 590E are Figure 6 Through-hole trench opening 590A and through-hole trench opening 590B are formed at the same time (and using the same process steps).

[0120] Now refer to Figure 12 , a deposition process 630 is performed on the IC element 300 to fill the through-hole trench openings 590C-through-hole trench openings 590E with conductive material, thereby forming conductive through-holes 410C-conductive through-holes 410E. As described above, Figure 12 The conductive through vias 410C, 410D and 410E are connected to Figure 8 The conductive vias 410A and 410B are formed simultaneously (using the same process / step). The conductive vias 410C and 410E are electrically coupled to the source / drain components 730 on the side 431 and provide electrical connections from the side 431 to the source / drain components 730.

[0121] according to Figure 10-12 The process flow of GAA transistor 700 shows Figure 8-Figure 9 The formation of the CPEC structure 400 is fully compatible with the manufacturing process of the GAA transistor 700. Therefore, the manufacturing cost and / or process time can be reduced.

[0122] Figure 13 An integrated circuit manufacturing system 900 according to an embodiment of the present disclosure is shown, which can be used to manufacture the IC device 300 of the present disclosure. Manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916, ..., N connected by a communication network 918. Communication network 918 can be a single network or can be a variety of different networks, such as an intranet and the Internet, and can include wired lines and wireless communication channels.

[0123] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer who monitors a product of interest; entity 906 represents an engineer, such as a process engineer who controls a process and associated recipes, or an equipment engineer who monitors or adjusts the conditions and settings of a process tool; entity 908 represents a metrology tool used for IC testing and measurement; entity 910 represents a semiconductor process tool, such as an extreme ultraviolet (EUV) tool for performing optical processes; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents an advanced process control module associated with process tool 910 and other process tools; and entity 916 represents a sampling module associated with process tool 910.

[0124] Each entity may communicate with the other entities and may provide integrated circuit processing, process control, and / or computing capabilities to the other entities and / or receive such capabilities from the other entities. Each entity may also include one or more computer systems for performing calculations and performing automation. For example, the advanced process control module of entity 914 may include a plurality of computer hardware having software instructions encoded therein. The computer hardware may include a hard disk, a flash drive, a compact disc read-only memory (CD-ROM), random access memory (RAM), a display device (e.g., a screen), and input / output devices (e.g., a mouse and keyboard). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

[0125] The integrated circuit manufacturing system 900 enables interaction between entities to perform integrated circuit (IC) manufacturing and advanced process control for IC manufacturing. In one embodiment, the advanced process control includes adjusting processing conditions, settings, and / or recipes of a processing tool applied to an associated wafer based on measurement results.

[0126] In another embodiment, the metrology results are measured from a subset of processed wafers based on an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, the metrology results are measured from selected fields / points of the subset of processed wafers based on optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0127] One capability provided by IC manufacturing system 900 may enable collaboration and information access in areas such as design, engineering, process, metrology, and advanced process control. Another capability provided by IC manufacturing system 900 may be system integration between facilities, such as between metrology tools and process tools. This integration enables facilities to coordinate their activities. For example, integrating metrology tools with process tools may enable more efficient incorporation of manufacturing information into process or advanced process control modules, and may enable integration of wafer data from in-line or in-situ metrology tool measurements within related process tools.

[0128] Figure 14 FIG1 is a flow chart illustrating a method 1000 for fabricating an IC device according to various aspects of the present disclosure. The method 1000 includes step 1010 of forming an active region comprising a plurality of alternating first and second semiconductor layers.

[0129] The method 1000 includes step 1020 of doping a first portion of the active region with a P-type dopant.

[0130] The method 1000 includes step 1030 of doping a second portion of the active region with an N-type dopant. The second portion of the active region is separated from the first portion of the active region by a third portion of the active region that is undoped.

[0131] The method 1000 includes step 1040 of forming a first interconnect structure on a first side of a first portion of an active region and a first side of a second portion of an active region, such that the first portion of the active region is electrically coupled to a first group of interconnects of the first interconnect structure via the first side, and the second portion of the active region is electrically coupled to a second group of interconnects of the first interconnect structure via the first side.

[0132] The method 1000 includes step 1050 of forming a second interconnect structure on a second side of the first portion of the active region and a second side of the second portion of the active region, such that the first portion of the active region is electrically coupled to a third group of interconnect components of the second interconnect structure via the second side, and the second portion of the active region is electrically coupled to a fourth group of interconnect components of the second interconnect structure via the second side. The first group of interconnect components is electrically coupled to the third group of interconnect components, and the second group of interconnect components is electrically coupled to the fourth group of interconnect components.

[0133] In some embodiments, the dielectric structure is formed on the second side of the active region. In some embodiments, forming the second interconnect structure includes: etching a first trench and a second trench in the dielectric structure by etching from the second side toward the first side, such that the first trench exposes a portion of the first portion of the active region from the second side, and the second trench exposes a portion of the second portion of the active region from the second side; and filling the first trench and the second trench with a conductive material to form a first conductive via in the first trench and a second conductive via in the second trench.

[0134] In some embodiments, the dielectric structure includes a plurality of dielectric layers; an active region is formed on a semiconductor substrate; and the first trench and the second trench are etched to penetrate the plurality of dielectric layers and at least partially through the semiconductor substrate.

[0135] In some embodiments, forming the second interconnect structure further includes forming a first metal line on a second side of the first conductive through-via, and forming a second metal line on a second side of the second conductive through-via.

[0136] In some embodiments, the first metal line and the first conductive through-via are part of a third group of interconnect components of the second interconnect structure; the second metal line and the second conductive through-via are part of a fourth group of interconnect components of the second interconnect structure; the first group of interconnect components is electrically coupled to a first side of the first metal line; and the second group of interconnect components is electrically coupled to a first side of the second metal line.

[0137] In some embodiments, the active region of the first portion, the active region of the second portion, and the active region of the third portion together form a PIN diode; forming the second interconnect structure further includes forming a first pad and a second pad on second sides of the first metal line and the second metal line; the first pad is configured to receive a first voltage at the P terminal of the PIN diode; and the second pad is configured to receive a second voltage at the N terminal of the PIN diode.

[0138] It should be understood that additional processes may be performed before, during, or after steps 1010 through 1050 of method 1000. For example, in some embodiments, method 1000 may further include biasing the first and third interconnect components to a first voltage, and biasing the second and fourth interconnect components to a second voltage. For another example, method 1000 may include fabricating a gate-all-around (GAA) device using at least a portion of the fourth portion of the active region.

[0139] Figure 15is a flowchart illustrating a method 1100 of fabricating an IC element in accordance with various aspects of the present disclosure. The method 1100 includes a step 1110 for forming a diode in an active region. The diode includes a P-type composition embedded in a first portion of the active region, an N-type composition embedded in a second portion of the active region, and an un-doped composition disposed between the P-type composition and the N-type composition.

[0140] The method 1100 includes a step 1120 for forming an interconnect structure on a first side of the diode. Different portions of the interconnect structure are respectively electrically coupled with the P-type composition and the N-type composition.

[0141] The method 1100 includes a step 1130 for etching one or more openings through a dielectric structure disposed on a second side of the diode opposite the first side.

[0142] The method 1100 includes a step 1140 for implanting a dopant material into the active region through the one or more openings.

[0143] The method 1100 includes a step 1150 for filling the one or more openings with a conductive material.

[0144] In certain embodiments, the active region includes a stack of a first semiconductor layer and a second semiconductor layer having different material compositions and interleaved with each other. In certain embodiments, forming the diode includes implanting P-type dopants in the first portion of the active region and implanting N-type dopants in the second portion of the active region such that each of the P-type dopants and the N-type dopants penetrates at least a partial subset of the stack of the first semiconductor layer and the second semiconductor layer.

[0145] In certain embodiments, the implanting includes implanting boron as the dopant material through the one or more openings.

[0146] In certain embodiments, the implanting is performed in a manner such that the dopant material implanted into the active region does not reach the P-type composition or the N-type composition of the diode.

[0147] In certain embodiments, the etching is performed in a manner such that a width of each of the one or more openings is greater than the P-type composition or the N-type composition.

[0148] In certain embodiments, the etching is performed in a manner such that none of the one or more openings exposes the P-type element or the N-type element to the second side.

[0149] It should be understood that additional processes may be performed before, during, or after steps 1110-1150 of method 1100. For example, in some embodiments, a diode is formed in a first portion of the active region, and method 1100 further includes the step of at least partially forming a gate-all-around (GAA) transistor in a second portion of the active region. The GAA transistor includes source / drain components, and the etching is performed as part of an etching process that etches source / drain via openings for the source / drain components from the second side.

[0150] In summary, the present disclosure relates to forming a CPEC structure to mitigate potential detrimental effects on diodes caused by positively charged plasma during processing. This disclosure may offer advantages over conventional devices. However, it is understood that not all advantages are discussed herein, that different embodiments may offer different advantages, and that no particular advantage is required. In this regard, various processes may involve the use of a positively charged plasma, which may cause positively charged particles to enter the dielectric structure of an IC device, including a diode. The presence of the positively charged particles may then attract electrons on or near the surface of the dielectric structure, potentially adversely affecting the performance and / or intended operation of the diode. One embodiment of the present disclosure addresses this issue by forming a CPEC structure comprising additional interconnects that balance the voltage potentials across the diode. This makes it more difficult for positively charged particles to find their way into the dielectric structure. This, in turn, may reduce the detrimental effects associated with the positively charged plasma. Another embodiment of the present disclosure addresses this issue by forming additional P-type doped regions in the active region near the dielectric structure. The additional P-type doped regions are formed by utilizing a through-hole formation process that is also used to form electrical interconnects for conventional transistors (e.g., GAA transistors) of IC components, including a through-hole trench formation process. After etching the through-hole trenches, but before filling them, P-type dopant material may be implanted into the active region through the opened through-hole trenches, thereby forming P-type doped regions. The P-type doped regions attract and / or neutralize electrons that would otherwise accumulate near the dielectric structure. In this way, harmful effects associated with positively charged plasmas can also be reduced, and component performance can be improved. Other advantages may include compatibility with existing processes and ease and low cost of implementation.

[0151] The advanced lithographic processes, methods, and materials described above can be used in many applications, including in IC components using fin field-effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between features, for which the above disclosure is well suited. In addition, the spacers used to form the fins of FinFETs, also known as mandrels, can be processed according to the above disclosure. It is also understood that the various aspects of the present disclosure discussed above may be applicable to multi-channel components, such as all-around gate-around (GAA) components. To the extent that the present disclosure refers to fin structures or FinFET components, such discussions may also apply to GAA components.

[0152] One aspect of the present disclosure relates to a component (e.g., an electronic component). The component includes a diode, which includes a P-type region, an N-type region, and an undoped intrinsic region. A first conductive contact and a second conductive contact are respectively located on a first side of the diode. The first conductive contact is electrically coupled to the P-type region from the first side. The second conductive contact is electrically coupled to the N-type region from the first side. A first conductive through-hole and a second conductive through-hole are respectively located on a second side of the diode. The second side is different from the first side. The first conductive through-hole is electrically coupled to the P-type region from the second side. The second conductive through-hole is electrically coupled to the N-type region from the second side. The first conductive contact is electrically coupled to the first conductive through-hole. The second conductive contact is electrically coupled to the second conductive through-hole.

[0153] Another aspect of the present disclosure relates to a component (e.g., an electronic component). The component includes an active region comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers. The first semiconductor layers are interlaced with the second semiconductor layers. A PIN diode is formed in the active region. The PIN diode includes a P-type composition, an N-type composition, and an undoped composition located between the P-type composition and the N-type composition. A first interconnect structure is formed on a first side of the PIN diode. The first interconnect structure includes a first group of interconnect compositions electrically coupled to the P-type composition and a second group of interconnect compositions electrically coupled to the N-type composition. A second interconnect structure is formed on a second side of the PIN diode. The second interconnect structure includes a third group of interconnect compositions electrically coupled to the P-type composition and a fourth group of interconnect compositions electrically coupled to the N-type composition. The first group of interconnect compositions and the third group of interconnect compositions have the same first voltage potential. The second group of interconnect compositions and the fourth group of interconnect compositions have the same second voltage potential.

[0154] Yet another aspect of the present disclosure relates to a method (e.g., an electronic device manufacturing method). An active region is formed comprising a plurality of interleaved first and second semiconductor layers. A first portion of the active region is doped with a P-type dopant. A second portion of the active region is doped with an N-type dopant. The second portion of the active region is separated from the first portion of the active region by a third portion of the undoped active region. A first interconnect structure is formed on a first side of the first portion of the active region and a first side of the second portion of the active region, such that the first portion of the active region is electrically coupled to a first group of interconnects of the first interconnect structure via the first side, and the second portion of the active region is electrically coupled to a second group of interconnects of the first interconnect structure via the first side. A second interconnect structure is formed on a second side of the first portion of the active region and a second side of the second portion of the active region, such that the first portion of the active region is electrically coupled to a third group of interconnects of the second interconnect structure via the second side, and the second portion of the active region is electrically coupled to a fourth group of interconnects of the second interconnect structure via the second side. The first group of interconnects is electrically coupled to the third group of interconnects. The second group of interconnects is electrically coupled to the fourth group of interconnects.

[0155] Another aspect of the present disclosure relates to a device (e.g., an electronic device). The device includes a diode comprising a P-type region, an N-type region, and an undoped intrinsic region located between the P-type region and the N-type region. An interconnect structure is located on a first side of the diode. A plurality of conductive vias are located on a second side of the diode, the second side being different from the first side. One or more doped regions are disposed between the diode and the conductive vias. In one embodiment, the one or more doped regions are doped with a P-type dopant. In one embodiment, in a cross-sectional side view, each of the one or more doped regions has a lateral dimension that is wider than the P-type region or the N-type region. In one embodiment, the electronic device further includes a first isolation structure and a second isolation structure, wherein in a cross-sectional side view, the diode is located between the first isolation structure and the second isolation structure, and the one or more doped regions extend laterally from the first isolation structure to the second isolation structure. In one embodiment, the one or more doped regions include a first doped region vertically aligned with the P-type region of the diode, and a second doped region vertically aligned with the N-type region of the diode. In one embodiment, the electronic device further includes a dielectric layer located on the second side of the diode, wherein each of the conductive vias extends vertically through the dielectric layer. In one embodiment, the undoped intrinsic region includes a plurality of first semiconductor layers and a plurality of second semiconductor layers, the first semiconductor layers being interlaced with the second semiconductor layers. In one embodiment, the first semiconductor layers include silicon; and the second semiconductor layers include silicon germanium. In one embodiment, the P-type region includes a plurality of P-type doped portions of the first and second semiconductor layers; and the N-type region includes a plurality of N-type doped portions of the first and second semiconductor layers. In one embodiment, a diode is formed in the first region of the device, and the device further includes a second region in which a plurality of gate-all-around (GAA) transistors are formed.

[0156] Another aspect of the present disclosure relates to a component (e.g., an electronic component). The component includes an active region comprising a plurality of interlaced first and second semiconductor layers. A PIN diode is formed in the active region. The PIN diode includes a P-type composition, an N-type composition, and an undoped composition located between the P-type composition and the N-type composition. A first conductive contact and a second conductive contact are located on a first side of the PIN diode. The first conductive contact and the second conductive contact are electrically coupled to the P-type composition and the N-type composition, respectively. A dielectric structure is located on a second side of the PIN diode relative to the first side. One or more doped regions are located between the PIN diode and the dielectric structure, wherein each of the one or more doped regions includes a P-type dopant. In one embodiment, the electronic component further includes one or more conductive through-holes each passing through the dielectric structure, wherein each conductive through-hole is aligned with a corresponding one of the one or more doped regions. In one embodiment, each of the one or more doped regions is spaced apart from the P-type composition and the N-type composition.

[0157] Yet another aspect of the present disclosure relates to a method (e.g., an electronic device manufacturing method). A diode is formed in an active region. The diode includes a P-type component embedded in a first portion of the active region, an N-type component embedded in a second portion of the active region, and an undoped component located between the P-type component and the N-type component. An interconnect structure is formed on a first side of the diode. Different portions of the interconnect structure are electrically coupled to the P-type component and the N-type component, respectively. One or more openings are etched in a dielectric structure disposed on a second side of the diode opposite the first side. A dopant material is implanted into the active region through the one or more openings. The one or more openings are filled with a conductive material. In one embodiment, the active region includes a stack of first and second semiconductor layers having different material compositions and interleaved with each other; and forming the diode includes implanting a P-type dopant into the first portion of the active region and implanting an N-type dopant into the second portion of the active region, such that each of the P-type dopant and the N-type dopant penetrates at least a subset of the stack of the first and second semiconductor layers. In one embodiment, the implantation includes implanting boron as the dopant material through the one or more openings. In one embodiment, the implantation is performed such that the dopant material implanted into the active region does not reach the P-type component or the N-type component of the diode. In one embodiment, the etching is performed such that each of the one or more openings is wider than the P-type component or the N-type component. In one embodiment, the etching is performed such that none of the one or more openings exposes the P-type component or the N-type component to the second side. In one embodiment, the diode is formed in a first portion of the active region, and the method further includes: forming a gate-all-around (GAA) transistor in at least the second portion of the active region; wherein the GAA transistor includes a source component / drain component, and the etching is part of an etching process that etches from the second side as a source through-hole opening / drain through-hole opening for the source component / drain component.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic component, characterized in that: include: A diode comprising a P-type region, an N-type region, and an undoped intrinsic region located between the P-type region and the N-type region; an interconnect structure on a first side of the diode; a plurality of conductive through vias located on a second side of the diode, the second side being different from the first side; as well as One or more doped regions are disposed between the diode and the conductive through-via.

2. The electronic component according to claim 1, wherein The one or more doped regions are doped with a P-type dopant.

3. The electronic component according to claim 1, wherein In the cross-sectional side view, each of the one or more doped regions has a lateral dimension wider than that of the P-type region or the N-type region.

4. The electronic component according to claim 1, wherein Also included are a first isolation structure and a second isolation structure; in: In a cross-sectional side view, the diode is located between the first isolation structure and the second isolation structure; and The one or more doped regions extend laterally from the first isolation structure to the second isolation structure.

5. The electronic component according to claim 1, wherein The one or more doped regions include a first doped region vertically aligned with the P-type region of the diode, and a second doped region vertically aligned with the N-type region of the diode.

6. The electronic component according to claim 1, wherein The invention also includes a dielectric layer located on the second side of the diode, wherein each of the conductive through-holes vertically passes through the dielectric layer.

7. The electronic component according to claim 1, wherein The undoped intrinsic region includes a plurality of first semiconductor layers and a plurality of second semiconductor layers, wherein the first semiconductor layers are interlaced with the second semiconductor layers.

8. The electronic component according to claim 1, wherein The diode is formed in a first region of the device, and the device further includes a second region in which a plurality of gate-all-around (GAA) transistors are formed.

9. An electronic component, characterized in that: include: an active region comprising a plurality of alternating first and second semiconductor layers; a PIN diode formed in the active region, the PIN diode including a P-type component, an N-type component, and an undoped component located between the P-type component and the N-type component; a first conductive contact and a second conductive contact on a first side of the PIN diode, wherein the first conductive contact and the second conductive contact are electrically coupled to the P-type component and the N-type component, respectively; a dielectric structure on a second side of the PIN diode opposite the first side; as well as One or more doped regions are located between the PIN diode and the dielectric structure, wherein each of the one or more doped regions includes a P-type dopant.

10. The electronic component according to claim 9, wherein Also included are one or more conductive through-vias each passing through the dielectric structure, wherein each of the conductive through-vias is aligned with a corresponding one of the one or more doped regions.

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