Multi-protocol combinable control equipment based on FPGA high-speed IO

Abstract

The utility model discloses multi-protocol combinable control equipment based on FPGA high-speed IO. The multi-protocol combinable control equipment comprises an MCU, an FPGA module, a QSPI NOR module, a QSPI channel control module, a fan, an EEPROM module, a URAT serial port module, an EMMC module and a peripheral module. The QSPI NOR module is connected with the MCU and the FPGA module through the QSPI channel control module, and the FPGA module is connected with a PCIe Slot connector, an ASM connector and a QSFP28 connector. According to the application, the MCU module is connected with the EEPROM module, the URAT serial port module and the EMMC module, so that wide compatibility in a multi-protocol environment is ensured; by introducing the FPGA module and combining with the multi-protocol high-speed interface, extremely high resource scheduling capability can be provided in a high-concurrency and big data processing scene, and the overall performance of the system is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of control equipment, and particularly relates to a multi-protocol combinable control equipment based on FPGA high-speed IO. BACKGROUND

[0002] At present, with the rapid development of artificial intelligence and large-scale model training, the demand for computing resources is increasing, especially in high-concurrency and big data processing scenarios. How to efficiently manage and integrate various computing resources has become a problem to be solved. Although resource pooling technology has been applied in existing systems, it is usually limited to a single protocol or hardware platform, which makes the resource integration efficiency not high and it is difficult to realize cross-protocol resource sharing in a complex multi-protocol environment.

[0003] The existing resource management and control equipment mainly schedules and transmits resources through independent protocols, such as PCIe, Ethernet and QSFP protocols, which have been widely used in high-bandwidth resource transmission and management. However, the interoperability and compatibility between different protocols are poor, and the existing technology is difficult to balance the efficient switching and resource integration of multiple protocols in high-speed transmission scenarios. UTILITY MODEL CONTENT

[0004] Therefore, the present application provides a multi-protocol combinable control equipment based on FPGA high-speed IO to solve the problem of poor interoperability and compatibility between different protocols in the prior art, which is difficult to balance the efficient switching and resource integration of multiple protocols in high-speed transmission scenarios.

[0005] In order to achieve the above purpose, the present application provides the following technical scheme:

[0006] A multi-protocol combinable control equipment based on FPGA high-speed IO, comprising an MCU, an FPGA module, a QSPI NOR module, a QSPI channel control module, a fan, an EEPROM module, a URAT serial port module, an EMMC module and a peripheral module;

[0007] The fan, the EEPROM module, the URAT serial port module, the EMMC module and the peripheral module are connected with the MCU;

[0008] The QSPI NOR module is connected with the MCU and the FPGA module through the QSPI channel control module, the FPGA module is connected with a PCIe Slot connector, an ASM connector and a QSFP28 connector; the PCIe Slot connector is used for providing a plurality of standard PCIe Gen4_X8 Slot interfaces, the ASM connector is used for providing a plurality of standard PCIe Gen4_X8 ASM interfaces, and the QSFP28 connector is used for providing a plurality of standard QSFP28 interfaces.

[0009] Preferably, the number of the PCIe Gen4_X8 Slot interfaces is 8, the number of the PCIe Gen4_X8 ASM interfaces is 2, and the number of the QSFP28 interfaces is 4.

[0010] Preferably, the QSPI channel control module is a switch-gating device SW1, a first end of the switch-gating device SW1 is connected with the QSPI NOR module, a second end of the switch-gating device SW1 is connected with a SW-CTL port of the MCU, a third end of the switch-gating device SW1 is connected with a QSPI port of the MCU, and a fourth end of the switch-gating device SW1 is connected with the FPGA module.

[0011] Preferably, the model of the switch-gating device SW1 is RS0204YQ.

[0012] Preferably, the peripheral module is at least one of a PCIe Slot module, an ASM module and a QSFP28 module.

[0013] Preferably, the FPGA module is further connected with a JTAG bus and a QSPI bus respectively.

[0014] Preferably, the control device further comprises a power button, and the power button is connected with the MCU.

[0015] Preferably, the control device further comprises an RJ45 connector, and the RJ45 connector is connected with the MCU.

[0016] Compared with the prior art, the application has at least the following beneficial effects:

[0017] The application provides a multi-protocol combinable control device based on FPGA high-speed IO, which comprises an MCU, an FPGA module, a QSPI NOR module, a QSPI channel control module, a fan, an EEPROM module, a URAT serial port module, an EMMC module and a peripheral module; the fan, the EEPROM module, the URAT serial port module, the EMMC module and the peripheral module are connected with the MCU; the QSPI NOR module is connected with the MCU and the FPGA module through the QSPI channel control module, and the FPGA module is connected with a PCIe Slot connector, an ASM connector and a QSFP28 connector; the PCIe Slot connector is used for providing a plurality of standard PCIe Gen4_X8 Slot interfaces, the ASM connector is used for providing a plurality of standard PCIe Gen4_X8 ASM interfaces, and the QSFP28 connector is used for providing a plurality of standard QSFP28 interfaces. The multi-protocol combinable control device based on FPGA high-speed IO provided by the application can ensure wide compatibility in a multi-protocol environment through the connection of the MCU module with the EEPROM module, the URAT serial port module and the EMMC module; the FPGA module is introduced, and in combination with the QSPI NOR module and the QSPI channel control module, the FPGA module can realize rapid scheduling and sharing of different types of resources, especially in the high-bandwidth interfaces such as PCIe Gen4_X8 and QSFP28, the data transmission speed and the resource integration capability are significantly improved; in addition, the introduction of the FPGA module in combination with the multi-protocol high-speed interfaces (the PCIe Gen4_X8 Slot interface, the ASM interface and the QSFP28 interface) can provide extremely high resource scheduling capability in the high-concurrency and large-data processing scene, and the overall performance of the system is significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more directly illustrate the prior art and the application, the following exemplary drawings are given. It should be understood that the specific shapes, structures shown in the drawings should not be regarded as the limiting conditions for the implementation of the application; for example, based on the technical concepts disclosed in the application and the exemplary drawings, those skilled in the art can easily make routine adjustments or further optimization on the increase / decrease / ownership division of certain units (components), specific shapes, positional relationship, connection mode, size ratio relationship, etc.

[0019] Figure 1 The circuit principle block diagram of the multi-protocol combinable control device based on FPGA high-speed IO provided by the application is shown in the figure;

[0020] Figure 2 The circuit principle diagram of the FPGA minimum system provided by the application is shown in the figure;

[0021] Figure 3A circuit schematic diagram of an FPGA high-speed IO provided for the present application;

[0022] Figure 4 A circuit schematic diagram of a PCIe_X16 connector provided for the present application;

[0023] Figure 5 A circuit schematic diagram of an ASM connector provided for the present application;

[0024] Figure 6 A circuit schematic diagram of a QSFP28 connector provided for the present application;

[0025] Figure 7 A circuit schematic diagram of an MCU minimum system provided for the present application;

[0026] Figure 8 A circuit schematic diagram of an MCU and a row pin provided for the present application;

[0027] Figure 9 A circuit schematic diagram of an MCU and a fan provided for the present application;

[0028] Figure 10 A circuit schematic diagram of a switch strobe provided for the present application;

[0029] Figure 11 A circuit schematic diagram of an RJ45 connector provided for the present application. DETAILED DESCRIPTION

[0030] The present application will be further described in conjunction with the accompanying drawings.

[0031] In the description of the present application: unless otherwise specified, the meaning of "a plurality of" is two or more. The terms "first", "second", "third", etc. in the present application are intended to distinguish the objects referred to, and do not have special meanings in the technical connotation aspect (for example, should not be understood as emphasizing importance or order, etc.). The expressions "include", "contain", "have" and the like also mean "not limited to" (certain units, components, materials, steps, etc.).

[0032] The terms such as "upper", "lower", "left", "right", "middle" and the like cited in the present application are generally indications for the intuitive understanding of the relative positional relationship according to the drawings, and are not absolute limitations on the positional relationship in the actual product.

[0033] Figure 1 A circuit schematic diagram of a multi-protocol combinable control device based on FPGA high-speed IO provided for the present application. Please refer to Figure 1The application provides a multi-protocol combinable control device based on FPGA high-speed IO, which comprises an MCU, an FPGA module, a QSPI NOR module, a QSPI channel control module, a fan, an EEPROM module, a URAT serial port module, an EMMC module and a peripheral module.

[0034] The fan, the EEPROM module, the URAT serial port module, the EMMC module and the peripheral module are connected with the MCU.

[0035] The QSPI NOR module is connected with the MCU and the FPGA module through the QSPI channel control module, and the FPGA module is connected with a PCIe Slot connector, an ASM connector and a QSFP28 connector; the PCIe Slot connector is used for providing a plurality of standard PCIe Gen4_X8 Slot interfaces, the ASM connector is used for providing a plurality of standard PCIe Gen4_X8 ASM interfaces, and the QSFP28 connector is used for providing a plurality of standard QSFP28 interfaces.

[0036] Specifically, please refer to Figure 1 The MCU is responsible for the control unit of the whole motherboard, and the specific function of the MCU is as follows: the MCU controls the power-on and power-off of the whole motherboard through a PWRKEY signal; the MCU dynamically controls the fan speed of the motherboard through a PWM signal of the chip, so as to achieve the effect of balanced heat dissipation; the MCU can achieve the function of remotely updating the firmware version of the FPGA through a QSPI and SW interface; the MCU outputs the FPGA link training state and key information analysis through a UART serial port; the MCU externally connects an EMMC device through an SDIO signal to store a log file of key information; the MCU obtains the information of peripherals (PCIe Slot / ASM / QSFP28) through a group of IIC signals; and the MCU is connected with the FPGA through a general-purpose GPIO signal to observe the running state and special function development of the FPGA.

[0037] The FPGA module is responsible for the computing unit of the whole motherboard, and the specific function of the FPGA module is as follows: the FPGA module is debugged online through a JTAG interface; the FPGA module is instantiated into 8 standard PCIe Gen4_X8 Slots through GTY high-speed IO; the FPGA module is instantiated into 2 standard PCIe Gen4_X8 ASM interfaces through GTY high-speed IO; and the FPGA module is instantiated into 4 standard QSFP28 interfaces through GTY high-speed IO.

[0038] Specifically, Figure 2 A circuit schematic diagram of a minimum system of the application is provided. Please refer to Figure 2, the minimum system of PFGA includes JTAG bus, QSPI bus, M[2:0] signal, key GPIO and the like. The system adopts 2x5_2.54mm connector to access JTAG bus, which is used for online debugging of FPGA chip; the QSPI bus is connected with a 1GB QSPI Flash chip, which is used for solidifying FPGA logic program; the key IO processing mode of FPGA affects the normal start of FPGA, and the system adopts the mode of pull-up and pull-down resistance to selectively debug; the FPGA has two state pins, init and done, and the system connects a light emitting diode to each of the pins to observe the start state of the FPGA.

[0039] Figure 3 A circuit schematic diagram of FPGA high-speed IO is provided in the application. Please refer to Figure 3 , the FPGA has many high-speed IO resources, Figure 3 two groups of high-speed IO with X8 bit width, which can be instantiated into two standard PCIe_X8 signals, and the high-speed IO interfaces are respectively connected to PCIe Slot, ASM connector and QSFP28 connector, so as to realize the functions of multiple interfaces, multiple protocols and combination. As shown in Figure 3 , all data is respectively connected to PCIe Slot1 and PCIe Slot2, and all clock signals are connected to a clock chip on the board.

[0040] Figure 4 A circuit schematic diagram of PCIe_X16 connector is provided in the application. Please refer to Figure 4 , the high-speed signals are one-to-one corresponding, the P and N of TX signal need to be connected with 220nF AC coupling capacitor, P12V_SYS and P3V3_DEV power supply can provide power supply for the card, 100MHz clock signal can provide corresponding PCIe clock source for the board card, reset signal is used for resetting the card, and in-situ monitoring signal PRSNT is used for monitoring whether the slot is inserted with the card.

[0041] Figure 5 A circuit schematic diagram of ASM connector is provided in the application. Please refer to Figure 5 , the following is the ASM_x8 bit width connector instantiated by the high-speed IO of FPGA, as shown in the following figure, the connector completely conforms to the PCIe data transmission protocol, and the functions of device ID number and master-slave in-situ detection are added.

[0042] Figure 6 A circuit schematic diagram of QSFP28 connector is provided in the application. Please refer to Figure 6QSFP28 connector selection is 2x2 mode (one connector contains 4 optical ports), each optical port can provide 100G bandwidth capability, QSFP28 connector high-speed IO does not need to be AC coupled design, compared with PCIe slot and ASM connector, the hardware design is relatively simple. The reset signal, lpmode signal, modeselt signal and modeprsl signal of the connector are connected to the FPGA to control.

[0043] Figure 7 A circuit schematic diagram of an MCU minimum system is provided for the present application. Please refer to Figure 7 The MCU minimum system includes SWJTAG bus, QSPI bus, IIC bus, UART bus, EMMC bus, PWM, key GPIO and other resources, the SWJTAG bus is connected to the pin header for online updating the firmware version of the MCU, the QSPI bus is connected to the QSPI bus of the FPGA to realize the function of online upgrading the FPGA logic code; the EMMC bus is connected to an 8GB EMMC storage chip; the PWM signal is connected to the fan terminal on the mainboard to adjust the speed of the mainboard fan and realize the effect of adaptive cooling; the general GPIO signal is reserved to be connected to the GPIO pin of the FPGA to realize the data interaction between the MCU and the FPGA.

[0044] Figure 8 A circuit schematic diagram of an MCU and a pin header is provided for the present application. Please refer to Figure 8 The PWRKEY signal of the MCU is connected to a 2x4 pin header, and the signals on the pin header are connected to the power button outside the case through a cable, and by pressing the power button for 5 seconds, the power-on and power-off process of the whole mainboard can be controlled. The following is the circuit design of the MCU and the pin header.

[0045] Figure 9 A circuit schematic diagram of an MCU and a fan is provided for the present application. Please refer to Figure 9 The PWM signal of the MCU is connected to the 4-pin connector of the fan, and the fan speed of the mainboard is dynamically controlled according to the power consumption value of the FPGA, so as to achieve the effect of balanced cooling.

[0046] In the embodiment of the present application, different protocols share the bottom layer high-speed serial signal innovatively, different controllers are constructed on the same serial signal, so as to realize flexible construction of multiple protocols, and ensure the stability of the bottom layer signal, for example, the bottom layer structure based on PCIe, and at the same time, high flexibility is reserved at the protocol layer.

[0047] In the embodiments of the present application, a variety of heterogeneous servers can be built, such as GPU servers and heterogeneous GPU servers. In this case, the control device can flexibly adapt to different application requirements and provide high-performance and highly scalable interconnection solutions.

[0048] In this application, the number of the PCIe Gen4_X8 Slot interfaces is 8, the number of the PCIe Gen4_X8ASM interfaces is 2, and the number of the QSFP28 interfaces is 4.

[0049] In the present application, the QSPI channel control module switch enabler SW1, the first end of the switch enabler SW1 is connected to the QSPI NOR module, the second end of the switch enabler SW1 is connected to the SW-CTL port of the MCU, the third end of the switch enabler SW1 is connected to the QSPI port of the MCU, and the fourth end of the switch enabler SW1 is connected to the FPGA module.

[0050] Figure 10 For a circuit diagram of a switch gate provided in this application, please refer to Figure 10 The motherboard has been designed to remotely upgrade the FPGA firmware. By connecting the SPI interface of the MCU to a GPIO selection switch chip, the BIOS upgrade path is selectively switched through the high and low levels of the SW signal. When the SW signal is low, the FPGA can directly access the contents of the QSPI Flash. When the SW signal is high, the MCU can access and remotely upgrade the FPGA firmware version information.

[0051] In this application, the model of the switch selector SW1 is RS0204YQ.

[0052] In this application, the peripheral module is at least one of a PCIe Slot module, an ASM module, and a QSFP28 module.

[0053] In the present application, the FPGA module is also connected to the JTAG bus and the QSPI bus respectively.

[0054] In the present application, the control device further includes a power button, which is connected to the MCU.

[0055] In the present application, the control device further includes an RJ45 connector, and the RJ45 connector is connected to the MCU.

[0056] Figure 11 For a circuit diagram of an RJ45 connector provided in this application, please refer to Figure 11The mainboard is integrated with a 2x1 RJ45 connector, which is respectively a uart and a 100M network interface, and signals are led out by an MCU controller, the uart signal is used for debug of the FPGA in the running process, and the 100M network is used for remote debug of the FPGA.

[0057] In the embodiments of the present application, the general server can be connected to the control device through the ASM interface, realizing interconnection of the server and the control device, the CPU can directly access peripheral resources below the FPGA, realizing expansion of mixed resources; the general server can also be connected to the control device through the QSFP28 interface, realizing interconnection of the server and the control device, the CPU can directly access peripheral resources of the FPGA through the QSFP28 interface, realizing expansion of mixed resources.

[0058] Memory pooling function: PCIe Slot can access CXL memory expansion card, realizing memory pooling and sharing of 8 memory expansion cards, aiming at expanding the memory capacity of the server itself and providing the performance of the server as a whole.

[0059] GPU interconnection function: PCIe Slot can access standard full-height full-length double-wide GPU card, realizing 8-way GPU parallel computing function of a single node, liberating the pressure of server CPU transaction processing and improving performance.

[0060] CPU interconnection function: PCIe Slot can access standard full-height full-length double-wide CPU computing card, realizing the function of multiple CPU interconnection and solving the problem of weak single CPU computing power.

[0061] Distributed storage: PCIe Slot can access memory expansion card and SSD expansion card, realizing the function of CPU directly obtaining data from memory, in addition, data in the memory can be backed up to the SSD expansion card, which is more efficient and faster, and is suitable for business needs of big data storage.

[0062] The technical features of the above embodiments can be combined in any manner (as long as the combination of the technical features does not exist contradictions), in order to make the description simple, not all possible combinations of the technical features in the above embodiments are described; these embodiments not explicitly written should also be considered as the scope of the present application.

Claims

1. A multi-protocol combinable control device based on FPGA high-speed IO, characterized in that: Including MCU, FPGA module, QSPI NOR module, QSPI channel control module, fan, EEPROM module, URAT serial port module, EMMC module and peripheral modules; The fan, the EEPROM module, the URAT serial port module, the EMMC module and the peripheral module are all connected to the MCU; The QSPI NOR module is connected to the MCU and the FPGA module through the QSPI channel control module, and the FPGA module is connected with a PCIe Slot connector, an ASM connector and a QSFP28 connector; the PCIe Slot connector is used to provide multiple standard PCIe Gen4_X8 Slot interfaces, the ASM connector is used to provide multiple standard PCIe Gen4_X8 ASM interfaces, and the QSFP28 connector is used to provide multiple standard QSFP28 interfaces.

2. A multi-protocol combinable control device based on FPGA high-speed IO according to claim 1, characterized in that: The number of the PCIe Gen4_X8 Slot interfaces is 8, the number of the PCIe Gen4_X8 ASM interfaces is 2, and the number of the QSFP28 interfaces is 4.

3. The multi-protocol combinable control device based on FPGA high-speed IO according to claim 1, characterized in that: The QSPI channel control module switch gate SW1, the first end of the switch gate SW1 is connected to the QSPI NOR module, the second end of the switch gate SW1 is connected to the SW-CTL port of the MCU, the third end of the switch gate SW1 is connected to the QSPI port of the MCU, and the fourth end of the switch gate SW1 is connected to the FPGA module.

4. The multi-protocol combinable control device based on FPGA high-speed IO according to claim 3, characterized in that: The model of the switch selector SW1 is RS0204YQ.

5. The multi-protocol combinable control device based on FPGA high-speed IO according to claim 1, characterized in that: The peripheral module is at least one of a PCIe Slot module, an ASM module, and a QSFP28 module.

6. The multi-protocol combinable control device based on FPGA high-speed IO according to claim 1, characterized in that: The FPGA module is also connected to the JTAG bus and the QSPI bus respectively.

7. The multi-protocol combinable control device based on FPGA high-speed IO according to claim 1, characterized in that: The control device further includes a power button, which is connected to the MCU.

8. The multi-protocol combinable control device based on FPGA high-speed IO according to claim 1, characterized in that: The control device further includes an RJ45 connector, and the RJ45 connector is connected to the MCU.

Images