Integrated circuit chip packaging structure
The integrated circuit chip packaging structure with a multi-layer heat dissipation structure and a stabilizing mechanism solves the problem of insufficient heat dissipation in the traditional packaging structure, achieves efficient heat dissipation and stability of the chip, and extends the service life of the chip.
Patent Information
- Application Number
- CN202422674522.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-11-04
AI Technical Summary
Traditional packaging structures have limited heat dissipation paths, which causes heat accumulation in the chip during operation, affecting chip performance and service life, especially when the temperature rises rapidly during high-load operation.
A multi-layer heat dissipation structure and stabilization mechanism is adopted, including the first, second, and third heat dissipation layers and the chip carrier, combined with a shielding layer and a limit block, to quickly dissipate heat through heat conduction and prevent electromagnetic interference, thereby improving the stability and life of the chip.
Effectively reduce the chip operating temperature, improve the chip's service life and stability, prevent electromagnetic interference, and enhance the heat dissipation efficiency of the packaging structure.
Smart Images
Figure CN223450885U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to integrated circuit chip technical field, concretely is a kind of integrated circuit chip packaging structure. BACKGROUND
[0002] Integrated circuit is a kind of miniature electronic device or component, using certain process, the transistor, resistance, capacitor and inductance element and wiring interconnection required in a circuit are interconnected together, made on a small piece or several small pieces semiconductor wafer or dielectric substrate, then encapsulation in a tube shell, become the miniature structure with required circuit function, wherein all components have formed an integral whole in structure, make electronic component towards small, low power consumption, intelligent and high reliability, in the processing of chip, integrated circuit chip packaging structure needs to be used;
[0003] Traditional packaging structure is often limited in heat dissipation approach, resulting in heat accumulation in the working process of chip, influence chip performance and service life, traditional packaging structure can rapidly rise in high load operation Chip temperature, far higher than the normal working temperature range of chip, resulting in the problem of reducing service life of chip. UTILITY MODEL CONTENT
[0004] The utility model aims at providing a kind of integrated circuit chip packaging structure, achieve the purpose of solving the problem proposed in the above background technology.
[0005] To achieve the above object, the utility model provides the following technical scheme: a kind of integrated circuit chip packaging structure, including packaging box,
[0006] packaging cover is installed in the top of the packaging box;
[0007] fixedly installed in the bottom of the packaging cover is attached pad;
[0008] And the packaging assembly is arranged in the inner wall position of the packaging box;
[0009] The packaging assembly includes heat dissipation mechanism installed in the inner wall position of packaging box;
[0010] The inner wall position of the packaging box is installed with stabilizing mechanism, and the stabilizing mechanism is connected with heat dissipation mechanism.
[0011] Preferably, the heat dissipation mechanism includes first heat dissipation layer, the first heat dissipation layer is arranged in contact with the inner wall bottom of packaging box, the top of the first heat dissipation layer is arranged in contact with second heat dissipation layer, the top of the second heat dissipation layer is arranged in contact with third heat dissipation layer, the top of the third heat dissipation layer is arranged in contact with chip carrier, and the inner wall of the chip carrier is fixedly installed with shielding layer.
[0012] Preferably, the side wall of the chip carrier is in contact with the inner wall of the packaging box, the side wall of the third heat dissipation layer is in contact with the inner wall of the packaging box, and the side wall of the second heat dissipation layer is in contact with the inner wall of the packaging box.
[0013] Preferably, the inner wall of the chip carrier is in contact with the chip body, the side wall of the chip body is fixedly installed with the chip pin, the bottom of the chip pin penetrates the inner wall of the packaging box, the third heat dissipation layer, the second heat dissipation layer, the first heat dissipation layer and the packaging box in sequence, and extends to the bottom of the packaging box.
[0014] Preferably, the material of the shielding layer is silver-plated copper foil, the material of the chip carrier is ceramic, the material of the third heat dissipation layer is heat dissipation fin, the material of the second heat dissipation layer is heat dissipation gel, and the material of the first heat dissipation layer is copper heat dissipation plate.
[0015] Preferably, the stabilizing mechanism comprises a limiting block, one end of the stabilizing mechanism is fixedly connected with the inner wall of the shielding layer, the side wall of the limiting block is fixedly installed with an arc-shaped limiting strip, and the side wall of the arc-shaped limiting strip is in contact with the side wall of the chip body.
[0016] Preferably, the number of the limiting blocks is six, the shapes and sizes of the six limiting blocks are equal, and three of the limiting blocks are symmetrically arranged relative to the middle surface of the packaging box in the left-right direction.
[0017] The utility model provides a kind of integrated circuit chip packaging structure. With the following beneficial effects:
[0018] (1), the utility model discloses when operating personnel encapsulates chip body, first, first heat dissipation layer, second heat dissipation layer and third heat dissipation layer are sequentially installed to the inner wall of packaging box, then chip carrier is placed to the top of third heat dissipation layer, then operating personnel can directly place chip body to the inner wall of chip carrier, then encapsulation resin is added to the surface of chip body, finally, the position of encapsulation cover is installed, the position of chip body is encapsulated quickly, the shielding layer has good heat conductivity and insulation, which can effectively prevent external electromagnetic interference from entering the inside of the packaging structure, and also prevent internal signals from radiating interference outward, by setting multiple heat dissipation layers, heat generated by the chip can be quickly dissipated through heat conduction, reducing the temperature of chip body during work, improving the service life of chip body, solving the problem that the heat dissipation path of traditional packaging structure is often limited, leading to heat accumulation in the chip during work, affecting the performance and service life of the chip, and the temperature of the chip can quickly rise when the traditional packaging structure is running under high load, which is much higher than the normal working temperature range of the chip, resulting in reduced service life of the chip.
[0019] (2), the utility model discloses through the position of chip body of operating personnel through limiting block and arc limiting strip can effectively limit, improve the stability of chip body in the installation encapsulation process, conveniently operating personnel better use the device. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 It is appearance structure schematic diagram of the utility model;
[0021] Figure 2 It is explosion structure schematic diagram of the utility model;
[0022] Figure 3 It is cross section structure schematic diagram of the utility model;
[0023] Figure 4 It is structure schematic diagram of the utility model stabilizing mechanism.
[0024] In the drawing: 1, package box;2, package cover;3, adhere pad;4, package assembly;41, heat dissipation mechanism;411, first heat dissipation layer;412, second heat dissipation layer;413, third heat dissipation layer;414, chip carrier;415, shielding layer;42, stabilizing mechanism;421, limiting block;422, arc limiting strip;5, chip body;6, chip pin. DETAILED DESCRIPTION
[0025] In order to have more clear understanding to the technical features, object and effect of the utility model, now the specific implementation mode of the utility model is explained with the drawing.
[0026] Embodiment 1: the preferable implementation example of the integrated circuit chip encapsulation structure provided by the utility model as shown in Figures 1 to 4 The integrated circuit chip encapsulation structure includes package box 1,
[0027] Package cover 2 is installed at the top of package box 1;
[0028] Adhere pad 3 is fixedly installed at the bottom of package cover 2;
[0029] And package assembly 4 is arranged at the inner wall position of package box 1;
[0030] Package assembly 4 includes heat dissipation mechanism 41 installed at the inner wall position of package box 1;
[0031] The inner wall position of package box 1 is installed with stabilizing mechanism 42, and stabilizing mechanism 42 is connected with heat dissipation mechanism 41.
[0032] The heat dissipation mechanism 41 comprises a first heat dissipation layer 411, the first heat dissipation layer 411 is arranged on the inner wall of the bottom of the packaging box 1, the top of the first heat dissipation layer 411 is arranged with a second heat dissipation layer 412, the top of the second heat dissipation layer 412 is arranged with a third heat dissipation layer 413, the top of the third heat dissipation layer 413 is arranged with a chip carrier 414, and the inner wall of the chip carrier 414 is fixedly installed with a shielding layer 415.
[0033] In the embodiment, the side wall of the chip carrier 414 is arranged in contact with the inner wall of the packaging box 1, the side wall of the third heat dissipation layer 413 is arranged in contact with the inner wall of the packaging box 1, and the side wall of the second heat dissipation layer 412 is arranged in contact with the inner wall of the packaging box 1.
[0034] Further, the inner wall of the chip carrier 414 is arranged in contact with a chip body 5, the side wall of the chip body 5 is fixedly installed with a chip pin 6, the bottom of the chip pin 6 penetrates the inner wall of the packaging box 1, the first heat dissipation layer 411, the second heat dissipation layer 412, the third heat dissipation layer 413 and the chip carrier 414 in sequence, and extends to the bottom of the packaging box 1.
[0035] Further, the material of the shielding layer 415 is silver-plated copper foil, the material of the chip carrier 414 is ceramic, the material of the third heat dissipation layer 413 is heat dissipation fin, the material of the second heat dissipation layer 412 is heat dissipation gel, and the material of the first heat dissipation layer 411 is copper heat dissipation plate.
[0036] Embodiment 2: on the basis of embodiment 1, the preferred embodiment of the integrated circuit chip packaging structure provided by the utility model is Figures 1 to 4 As shown in the figure: the stabilizing mechanism 42 comprises a limiting block 421, one end of the stabilizing mechanism 42 is fixedly connected with the inner wall of the shielding layer 415, the side wall of the limiting block 421 is fixedly installed with an arc-shaped limiting strip 422, and the side wall of the arc-shaped limiting strip 422 is arranged in contact with the side wall of the chip body 5.
[0037] In the embodiment, the number of limiting blocks 421 is six, the shapes and sizes of the six limiting blocks 421 are equal, and three limiting blocks 421 are symmetrically arranged with respect to the middle surface of the packaging box 1 in the left-right direction.
[0038] In the process of specific implementation, when the operator encapsulates the chip body 5, first, the first heat dissipation layer 411, the second heat dissipation layer 412 and the third heat dissipation layer 413 are sequentially installed to the inner wall of the encapsulation box 1, then the chip carrier 414 is placed on the top of the third heat dissipation layer 413, then the operator can directly place the chip body 5 to the inner wall of the chip carrier 414, then the encapsulation resin is added to the surface of the chip body 5, finally, the position of the encapsulation cover 2 is installed, realizing the rapid encapsulation of the position of the chip body 5, the shielding layer 415 has good heat conductivity and insulation, which can effectively prevent external electromagnetic interference from entering the inside of the encapsulation structure, and also prevents internal signals from radiating interference outward, by setting multiple heat dissipation layers, the heat generated by the chip can be quickly dissipated through heat conduction, reducing the temperature of the chip body 5 when working, and improving the service life of the chip body 5.
[0039] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.
Claims
1. An integrated circuit chip packaging structure, comprising a packaging box (1), A packaging cover (2) mounted on the top of the packaging box (1); A fitting pad (3) fixedly mounted on the bottom of the packaging cover (2); and a packaging component (4) arranged on the inner wall of the packaging box (1); characterized in that: The packaging assembly (4) includes a heat dissipation mechanism (41) installed on the inner wall of the packaging box (1); A stabilizing mechanism (42) is installed on the inner wall of the packaging box (1), and the stabilizing mechanism (42) is connected to the heat dissipation mechanism (41).
2. The integrated circuit chip packaging structure according to claim 1, wherein: The heat dissipation mechanism (41) comprises a first heat dissipation layer (411), the first heat dissipation layer (411) being arranged in contact with the bottom of the inner wall of the packaging box (1), the top of the first heat dissipation layer (411) being arranged in contact with a second heat dissipation layer (412), the top of the second heat dissipation layer (412) being arranged in contact with a third heat dissipation layer (413), the top of the third heat dissipation layer (413) being arranged in contact with a chip carrier (414), and a shielding layer (415) being fixedly mounted on the inner wall of the chip carrier (414).
3. The integrated circuit chip packaging structure according to claim 2, wherein: The side wall of the chip carrier (414) is in contact with the inner wall of the packaging box (1), the side wall of the third heat dissipation layer (413) is in contact with the inner wall of the packaging box (1), and the side wall of the second heat dissipation layer (412) is in contact with the inner wall of the packaging box (1).
4. The integrated circuit chip packaging structure according to claim 3, wherein: The chip body (5) is provided in contact with the inner wall of the chip carrier (414), and the chip pins (6) are fixedly mounted on the side walls of the chip body (5). The bottom of the chip pins (6) sequentially penetrates the chip carrier (414), the third heat dissipation layer (413), the second heat dissipation layer (412), the first heat dissipation layer (411), and the inner wall of the packaging box (1), and extends to the bottom of the packaging box (1).
5. The integrated circuit chip packaging structure according to claim 3, wherein: The shielding layer (415) is made of silver-plated copper foil, the chip carrier (414) is made of ceramic, the third heat dissipation layer (413) is made of heat dissipation fins, the second heat dissipation layer (412) is made of heat dissipation gel, and the first heat dissipation layer (411) is made of a copper heat dissipation plate.
6. The integrated circuit chip packaging structure according to claim 1, wherein: The stabilizing mechanism (42) comprises a limiting block (421), one end of the stabilizing mechanism (42) is fixedly connected to the inner wall of the shielding layer (415), a side wall of the limiting block (421) is fixedly mounted with an arc-shaped limiting strip (422), and the side wall of the arc-shaped limiting strip (422) is arranged in contact with the side wall of the chip body (5).
7. The integrated circuit chip packaging structure according to claim 6, wherein: There are six limit blocks (421), and the six limit blocks (421) are all equal in shape and size. Three limit blocks (421) form a group and are symmetrically arranged relative to the middle surface of the packaging box (1) in the left and right directions.