Semiconductor element

Abstract

A semiconductor die and a method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source / drain region adjacent to the first gate structure, and a shared contact extending through the semiconductor fin to electrically connect to the source / drain region and the first gate structure. The conductive feature contacts the shared contact.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor element. BACKGROUND

[0002] Semiconductor elements are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor elements are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and using lithography to pattern the various material layers to form circuitry components and assemblies thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size. This allows more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise. SUMMARY

[0004] Embodiments of the present application provide a semiconductor element including a first interconnect structure, a second interconnect structure including a conductive feature, and an element layer between the first interconnect structure and the second interconnect structure. The element layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source / drain region adjacent to the first gate structure, and a shared contact extending through the semiconductor fin to electrically connect to the source / drain region and the first gate structure. The conductive feature contacts the shared contact.

[0005] Embodiments of the present application provide a semiconductor element including a first gate electrode, a second gate electrode, a source / drain region adjacent to the first gate electrode, a semiconductor fin on the source / drain region, the first gate electrode, and the second gate electrode, a shared contact extending through the semiconductor fin and connected to a backside of the first gate electrode and a backside of the source / drain region, a first gate contact extending through the semiconductor fin and connected to a backside of the second gate electrode, and a first interconnect structure on the first gate contact and the shared contact. The first interconnect structure includes a first conductive feature electrically connected to the shared contact and the first gate contact.

[0006] Based on the above, the utility model relates to a semiconductor element having front side and back side interconnect structures on the front side and back side of the element layer, respectively. Shared contacts connect the wires of the back side interconnect structure to both the gate structure and the source / drain regions at the back side of the element layer. In this way, the density of conductive contacts on the front side of the element layer is reduced, which can reduce shorting and parasitic capacitance between adjacent conductive contacts on the front side of the element layer, thereby improving the performance and long-term reliability of the semiconductor element. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure will be best understood with reference to the following detailed description together with the drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of clarity. It should be noted that the description and drawings merely illustrate the principles of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope.

[0008] FIG. 1 An example of a nano-FET in a three-dimensional view is shown, according to some embodiments.

[0009] FIG. 2 FIG. 3 FIG. 4 FIG. 5 FIG. 6A FIG. 6B FIG. 6C FIG. 7A FIG. 7B FIG. 7C FIG. 8A FIG. 8B FIG. 8C FIG. 9A FIG. 9B FIG. 9C FIG. 10A FIG. 10B FIG. 10C FIG. 11A FIG. 11B FIG. 11C FIG. 11D FIG. 12A FIG. 12B FIG. 12C FIG. 12D FIG. 12E FIG. 13A FIG. 13B FIG. 13C FIG. 14A FIG. 14B FIG. 14C FIG. 15A FIG. 15B FIG. 15C FIG. 16A FIG. 16B FIG. 16C FIG. 17A FIG. 17B ,​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​FIG. 17C FIG. 18A FIG. 18B FIG. 18C FIG. 19A FIG. 19B FIG. 19C FIG. 20A FIG. 20B FIG. 20C FIG. 21A FIG. 21B FIG. 21C FIG. 22A FIG. 22B FIG. 22C FIG. 23 FIG. 24 FIG. 25 FIG. 26 FIG. 27 FIG. 28 FIG. 29A FIG. 29B Figs. are intermediate stages in the fabrication of a semiconductor die including a nanostructure FET according to some embodiments.

[0010] FIG. 30A FIG. 30B Figs. are intermediate stages in the fabrication of a semiconductor die including a nanostructure FET according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of first and second features on top of each other in the following description can include embodiments in which the first and second features are formed directly contacting each other, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not directly contact each other.

[0012] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for explaining the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] ​​​​​​​​​​​​​​​​​​​​​​​​Various embodiments provide a semiconductor die having front-side and back-side interconnect structures on a front side and a back side, respectively, of a device layer. Conductive contacts extend between and electrically connect the front-side interconnect structure and the front side of the device layer and the back-side interconnect structure and the back side of the device layer. In particular, a shared contact connects a conductive line of the back-side interconnect structure to both a gate structure and a source / drain region at the back side of the device layer. In this way, the density of conductive contacts on the front side of the device layer is reduced, which can reduce shorting and parasitic capacitance between adjacent conductive contacts on the front side of the device layer, thereby improving the performance and long-term reliability of the semiconductor die.

[0014] Some embodiments discussed herein are set forth in the context of a semiconductor die including nanostructure field-effect transistors (nano-FETs). However, various embodiments can be applied to a die including other types of transistors (e.g., fin field effect transistors (FinFETs), vertical field-effect transistors (VFETs), complementary field-effect transistors (CFETs), planar transistors, or the like) instead of or in combination with nanostructure FETs.

[0015] FIG. 1An example of a nanosheet FET is shown in a three-dimensional view. The nanosheet FET includes nanosheets 55 (e.g., nanosheets, nanowires, or similar components) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), where the nanosheets 55 act as channel regions of the nanosheet FET. The nanosheets 55 can include p-type nanosheets, n-type nanosheets, or a combination thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, and the fins 66 can protrude above the adjacent STI regions 68. Although the STI regions 68 are illustrated / shown as separate from the substrate 50, the term “substrate” as used herein can refer to a separate semiconductor substrate or a combination of a semiconductor substrate and STI regions. Additionally, although a bottom portion of the fins 66 is shown as a single, continuous material with the substrate 50, the bottom portion of the fins 66 and / or the substrate 50 can include a single material or multiple materials. In this context, a fin 66 refers to a portion that extends between adjacent STI regions 68.

[0016] A gate dielectric layer 100 is over a top surface of the fins 66 and along top surfaces, sidewalls, and bottom surfaces of the nanosheets 55. A gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fins 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0017] FIG. 1 Reference cross-sections used in later figures are further illustrated. Reference cross-section A-A’ is along a longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to a current flow direction between the epitaxial source / drain regions 92 of the nanosheet FET. Reference cross-section B-B’ is parallel to the reference cross-section A-A’ and extends through the epitaxial source / drain regions 92 of multiple nanosheet FETs. Reference cross-section C-C’ is perpendicular to the reference cross-section A-A’ and parallel to a longitudinal axis of the fins 66 of the nanosheet FET and in a direction, for example, perpendicular to a current flow direction between the epitaxial source / drain regions 92 of the nanosheet FET. Reference cross-section D-D’ is parallel to the reference cross-section C-C’ and extends through the gate electrodes 102 of multiple nanosheet FETs. For clarity, the reference cross-sections are referred to in later figures.

[0018] Some embodiments discussed herein are discussed in the context of a nanoscale FET formed using a gate-last process. In other embodiments, a gate-first process can also be used. In addition, some embodiments contemplate the use of a planar device (e.g., a planar FET) or a FinFET.

[0019] FIG. 2 to FIG. 29B FIG. 1 is a diagram of an intermediate stage in the manufacture of a semiconductor die including a nanoscale FET according to some embodiments. FIG. 2 FIG. 3 FIG. 4 FIG. 5 FIG. 6A FIG. 7A FIG. 8A FIG. 9A FIG. 10A FIG. 11A FIG. 12A FIG. 13A FIG. 14A FIG. 15A FIG. 16A FIG. 17A FIG. 18A FIG. 19A FIG. 20A FIG. 21A and FIG. 22A show cross-sectional views along the reference cross-section A-A' shown in FIG. 1. FIG. 1 FIG. 6B FIG. 7B FIG. 8B FIG. 9B FIG. 10B FIG. 11B FIG. 12B FIG. 12D FIG. 13B FIG. 14B FIG. 15B FIG. 16B FIG. 17B FIG. 18B FIG. 19B FIG. 20B FIG. 21B and FIG. 22B show cross-sectional views along the reference cross-section B-B' shown in FIG. 1. FIG. 1 FIG. 7C FIG. 8C FIG. 9C FIG. 10C FIG. 11C FIG. 11D FIG. 12C FIG. 12E FIG. 13C FIG. 14C FIG. 15C FIG. 16C FIG. 17C ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​、 FIG. 18C 、 FIG. 19C 、 FIG. 20C 、 FIG. 21C 、 FIG. 22C 、 FIG. 23 、 FIG. 24 、 FIG. 25 、 FIG. 26 、 FIG. 27 、 FIG. 28 and FIG. 29A shows a cross-sectional view along the reference cross-section C-C’ shown in FIG. 1 . FIG. 29B is a top view showing the region shown in FIG. 29B along the reference cross-section C-C’. FIG. 29A

[0020] In FIG. 2 , a substrate 50 is provided. The substrate 50 can be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as a multi-layered substrate or a graded substrate can also be used. In some embodiments, the semiconductor material of the substrate 50 can include silicon, germanium, compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or combinations thereof.

[0021] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type elements such as NMOS transistors (e.g., n-type nanowire FETs), and the p-type region 50P can be used to form p-type elements such as PMOS transistors (e.g., p-type nanowire FETs). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the divider 20), and any number of element features (e.g., other active elements, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and any number of p-type regions 50P can be provided.

[0022] Further in FIG. 2 ​In the embodiment of the present invention, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form the channel region of the nanostructure FET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form the channel region of the nanostructure FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form the channel region of the nanostructure FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructure FET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanostructure FET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanostructure FET in both the n-type region 50N and the p-type region 50P.

[0023] For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material different from the first semiconductor material such as silicon, carbon-doped silicon, or the like.

[0024] The first semiconductor material and the second semiconductor material can be materials that have a high etch selectivity with respect to each other. In this way, the first semiconductor layer 51 formed of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 formed of the second semiconductor material, thereby enabling the second semiconductor layer 53 to be patterned to form the channel region of the nanostructure FET. Similarly, in embodiments in which the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 formed of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 formed of the first semiconductor material, thereby enabling the first semiconductor layer 51 to be patterned to form the channel region of the nanostructure FET.

[0025] Reference is now made to the following drawings FIG. 3 , in accordance with some embodiments, the fins 66 are formed in the substrate 50 and the nanostructures 55 are formed in the multi-layered stack 64. In some embodiments, the nanostructures 55 and the fins 66 can be formed in the multi-layered stack 64 and the substrate 50, respectively, by etching trenches in the multi-layered stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), similar processes, or combinations thereof. The etching can be anisotropic. Forming the nanostructures 55 by etching the multi-layered stack 64 can further define the first nanostructures 52A-52C (collectively, first nanostructures 52) from the first semiconductor layer 51 and the second nanostructures 54A-54C (collectively, second nanostructures 54) from the second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 can be collectively referred to as the nanostructures 55.

[0026] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, one or more photolithography processes, including a double-patterning process or a multi-patterning process, can be used to pattern the fins 66 and nanostructures 55. Generally, a double-patterning process or a multi-patterning process combines photolithography processes with self-aligned processes, enabling the formation of patterns having a small pitch, for example, than would otherwise be obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0027] For illustrative purposes, FIG. 3 The fins 66 in the n-type region 50N and the fins 66 in the p-type region 50P are shown to have substantially equal widths. In some embodiments, the widths of the fins 66 in the n-type region 50N can be greater than or thinner than the fins 66 in the p-type region 50P. Further, although each of the fins 66 and nanostructures 55 are shown to have a uniform width throughout, in other embodiments, the fins 66 and / or nanostructures 55 can also have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 can have a different width and be shaped as a trapezoid.

[0028] In FIG. 4In the middle, a shallow trench isolation (STI) region 68 is formed adjacent to the fins 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, fins 66, and nanostructures 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide, nitride, similar material, or combination thereof), and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), similar methods, or combination thereof. Other insulating materials formed by any acceptable process can also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a FCVD process. Once the insulating material is formed, an anneal process can be performed. In embodiments, the insulating material is formed such that excess insulating material covers the nanostructures 55. Although the insulating material is shown as a single layer, some embodiments can utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can first be formed along the surfaces of the substrate 50, fins 66, and nanostructures 55. Thereafter, a fill material (e.g., discussed above) can be formed over the liner.

[0029] A removal process is then applied to the insulating material to remove the excess insulating material located over the nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polish (CMP), etch-back process, combination thereof, or similar process can be utilized. The planarization process exposes the nanostructures 55, which in turn causes the top surfaces of the nanostructures 55 to be flush with the top surface of the insulating material after the planarization process is completed.

[0030] The insulating material is then recessed to form the STI region 68. The insulating material is recessed such that the upper portions of the fins 66 in the n-type region 50N and p-type region 50P protrude from between the adjacent STI regions 68. In addition, the top surface of the STI region 68 can have a flat surface, convex surface, concave surface (e.g., dishing), or combination thereof as shown. The top surface of the STI region 68 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process such as an etching process selective to the material of the insulating material (e.g., etches the material of the insulating material faster than the materials of the fins 66 and nanostructures 55). For example, dilute hydrofluoric acid (dHF) can be used to remove the oxide.

[0031] The above with respect to FIG. 2 to FIG. 4The process set forth is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, a mask and epitaxial growth process can be used to form the fins 66 and / or nanostructures 55. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include the alternating semiconductor materials discussed above, such as the first and second semiconductor materials. In some embodiments in which the epitaxial structure is epitaxially grown, in-situ doping of the epitaxially grown material can be performed during growth, which can avoid the need for prior implantation and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0032] Additionally, the first semiconductor layer 51 (and resulting first nanostructures 52) and the second semiconductor layer 53 (and resulting second nanostructures 54) are shown and discussed herein as including the same materials in the p-type region 50P and the n-type region 50N for illustrative purposes only. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 can be different materials or can be formed in a different order in the p-type region 50P and the n-type region 50N.

[0033] Further in FIG. 4 embodiments having different well types, a photoresist or other mask (not shown separately) can be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fins 66 and STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist can be patterned to expose the p-type region 50P. The photoresist can be formed using a spin-on technique, and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity can be phosphorous, arsenic, antimony, or a similar material, implanted to a concentration in the range of about 10 13 atoms per cubic centimeter to about 10 14 atoms per cubic centimeter. After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0034] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin-on coating techniques, and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be carried out in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or similar materials implanted in the region to a concentration in a range of about 10 13 atoms per cubic centimeter to about 10 14 atoms per cubic centimeter. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0035] After implantation of the n-type region 50N and the p-type region 50P, annealing can be carried out to repair implantation damage and to activate the implanted p-type impurities and / or n-type impurities. In some embodiments, although in-situ doping can be used together with implantation doping, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation.

[0036] In FIG. 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed over the fins 66 and / or nanostructures 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 can be made of other materials with high etch selectivity relative to the etching of the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or a similar material. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55 for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 can be deposited so that the dummy dielectric layer 70 covers the STI region 68, thereby extending the dummy dielectric layer 70 between the dummy gate layer 72 and the STI region 68.

[0037] FIG. 6A to FIG. 18C Various additional steps in the fabrication of example nanostructured FET elements are shown. FIG. 6A to FIG. 18C Features in either the n-type region 50N or the p-type region 50P are shown. FIG. 6A to FIG. 6C In the embodiment, the mask layer 74 (see FIG. 5 ) is patterned to form a mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectric 71, respectively. Dummy gates 76 cover the corresponding channel regions of fins 66. The pattern of mask 78 can be used to physically separate each of dummy gates 76 from adjacent dummy gates 76. Dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the lengthwise direction of the corresponding fin 66.

[0038] exist FIG. 7A to FIG. 7C inFIG. 6A to FIG. 6C A first spacer layer 80 and a second spacer layer 82 are formed over the structures shown in FIG. 7A to FIG. 7C In one embodiment, the first spacer layer 80 is formed on: the top surface of the STI regions 68; the top surfaces and sidewalls of the fins 66, the nanostructures 55, and the mask 78; and the sidewalls of the dummy gates 76 and the dummy gate dielectric 71. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using a technique such as thermal oxidation, or the first spacer layer 80 can be deposited by CVD, ALD, or the like. The second spacer layer 82 can be formed of a material having a different etch rate than the material of the first spacer layer 80 (e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like), and the second spacer layer 82 can be deposited by CVD, ALD, or the like.

[0039] After the first spacer layer 80 is formed and before the second spacer layer 82 is formed, an implant for lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments having different element types, implants similar to those discussed above in FIG. 4 In one embodiment, a mask (e.g., photoresist) can be formed over the n-type regions 50N, exposing the p-type regions 50P, and impurities of the appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 of the p-type regions 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type regions 50P, exposing the n-type regions 50N, and impurities of the appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 of the n-type regions 50N. The mask can then be removed. The n-type impurities can be any of the n-type impurities discussed previously, and the p-type impurities can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity concentration ranging from about 1 x 1014atoms / cubic centimeter to about 1 x 1016atoms / cubic centimeter. 15 19 In one embodiment, a mask (e.g., photoresist) can be formed over the n-type regions 50N, exposing the p-type regions 50P, and impurities of the appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 of the p-type regions 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type regions 50P, exposing the n-type regions 50N, and impurities of the appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 of the n-type regions 50N. The mask can then be removed. The n-type impurities can be any of the n-type impurities discussed previously, and the p-type impurities can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity concentration ranging from about 1 x 1014atoms / cubic centimeter to about 1 x 1016atoms / cubic centimeter.

[0040] In one embodiment, a mask (e.g., photoresist) can be formed over the n-type regions 50N, exposing the p-type regions 50P, and impurities of the appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 of the p-type regions 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type regions 50P, exposing the n-type regions 50N, and impurities of the appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 of the n-type regions 50N. The mask can then be removed. The n-type impurities can be any of the n-type impurities discussed previously, and the p-type impurities can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity concentration ranging from about 1 x 1014atoms / cubic centimeter to about 1 x 1016atoms / cubic centimeter. FIG. 8A to FIG. 8C ​In some embodiments, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacers 81 and the second spacers 83. As will be discussed in more detail below, the first spacers 81 and the second spacers 83 are used to self-align subsequently formed source / drain regions and to protect sidewalls of the fins 66 and / or the nanowires 55 during subsequent processing. Suitable etching processes, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like, can be used to etch the first spacer layer 80 and the second spacer layer 82. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, thereby enabling the first spacer layer 80 to act as an etch stop when the second spacer layer 82 is patterned and enabling the second spacer layer 82 to act as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, with the first spacer layer 80 acting as an etch stop, where the remaining portions of the second spacer layer 82 form the second spacers 83 as shown in FIG. 8B FIG. 3B. Thereafter, the second spacers 83 act as a mask while the exposed portions of the first spacer layer 80 are etched, thereby forming the first spacers 81 as shown in FIG. 8B and FIG. 8C FIG. 3C.

[0041] As shown in FIG. 8B FIG. 3B, the first spacers 81 and the second spacers 83 are disposed on sidewalls of the fins 66 and / or the nanowires 55. As shown in FIG. 8C FIG. 3B, in some embodiments, the second spacer layer 82 can be removed from over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, while the first spacers 81 are disposed on sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 71. In other embodiments, portions of the second spacer layer 82 can remain over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0042] It should be noted that the above disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences can also be used. For example, fewer or additional spacers can be utilized, different step sequences can be utilized (e.g., the first spacers 81 can be patterned prior to deposition of the second spacer layer 82), additional spacers can be formed and removed, and / or the like. Furthermore, different structures and steps can be used to form n-type elements and p-type elements.

[0043] In FIG. 9A to FIG. 9CIn some embodiments, a recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. Epitaxial source / drain regions will subsequently be formed in the recess 86. The recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. FIG. 9B As shown in FIG, the top surface of STI region 68 can be flush with the bottom surface of recess 86. In various embodiments, fin 66 can be etched such that the bottom surface of recess 86 is disposed below the top surface of STI region 68 or a similar component. Recess 86 can be formed by etching fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (e.g., RIE, NBE, or a similar process). During the etching process to form recess 86, first spacer 81, second spacer 83, and mask 78 shield portions of fin 66, nanostructure 55, and substrate 50. A single etching process or multiple etching processes can be used to etch each layer of nanostructure 55 and / or fin 66. After recess 86 reaches the desired depth, a timed etching process can be used to terminate the etching.

[0044] exist FIG. 10A to FIG. 10C In the embodiment, the layer formed of the first semiconductor material of the multilayer stack 64 (eg, the first nanostructure 52) is etched to expose a portion of the sidewall of the recess 86 to form a sidewall recess 88. FIG. 10C The sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are shown as straight, however, the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process, such as a wet etch or similar process. In embodiments where the first nanostructure 52 comprises, for example, SiGe, and the second nanostructure 54 comprises, for example, Si or SiC, the sidewalls of the first nanostructure 52 may be etched using a dry etch process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or a similar material.

[0045] exist FIG. 11A to FIG. 11D In the embodiment, a first inner spacer 90 is formed in the sidewall recess 88. The first inner spacer 90 can be formed by FIG. 10A to FIG. 10C. A first inner spacer 90 is formed by depositing an inner spacer layer (not separately shown) over the structure shown in . The first inner spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions and epitaxial material will be formed in the recess 86, while the first nanostructure 52 will be replaced with a corresponding gate structure. The inner spacer layer can be deposited by a conformal deposition process such as CVD, ALD, or the like. While any suitable material (e.g., a low dielectric constant (low-k) material having a k value of less than approximately 3.5) can be used, the inner spacer layer can include a material such as silicon nitride or silicon oxynitride. The inner spacer layer can then be anisotropically etched to form the first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown aligned with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 can extend beyond the sidewalls of the second nanostructure 54 or can be recessed from the sidewalls of the second nanostructure 54.

[0046] In addition, despite FIG. 11C The outer sidewall of the first inner spacer 90 is shown as straight, however, the outer sidewall of the first inner spacer 90 may be concave or convex. As an example, FIG. 11D An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. The inner spacer layer can be etched by an anisotropic etching process (such as RIE, NBE, or the like). The first inner spacer 90 can be used to prevent subsequent etching processes (such as etching processes for forming gate structures) from affecting subsequently formed source / drain regions (such as those described below). FIG. 12A to FIG. 12E The epitaxial source / drain regions 92) discussed above cause damage.

[0047] exist FIG. 12A to FIG. 12E In the embodiment of the present invention, a semiconductor layer 91, a bottom spacer 93, and an epitaxial source / drain region 92 are formed in the recess 86. The semiconductor layer 91 may be formed on the fin 66. The semiconductor layer 91 may contact the sidewalls of the first inner spacer 90 on the first nanostructure 52A. The bottom surface of the semiconductor layer 91 may be disposed below the bottom surface of the first inner spacer 90 on the first nanostructure 52A. The top surface of the semiconductor layer 91 may be disposed below the top surface of the first inner spacer 90 on the first nanostructure 52A. Therefore, the semiconductor layer 91 may not be located on the sidewalls of the second nanostructure 54. The semiconductor layer 91 may be formed of a semiconductor material selected from a candidate semiconductor material of the substrate 50, which may be grown by an epitaxial growth process (e.g., VPE, MBE, or the like). A timed epitaxial growth process may be used to grow the semiconductor layer 91 to a specific height.

[0048] A bottom spacer 93 is formed over the semiconductor layer 91. The bottom spacer 93 can be in contact with the first inner spacer 90 on the first nanostructure 52A. A bottom surface of the bottom spacer 93 can be disposed above a bottom surface of the first inner spacer 90 on the first nanostructure 52A. A top surface of the bottom spacer 93 can be disposed below a top surface of the first inner spacer 90 on the first nanostructure 52A. Thus, the bottom spacer 93 can not be located on the sidewall of the second nanostructure 54. The bottom spacer 93 can be formed by conformally forming one or more dielectric materials over the semiconductor layer 91 and then etching back the dielectric material(s). Acceptable dielectric materials can include silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, silicon carbonitride, silicon oxide, aluminum oxide, hafnium oxide, or the like, which can be formed by a deposition process such as CVD, ALD, or the like. Any acceptable etching process such as dry etching, wet etching, the like, or a combination thereof can be performed to pattern the dielectric material(s).

[0049] An epitaxial source / drain region 92 is then formed in the recess 86 and on the bottom spacer 93. In some embodiments, the epitaxial source / drain region 92 can exert stress on the second nanostructure 54, thereby improving performance. As shown in FIG. 6, the epitaxial source / drain region 92 is formed in the recess 86 such that each dummy gate 76 is disposed between a respective adjacent pair of the epitaxial source / drain region 92. In some embodiments, the epitaxial source / drain region 92 is separated from the dummy gate 76 using the first spacer 81 and separated from the nanostructure 55 by an appropriate lateral distance using the first inner spacer 90, such that the epitaxial source / drain region 92 does not short circuit with a subsequently formed gate of the resulting nanostructure FET. FIG. 12C

[0050] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can include any acceptable material appropriate for an n-type nanostructure FET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can include a material that exerts tensile strain on the second nanostructure 54, such as silicon, silicon carbide, phosphorous-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 can have a surface that is raised from a respective upper surface of the nanostructure 55 and can have a facet.

[0051] ​An epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material appropriate for a p-type nanosheet FET. For example, if the first nanosheet 52 is silicon germanium, the epitaxial source / drain region 92 can include a material that exerts a compressive strain on the first nanosheet 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain region 92 can also have a surface that is raised from the corresponding surface of the multilayered stack 64, and can have facets.

[0052] Similar to the previously discussed process for forming a lightly doped source / drain region, the epitaxial source / drain region 92, the first nanosheet 52, the second nanosheet 54, and / or the substrate 50 can be implanted with a dopant to form a source / drain region, followed by annealing. The source / drain region can have an impurity concentration between about 1 x 1019atoms per cubic centimeter and about 1 x 1021atoms per cubic centimeter. The n-type impurity and / or the p-type impurity for the source / drain region can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain region 92 can be in-situ doped during growth. 19 21 The n-type impurity and / or the p-type impurity for the source / drain region can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain region 92 can be in-situ doped during growth.

[0053] As a result of the epitaxial process for forming the epitaxial source / drain region 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain region 92 has facets that expand laterally outward beyond the sidewalls of the nanosheet 55. In some embodiments, as shown by FIG. 12B these facets cause adjacent epitaxial source / drain regions 92 of the same nanosheet FET to merge. In other embodiments, as shown by FIG. 12D these facets cause adjacent epitaxial source / drain regions 92 of the same nanosheet FET to remain separate after the epitaxial process is complete. In the embodiments shown in FIG. 12B and FIG. 12D In some embodiments, the first spacers 81 can be formed to the top surface of the STI region 68, thereby preventing epitaxial growth. In some other embodiments, the first spacers 81 can cover portions of the sidewalls of the nanosheet 55, thereby further preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 can be adjusted to remove spacer material, enabling the epitaxial growth region to extend to the surface of the STI region 68.

[0054] The epitaxial source / drain region 92 can include one or more layers of semiconductor material. In some embodiments, as shown by FIG. 12C ​As shown in FIG. 1C, the epitaxial source / drain regions 92 include a first liner layer 92A on the sidewalls of the second nanostmctures 54, a second liner layer 92B on the first liner layer 92A, and a fill layer 92C on the second liner layer 92B. The first liner layer 92A, the second liner layer 92B, and the fill layer 92C can be formed of different semiconductor materials and / or can be doped to different dopant concentrations. The first liner layer 92A can be grown first, the second liner layer 92B can be grown on the first liner layer 92A, and the fill layer 92C can be grown on the second liner layer 92B.

[0055] FIG. 12E An embodiment is shown in which the sidewalls of the first nanostmctures 52 are concave, the outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from the sidewalls of the second nanostmctures 54. As shown in FIG. 1C, the epitaxial source / drain regions 92 can be formed in contact with the first inner spacers 90 and can extend beyond the sidewalls of the second nanostmctures 54. FIG. 12E

[0056] In some embodiments, the epitaxial source / drain regions 92 can be formed in contact with the first inner spacers 90 and can extend beyond the sidewalls of the second nanostmctures 54. FIG. 13A to FIG. 13C FIG. 12A to FIG. 12C A first interlayer dielectric (ILD) 96 is deposited over the structure shown in FIG. 1C. The first ILD 96 can be formed of a dielectric material, and the first ILD 96 can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or similar materials. Other insulating materials formed by any acceptable process can also be used. In some embodiments, a contact etch stop layer (CESL) 94 is provided between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacers 81. The CESL 94 can include a dielectric material having a different etch rate than the material of the overlying first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, or similar materials.

[0057] In some embodiments, the epitaxial source / drain regions 92 can be formed in contact with the first inner spacers 90 and can extend beyond the sidewalls of the second nanostmctures 54. FIG. 14A to FIG. 14C ​​In some embodiments, a planarization process (e.g., CMP) can be performed to level the top surface of the first ILD 96 with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 over the dummy gate 76 and portions of the first spacers 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacers 81, and the first ILD 96 are level within process variation. Thus, the top surface of the dummy gate 76 is exposed to the first ILD 96. In some embodiments, the mask 78 can remain, in which case the planarization process levels the top surface of the first ILD 96 with the top surfaces of the mask 78 and the first spacers 81.

[0058] In FIG. 15A to FIG. 15C In some embodiments, the dummy gate 76 and the mask 78, if present, are removed in one or more etching steps to form the third recess 98. Portions of the dummy gate dielectric 71 in the third recess 98 are also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacers 81. Each of the third recesses 98 exposes portions of the nanostructure 55 and / or overlying portions of the nanostructure 55 that will act as channel regions in the subsequently completed nanostructure FET. The portions of the nanostructure 55 that act as channel regions are disposed between adjacent pairs of the epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer when etching the dummy gate 76. After the dummy gate 76 is removed, the dummy gate dielectric 71 can be subsequently removed.

[0059] In FIG. 16A to FIG. 16C In some embodiments, the first nanostructure 52 is removed, extending the third recess 98. The first nanostructure 52 can be removed by performing an isotropic etching process (e.g., wet etching or the like) using an etchant selective to the material of the first nanostructure 52, while the second nanostructures 54, the substrate 50, and the STI regions 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructure 52.

[0060] In FIG. 17A to FIG. 17CIn some embodiments, the gate dielectric layer 100 and the gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the third recess 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, the CESL 94, the first spacers 81, and the STI region 68, and on the sidewalls of the first spacers 81 and the first inner spacers 90.

[0061] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, similar materials, or combinations thereof. For example, in some embodiments, the gate dielectric can include a silicon oxide layer and a metal oxide layer on top of the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high dielectric constant (high-k) dielectric material, and in such embodiments, the gate dielectric layer 100 can have a dielectric constant (k) value greater than about 7.0, and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 can be the same or different in the n-type region 50N and the p-type region 50P. The method of forming the gate dielectric layer 100 can include molecular-beam deposition (MBD), ALD, PECVD, and similar methods.

[0062] The gate electrode 102 is deposited on top of the gate dielectric layer 100, and fills the remaining portion of the third recess 98. The gate electrode 102 can include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although a single layer of the gate electrode 102 is shown in FIG. 17A and FIG. 17C Although a single layer of the gate electrode 102 is shown in Figs. 1A-1C, the gate electrode 102 can include any number of liner layers, any number of work function tuning layers, and a fill material. Any combination of layers making up the gate electrode 102 can be deposited in the n-type region 50N, between adjacent second nanostructures 54 in the second nanostructure 54, and between the second nanostructure 54A and the substrate 50, and any combination of layers making up the gate electrode 102 can be deposited in the p-type region 50P, between adjacent first nanostructures 52 in the first nanostructure 52.

[0063] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, thereby causing the gate dielectric layer 100 in each region to be formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, thereby causing the gate electrode 102 in each region to be formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, thereby causing the gate dielectric layer 100 to be different materials and / or to have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, thereby causing the gate electrode 102 to be different materials and / or to have different numbers of layers. When different processes are used, various masking steps can be used to mask and expose the appropriate regions.

[0064] After filling the third recess 98, a planarization process (e.g., CMP) can be performed to remove excess portions of the material of the gate dielectric layer 100 and the gate electrode 102 that are above the top surface of the first ILD 96. The remaining portions of the material of the gate electrode 102 and the gate dielectric layer 100 thus form the replacement gate structure of the resulting nanostructure FET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure."

[0065] In FIG. 18A to FIG. 18C the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed so that a recess is formed directly between the gate structure and the opposing portions of the first spacers 81. The recess is filled with a gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, or the like), followed by a planarization process to remove excess portions of the dielectric material that extend above the first ILD 96. The subsequently formed gate contact (e.g., the gate contact 114 discussed below with respect to FIG. 5) is formed to extend through the gate mask 104, thereby contacting the top surface of the recessed gate electrode 102. FIG. 20A to FIG. 20C The gate contact 114 is formed to extend through the gate mask 104, thereby contacting the top surface of the recessed gate electrode 102.

[0066] As further shown by FIG. 18A to FIG. 18C a second ILD 106 is deposited over the first ILD 96 and the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and the second ILD 106 can be deposited by any suitable method such as CVD, PECVD, or the like.

[0067] In FIG. 19A to FIG. 19CIn some embodiments, the fourth recess 108 is formed by etching through the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104. Some of the gate structures can not be exposed through the fourth recess 108. Desired ones of the gate structures (e.g., the gate structures that are not exposed through the fourth recess 108) can be connected to a conductive contact that can be formed later through the substrate 50 as described in more detail below. The fourth recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, or the like). In some embodiments, a first etching process can be used to etch the fourth recess 108 through the second ILD 106 and the first ILD 96; a second etching process can be used to etch the fourth recess 108 through the gate mask 104; and then a third etching process can be used to etch the fourth recess 108 through the CESL 94. A mask (e.g., photoresist) can be formed over the second ILD 106 and patterned to shield portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching processes can over-etch, and thus, the fourth recess 108 extends into the epitaxial source / drain regions 92 and / or some of the gate structures, and the bottom of the fourth recess 108 can be flush with (e.g., at the same level, or the same distance from the substrate 50) or can be lower (e.g., closer to the substrate 50) than the epitaxial source / drain regions 92 and / or some of the gate structures. Although the fourth recess 108 is shown as exposing the epitaxial source / drain regions 92 and some of the gate structures in the same cross-section, in various embodiments, the epitaxial source / drain regions 92 and some of the gate structures can be exposed in different cross-sections, reducing the risk of shorting the contacts formed later. FIG. 19C The fourth recess 108 is shown as exposing the epitaxial source / drain regions 92 and some of the gate structures in the same cross-section, however, in various embodiments, the epitaxial source / drain regions 92 and some of the gate structures can be exposed in different cross-sections, reducing the risk of shorting the contacts formed later.

[0068] After forming the fourth recess 108, a first silicide region 110 is formed over the epitaxial source / drain regions 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain regions 92 to form a silicide region or a germanide region (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) over the exposed portions of the epitaxial source / drain regions 92, and then performing a first thermal annealing process to form the first silicide region 110. In some embodiments, the first thermal annealing process is performed at a temperature of about 450 °C. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 can also be a germanide region or a germanosilicide region (e.g., a region containing both silicide and germanide).

[0069] In FIG. 20A to FIG. 20C some embodiments, source / drain contacts 112 and gate contacts 114 (which can also be referred to as conductive contacts) are formed in fourth recesses 108. Source / drain contacts 112 and gate contacts 114 can each include one or more layers, such as a barrier layer, a diffusion layer, and a fill material. For example, in some embodiments, source / drain contacts 112 and gate contacts 114 each include a barrier layer and a conductive material, and are each electrically connected to an underlying conductive feature (e.g., gate electrode 102 and / or first silicide region 110). Gate contacts 114 are electrically connected to gate electrode 102, and source / drain contacts 112 are electrically connected to first silicide region 110. The barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process (e.g., CMP) can be performed to remove excess material from the surface of second ILD 106.

[0070] Epitaxial source / drain regions 92, second nanostructures 54 (e.g., channel regions), and gate structures (including gate dielectric layer 100 and gate electrode 102) can be collectively referred to as transistor structures 109. Transistor structures 109 can be collectively disposed in a device layer, with first interconnect structures (e.g., frontside interconnect structures 120 discussed below with respect to FIG. 2) formed over a frontside of the device layer, and second interconnect structures (e.g., backside interconnect structures 136 discussed below with respect to FIG. 3) formed over a backside of the device layer. FIG. 21A to FIG. 21C Although the device layer is illustrated as having nanostructure FETs, other embodiments can include device layers having different types of transistors (e.g., planar FETs, FinFETs, thin film transistors (TFTs), or the like). FIG. 29A Although the device layer is illustrated as having nanostructure FETs, other embodiments can include device layers having different types of transistors (e.g., planar FETs, FinFETs, thin film transistors (TFTs), or the like).

[0071] FIG. 20A to FIG. 20C Some gate structures are shown as not being connected to gate contacts 114. As explained in more detail below, some gate structures (e.g., gate structures that are not connected to conductive contacts located on the frontside of transistor structures 109) can be connected to conductive contacts that will be subsequently formed on the backside of transistor structures 109. In this way, the density of conductive contacts located on the frontside of transistor structures 109 (including source / drain contacts 112 and gate contacts 114) can be reduced, which can reduce shorting and parasitic capacitance between adjacent conductive contacts on the frontside of transistor structures 109, thereby improving the performance and long-term reliability of the semiconductor die.

[0072] FIG. 20A to FIG. 20CSource / drain contacts 112 are shown extending to each of the epitaxial source / drain regions 92 located on the front side of the transistor structures 109 as an example. In some embodiments, as set out in more detail below, conductive contacts can be subsequently formed on the back side of the transistor structures 109 to electrically connect to the back side of some of the epitaxial source / drain regions 92. For such epitaxial source / drain regions 92, the source / drain contacts 112 located at the front side of the epitaxial source / drain regions 92 can be omitted.

[0073] FIG. 21A to FIG. 29B An intermediate stage of forming front-side interconnect structures and back-side interconnect structures on the transistor structures 109 is shown. The front-side interconnect structures and the back-side interconnect structures can each include conductive features that are electrically connected to the nanostructure FETs formed on the substrate 50 to provide functional circuitry. FIG. 21A to FIG. 29B The processes set out in the

[0074] In FIG. 21A to FIG. 21C In the second ILD 106, front-side interconnect structures 120 are formed. The front-side interconnect structures 120 can be referred to as front-side interconnect structures because they are formed on the front side of the transistor structures 109 (e.g., the side of the transistor structures 109 on which the active elements are formed). The front-side interconnect structures 120 can include one or more layers of first conductive features 122 formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 can comprise a dielectric material, such as a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like. The first dielectric layers 124 can be deposited using an appropriate process, such as CVD, ALD, PVD, PECVD, or the like. The first conductive features 122 can include wires and vias that interconnect the wires of each layer. The vias can extend through the respective ones of the first dielectric layers 124 to provide vertical connections between the wires of each layer. The first wires can be in contact with the source / drain contacts 112 and the gate contacts 114. The first conductive features 122 can be formed by any acceptable process, such as a damascene process, a dual damascene process, or the like.

[0075] In some embodiments, the first conductive features 122 can be formed using a damascene process in which the corresponding first dielectric layer 124 is patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired pattern of the first conductive features 122. An optional diffusion barrier and / or an optional adhesion layer can be deposited, and the trenches can then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the first conductive features 122 can be formed by depositing a seed layer of copper or a copper alloy and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or a similar process can be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124 and to planarize the surfaces of the first dielectric layer 124 and the first conductive features 122 for subsequent processing.

[0076] FIG. 21A to FIG. 21C Five layers of first conductive features 122 and first dielectric layers 124 are shown in the front-side interconnect structure 120. However, it should be understood that the front-side interconnect structure 120 may include any number of first conductive features 122 disposed in any number of first dielectric layers 124. The front-side interconnect structure 120 may be electrically connected to the gate contact 114 and the source / drain contacts 112 to form a functional circuit. In some embodiments, the functional circuit formed by the front-side interconnect structure 120 may include a logic circuit, a memory circuit, an image sensor circuit, or the like.

[0077] Likewise FIG. 21A to FIG. 21C As shown in FIG, a first bonding layer 152A may be deposited on the front-side interconnect structure 120. The first bonding layer 152A may be deposited by any suitable process (eg, PVD, CVD, ALD, or the like), and the first bonding layer 152A may facilitate subsequent processes (see FIG. FIG. 22A to FIG. 22C ) is bonded to the carrier substrate. The first bonding layer 152A may include an insulating material suitable for a subsequent dielectric-to-dielectric bonding process. Example materials for the first bonding layer 152A include silicon oxide (e.g., SiO2), silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, or the like. A planarization process (e.g., CMP or the like) may then be used to remove excess material from the surface of the first bonding layer 152A and planarize the surface of the first bonding layer 152A for subsequent processing.

[0078] exist FIG. 22A to FIG. 22CIn some embodiments, the carrier substrate 150 is bonded to the top surface of the front-side interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B. After bonding, the first bonding layer 152A and the second bonding layer 152B can be collectively referred to as the bonding layer 152. It should be understood that the bonding layer 152 can include an internal interface where the first bonding layer 152A and the second bonding layer 152B meet. The carrier substrate 150 can be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. The carrier substrate 150 can provide structural support during subsequent processing steps and in the completed device. The second bonding layer 152B can be deposited on the carrier substrate 150 by any suitable process, such as PVD, CVD, ALD, or the like. The second bonding layer 152B can include an insulating material suitable for a dielectric-to-dielectric bonding process. Example materials for the second bonding layer 152B include silicon oxide (e.g., S1O2), silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or the like. The second bonding layer 152B can have the same or a different thickness than the first bonding layer 152A.

[0079] After depositing the second bonding layer 152B on the carrier substrate 150, the carrier substrate 150 can be bonded to the front-side interconnect structure 120 using a suitable technique, such as dielectric-to-dielectric bonding or the like. The dielectric-to-dielectric bonding process can include applying a surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment can include a plasma treatment. The plasma treatment can be performed in a vacuum environment. After the plasma treatment, the surface treatment can further include a cleaning process (e.g., a wash with deionized water or the like) that can be applied to one or more of the bonding layer 152. The carrier substrate 150 is then aligned with the front-side interconnect structure 120 and pressed against each other to begin pre-bonding of the carrier substrate 150 to the front-side interconnect structure 120. The pre-bonding can be performed at room temperature (e.g., between about 21 °C and about 25 °C). After pre-bonding, an annealing process can be applied by heating the front-side interconnect structure 120 and the carrier substrate 150 to a temperature in the range of 150 °C to 500 °C, for example. The annealing process drives the formation of covalent bonds between the first bonding layer 152A and the second bonding layer 152B. In other embodiments, other bonding processes can also be used, such as ambient bonding, vacuum bonding, or the like.

[0080] Further in FIG. 22A to FIG. 22CIn the embodiment of the present invention, after bonding the carrier substrate 150 to the front-side interconnect structure 120, the device can be flipped so that the back side of the transistor structure 109 faces upward. The back side of the transistor structure 109 can refer to the side opposite to the front side of the transistor structure 109 on which the active components are formed.

[0081] FIG. 23 to FIG. 29B Additional steps in the fabrication of a semiconductor die are shown. Region 50A and region 50B of a semiconductor die are shown. Region 50A and region 50B may be along the same fin 66 or along different fins 66. Region 50A and region 50B may span the same gate electrode 102 or may span different gate electrodes 102.

[0082] exist FIG. 23 In the embodiment of the present invention, a thinning process may be applied to the backside of substrate 50 in regions 50A and 50B. The thinning process may include a planarization process (e.g., mechanical grinding, CMP, or the like), an etch-back process, a combination thereof, or the like. In addition, a portion of substrate 50 may remain above the gate structure (e.g., gate electrode 102 and gate dielectric layer 100), semiconductor layer 91, and bottom spacer 93. After the thinning process, substrate 50 may have a thickness T1, which may be the distance between the surface of the gate structure (e.g., gate electrode 102 and gate dielectric layer 100) and the backside surface of substrate 50. Thickness T1 may be in a range from about 5 nanometers to about 50 nanometers.

[0083] exist FIG. 24 In the embodiment of the present invention, a first backside dielectric layer 125 is formed on the backside surface of the substrate 50 in regions 50A and 50B, and a second backside dielectric layer 127 is formed on the first backside dielectric layer 125 in regions 50A and 50B. The first backside dielectric layer 125 and the second backside dielectric layer 127 can serve as hard masks in subsequent etching processes and can be formed of different materials. The first backside dielectric layer 125 can be formed of a first dielectric material (e.g., silicon nitride or the like), and the second backside dielectric layer 127 can be formed of a second dielectric material (e.g., silicon oxide or the like). The first backside dielectric layer 125 and the second backside dielectric layer 127 can be formed by multiple deposition processes (e.g., CVD, ALD, or the like). The first backside dielectric layer 125 can have a thickness T2 ranging from about 5 nanometers to about 15 nanometers. The second backside dielectric layer 127 can have a thickness T3 ranging from about 15 nanometers to about 45 nanometers.

[0084] exist FIG. 25In some embodiments, the openings 128G and 128S are formed to pass through the first backside dielectric layer 125, the second backside dielectric layer 127, and the substrate 50 in the regions 50A and 50B, respectively. The openings 128G can expose a backside surface of the gate electrode 102 (e.g., the gate electrode 102 that is not connected to the gate contact 114 on the front side of the transistor structure 109 in the region 50A). The openings 128S can expose a backside surface of the gate electrode 102 (e.g., the gate electrode 102 that is not connected to the gate contact 114 on the front side of the transistor structure 109). The openings 128S can also expose a backside surface of the bottom spacer 93 adjacent to the gate electrode 102 exposed by the openings 128S. The openings 128G and 128S can be formed simultaneously by a series of etching steps. For example, a first etching step can be used to remove portions of the first backside dielectric layer 125 and portions of the second backside dielectric layer 127. The first etching step can be a dry etching process with an etchant such as fluoromethane, tetrafluoromethane, hydrogen, combinations thereof, or the like. Then, a second etching step can be used to remove portions of the substrate 50 and portions of the semiconductor layer 91. The second etching step can be a dry etching process with an etchant such as chlorine, hydrobromic acid, oxygen, combinations thereof, or the like. Then, a third etching step can be used to remove portions of the gate dielectric layer 100. The third etching step can be a wet etching process with an etchant such as hydrofluoric acid or the like. The openings 128G can have a width Wl in a range from about 10 nm to about 20 nm. The openings 128S can have a width W2 in a range from about 30 nm to about 50 nm. The width W2 can be greater than the width Wl.

[0085] In FIG. 26In the embodiment of the present invention, contact spacers 131 are formed on the sidewalls of the opening 128G in region 50A and the sidewalls of the opening 128S in region 50B, respectively. In addition, the portion of the bottom spacer 93 exposed in the opening 128S is removed in region 50B. The contact spacers 131 can be formed of a dielectric material (e.g., silicon nitride or the like) and can be formed by a deposition process (e.g., CVD, ALD, or the like). Initially, the material of the contact spacers 131 can also be formed on the bottom surfaces of the openings 128G and 128S and then removed by an etching step. The etching step can be a dry etching process using an etchant such as fluoromethane, difluoromethane, nitrogen, hydrogen, a combination thereof, or the like. In region 50B, the etching step can also remove the bottom spacer 93 exposed in the opening 128S to expose the backside surface of the epitaxial source / drain region 92 below. The dry etching process can selectively etch the material of the contact spacers 131 and bottom spacers 93 at a faster rate than the material of the gate electrode 102 and epitaxial source / drain regions 92. For example, the bottom spacers 93 and the contact spacers 131 can be formed of the same dielectric material, and the etching can be selective to the dielectric material. Thus, the contact spacers 131 and bottom spacers 93 can be removed without significantly removing the material of the gate electrode 102 and epitaxial source / drain regions 92. In some embodiments, the dry etching process is an anisotropic etching process, and as a result of being masked by the contact spacers 131 during etching, portions of the bottom spacers 93 located directly below the contact spacers 131 on the sidewalls of the opening 128S remain after the dry etching process. Thus, the bottom spacers 93 can be locally removed by the dry etching process. The contact spacers 131 can have a thickness T4 in the range of approximately 2 nanometers to approximately 5 nanometers.

[0086] exist FIG. 27 In the embodiment, a second silicide region 129 is formed in region 50B on the exposed epitaxial source / drain region 92. In some embodiments, the second silicide region 129 completely covers the exposed backside surface of the epitaxial source / drain region 92. FIG. 19A to FIG. 19CThe second silicide region 129 can be formed of the same or similar material as the first silicide region 110, and can be formed by the same or similar process as the first silicide region 110. The second silicide region 129 can be formed using a second thermal anneal process. The second thermal anneal process can be performed at a lower temperature than the first thermal anneal process used to form the first silicide region 110. In some embodiments, the second thermal anneal process is performed at a temperature of about 400 °C. In this way, diffusion of material in the first conductive feature 122 of the front side interconnect structure 120 can be reduced during the second thermal anneal process. The second silicide region 129 can have a thickness T5 in a range from about 5 nm to about 10 nm. The thickness T5 of the second silicide region 129 can be different than the thickness of the first silicide region 110.

[0087] In FIG. 28In some embodiments, a gate contact 130G is formed in the opening 128G in the region 50A, and a shared contact 130S is formed in the opening 128S in the region 50B. The gate contact 130G and the shared contact 130S can also be referred to as conductive contacts. The gate contact 130G can be electrically connected to and can be in contact with the underlying gate electrode 102. The shared contact 130S can be electrically connected to (via the second silicide region 129) and can be in contact with the gate electrode 102 and the epitaxial source / drain regions 92. The gate contact 130G and the shared contact 130S can each include a barrier layer (not shown). The gate contact 130G and the shared contact 130S can each further include a conductive material such as tungsten, cobalt, ruthenium, titanium, titanium nitride, and a combination of tungsten, or the like. The material of the gate contact 130G and the shared contact 130S can be formed by a deposition process, a plating process, or the like. Then, a planarization process such as CMP can be performed to remove excess conductive material and the second backside dielectric layer 127. During the planarization process, the first backside dielectric layer 125 can be used as a CMP stop layer. After the planarization process, surfaces of the gate contact 130G, the shared contact 130S, the contact spacers 131, and the first backside dielectric layer 125 can be substantially coplanar with each other (within process variation). The gate contact 130G can have a width W3 in a range from about 4 nanometers to about 16 nanometers. In some embodiments, the width W3 is similar to a width of the underlying gate electrode 102. The shared contact 130S can have a width W4 in a range from about 24 nanometers to about 46 nanometers. The width W4 can be greater than the width W3. A first bottom surface of the shared contact 130S that is in contact with the gate electrode 102 can be spaced apart from a second bottom surface of the shared contact 130S that is in contact with the second silicide region 129 by a distance Dl. The distance Dl can be less than about 10 nanometers. In this way, voids in the shared contact 130S can be reduced or prevented during a deposition process, thereby improving long-term reliability of the semiconductor die.

[0088] In FIG. 29AIn some embodiments, backside interconnect structures 136 are formed on the first backside dielectric layers 125 and gate contacts 130G in region 50A, and on the first backside dielectric layers 125 and shared contacts 130S in region 50B. The backside interconnect structures 136 can be referred to as backside interconnect structures because they are formed on the backside of the element layer in which the transistor structures 109 are disposed (e.g., the side of the transistor structures 109 opposite the gate electrodes 102). In particular, the backside interconnect structures 136 can include a stack of second conductive features 140 formed in a second dielectric layer 138. The second conductive features 140 can be electrically connected to the gate contacts 130G and shared contacts 130S. The second conductive features 140 can include wires and vias. The first layer of wires can be in contact with the gate contacts 130G and shared contacts 130S. The second dielectric layer 138 can be formed of the same or similar materials using the same or similar processes as the first dielectric layer 124, and the second conductive features 140 can be formed of the same or similar materials using the same or similar processes as the first conductive features 122.

[0089] A passivation layer 144, an underbump metallization (UBM) 146, and external connections 148 are formed over the backside interconnect structures 136. The passivation layer 144 can include a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. Alternatively, the passivation layer 144 can include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer 144 can be deposited by a CVD, PVD, ALD, or the like. The UBM 146 is formed through the passivation layer 144 to the second conductive features 140 of the backside interconnect structures 136. The UBM 146 can include one or more layers of copper, nickel, gold, or the like formed by a plating process or the like. The external connections 148 (e.g., solder balls) are formed on the UBM 146. The forming of the external connections 148 can include placing solder balls on exposed portions of the UBM 146 and reflowing the solder balls. In some embodiments, the forming of the external connections 148 includes performing a plating step to form a solder region on the topmost wires and then reflowing the solder region. The UBM 146 and external connections 148 can be used to provide input / output connections to other electrical components (e.g., other element dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like). The UBM 146 and external connections 148 can also be referred to as backside input / output pads, which can provide signal, supply voltage, and / or ground connections to the nanostructure FETs described above.

[0090] Subsequently, a singulation process can be applied along the scribe lines to separate the individual semiconductor dies 200 located on the carrier substrate 150 from one another. In this manner, semiconductor dies 200 can be manufactured having front-side interconnect structures 120, element layers including transistor structures 109, and back-side interconnect structures 136. Regions 50A and 50B can be different regions on the same semiconductor die 200 or different regions on different semiconductor dies 200.

[0091] FIG. 29B A top view (e.g., layout) of regions 50A and 50B is shown. For illustration purposes, various features in regions 50A and 50B are omitted in FIG. 29B In region 50A, gate contacts 130G can be located between adjacent epitaxial source / drain regions 92. Gate contacts 130G can have a width W5 along the longitudinal direction of gate electrodes 102, and epitaxial source / drain regions 92 can have a width W6 along the longitudinal direction of gate electrodes 102. In some embodiments, width W5 is less than width W6. In region 50B, shared contacts 130S can have a width W7 along the longitudinal direction of gate electrodes 102, and epitaxial source / drain regions 92 can have a width W8 along the longitudinal direction of gate electrodes 102. In some embodiments, width W7 is less than width W8. In a top view, shared contacts 130S can be aligned with underlying fins 66. In a top view, gate contacts 130G can be aligned with underlying fins 66.

[0092] FIG. 30A and FIG. 30B is a diagram of a semiconductor die including a nanostructure FET according to some other embodiments. FIG. 30A shows a region along FIG. 1 is a cross-sectional view along the reference cross-section D-D’ shown in FIG. 30B is a top view showing a region along FIG. 30B the reference cross-section D-D’ in FIG. 30A is shown.

[0093] FIG. 30A shows a region 50C of semiconductor die 200 along FIG. 1 the reference cross-section D-D’ shown in FIG. 30A to FIG. 30B Region 50C shown can be formed in the same semiconductor die 200 as Figures 29A-29BThe regions 50A and 50B are shown on the same semiconductor die 200, where like numbers refer to like features. In embodiments where the regions 50A, 50B, and 50C are on the same semiconductor die 200, the regions 50A, 50B, and 50C can span the same gate electrode 102 or different gate electrodes 102. In the region 50C, the gate contact 130G extends through the first backside dielectric layer 125 and the STI region 68 to electrically connect to the gate electrode 102. The gate contact 130G in the region 50C can be formed of the same or similar materials using the same or similar processes as the gate contact 130G in the region 50A. In embodiments where the region 50A and the region 50C are on the same semiconductor die 200, the gate contact 130G in the region 50A and the gate contact 130G in the region 50C can be formed at the same time. The gate contact 130G in the region 50C can have a width W9 in a range from about 4 nanometers to about 16 nanometers. In some embodiments, the width W9 is similar to a width of the underlying gate electrode 102.

[0094] Figure 30B A top view (e.g., layout) of the region 50C is shown. For illustration purposes, various features in the region 50C are omitted in the top view. Figure 30B In the top view, the gate contact 130G can be aligned with the underlying STI region 68. The gate contact 130G can have a width W10 along a longitudinal direction of the gate electrode 102, and the epitaxial source / drain region 92 can have a width W11 along the longitudinal direction of the gate electrode 102. In some embodiments, the width W10 is less than the width W11.

[0095] Embodiments of the present disclosure have some advantageous features. By forming the gate contact 130G and the shared contact 130S on the backside of the transistor structure 109, the density of conductive contacts (including the source / drain contacts 112 and the gate contacts 114) on the front side of the transistor structure 109 can be reduced, which can reduce shorting and parasitic capacitance between adjacent conductive contacts on the front side of the transistor structure 109. Furthermore, voids in the shared contact 130S can be reduced or prevented. As such, the performance and long-term reliability of the semiconductor die 200 can be improved.

[0096] In an embodiment, an element includes: a first interconnect structure; a second interconnect structure including a conductive feature; and an element layer between the first interconnect structure and the second interconnect structure, the element layer including: a semiconductor fin; a first gate structure on the semiconductor fin; a source / drain region adjacent to the first gate structure; and a shared contact extending through the semiconductor fin to electrically connect to the source / drain region and the first gate structure, the conductive feature contacting the shared contact. In an embodiment, the element layer further includes: a second gate structure on the semiconductor fin; and a gate contact extending through the semiconductor fin to electrically connect to the second gate structure. In an embodiment, the element layer further includes: an isolation region adjacent to the semiconductor fin; the second gate structure on the isolation region and the semiconductor fin; and the gate contact extending through the isolation region to electrically connect to the second gate structure. In an embodiment, the element layer further includes: a contact spacer between the shared contact and the semiconductor fin. In an embodiment, the element further includes: a silicide region between the shared contact and the source / drain region. In an embodiment, a first bottom surface of the shared contact contacts the silicide region, a second bottom surface of the shared contact contacts the first gate structure, and the first bottom surface is spaced apart from the second bottom surface. In an embodiment, the element further includes: a dielectric layer between the semiconductor fin and the second interconnect structure, wherein the shared contact extends through the dielectric layer.

[0097] In an embodiment, an element includes: a first gate electrode; a second gate electrode; a source / drain region beside the first gate electrode; and a semiconductor fin on the source / drain region, the first gate electrode, and the second gate electrode; a shared contact extending through the semiconductor fin and connected to a backside of the first gate electrode and a backside of the source / drain region; a first gate contact extending through the semiconductor fin and connected to a backside of the second gate electrode; and a first interconnect structure on the first gate contact and the shared contact, wherein the first interconnect structure includes a first conductive feature electrically connected to the shared contact and the first gate contact. In an embodiment, the element further includes: a contact spacer separating the shared contact from the semiconductor fin. In an embodiment, the element further includes: an interlayer dielectric on a frontside of the source / drain region; a source / drain contact extending through the interlayer dielectric and connected to the frontside of the source / drain region; and a second interconnect structure on the source / drain contact, wherein the second interconnect structure includes a second conductive feature electrically connected to the source / drain contact. In an embodiment, the element further includes: a third gate electrode; an isolation region adjacent to the semiconductor fin and on the third gate electrode; and a second gate contact extending through the isolation region and connected to the third gate electrode. In an embodiment, in a top-down view, the first gate contact has a width in a longitudinal direction of the first gate electrode that is smaller than the source / drain region.

[0098] In an embodiment, a method includes forming a first interconnect structure over a front side of a first gate electrode, a front side of a second gate electrode, and a front side of a source / drain region disposed adjacent to the first gate electrode, the first gate electrode and the second gate electrode disposed on a semiconductor fin, the semiconductor fin protruding from an isolation region; forming a first dielectric layer on the semiconductor fin and the isolation region; forming a first opening through the first dielectric layer and the semiconductor fin, the first opening exposing a backside of the first gate electrode and a backside of the source / drain region; forming a shared contact in the first opening; and forming a second interconnect structure on the first dielectric layer, the second interconnect structure including a conductive feature connected to the shared contact. In an embodiment, the method further includes forming a second opening through the first dielectric layer and the semiconductor fin, the second opening exposing a backside of the second gate electrode; and forming a gate contact in the second opening. In an embodiment, the method further includes forming a second opening through the first dielectric layer and the isolation region, the second opening exposing a backside of the second gate electrode; and forming a gate contact in the second opening. In an embodiment, at least a portion of a second dielectric layer between the semiconductor fin and the source / drain region is removed after forming the first opening. In an example, the method further includes forming a silicide region in the first opening and the source / drain region prior to forming the shared contact. In an embodiment, in a top view, the shared contact is narrower than the source / drain region along a longitudinal direction of the first gate electrode. In an embodiment, the method further includes forming a contact spacer along a sidewall of the first opening prior to forming the shared contact. In an embodiment, the method further includes removing a second dielectric layer on a backside of the first gate electrode during forming the first opening.

[0099] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device, characterized in that: include: a first internal connection structure; a second interconnect structure comprising a conductive feature; as well as a component layer located between the first interconnect structure and the second interconnect structure, the component layer comprising: semiconductor fins; a first gate structure located on the semiconductor fin; a source / drain region adjacent to the first gate structure; and A shared contact extends through the semiconductor fin to be electrically connected to the source / drain regions and the first gate structure, and the conductive feature contacts the shared contact.

2. The semiconductor device according to claim 1, wherein The component layer further includes: a second gate structure located on the semiconductor fin; and A gate contact extends through the semiconductor fin to be electrically connected to the second gate structure.

3. The semiconductor device according to claim 1, wherein The component layer further includes: an isolation region adjacent to the semiconductor fin; a second gate structure located on the isolation region and the semiconductor fin; and A gate contact extends through the isolation region to be electrically connected to the second gate structure.

4. The semiconductor device according to claim 1, wherein Also includes: A silicide region is located between the shared contact and the source / drain region.

5. The semiconductor device according to claim 4, wherein A first bottom surface of the shared contact contacts the silicide region, a second bottom surface of the shared contact contacts the first gate structure, and the first bottom surface is spaced apart from the second bottom surface.

6. The semiconductor device according to claim 1, wherein Also includes: A dielectric layer is located between the semiconductor fin and the second interconnect structure, wherein the shared contact extends through the dielectric layer.

7. A semiconductor element, characterized in that: include: a first gate electrode; a second gate electrode; a source / drain region located next to the first gate electrode; a semiconductor fin located on the source / drain region, the first gate electrode, and the second gate electrode; a shared contact extending through the semiconductor fin and connected to a back side of the first gate electrode and a back side of the source / drain region; a first gate contact extending through the semiconductor fin and connected to a back side of the second gate electrode; and A first interconnect structure is located on the first gate contact and the shared contact, wherein the first interconnect structure includes a first conductive feature electrically connected to the shared contact and the first gate contact.

8. The semiconductor device according to claim 7, wherein Also includes: A contact spacer separates the shared contact from the semiconductor fin.

9. The semiconductor device according to claim 7, wherein Also includes: an interlayer dielectric located on the front side of the source / drain region; source / drain contacts extending through the interlayer dielectric and connected to the front side of the source / drain regions; as well as A second interconnect structure is located on the source / drain contact, wherein the second interconnect structure includes a second conductive feature electrically connected to the source / drain contact.

10. The semiconductor device according to claim 7, wherein Also includes: a third gate electrode; an isolation region adjacent to the semiconductor fin and located on the third gate electrode; as well as A second gate contact extends through the isolation region and is connected to the third gate electrode.

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