Acquisition chip shutdown wake-up circuit applied to energy storage field

Abstract

The utility model relates to the technical field of circuits, in particular to an acquisition chip shutdown wake-up circuit applied to the field of energy storage. The first switch circuit comprises an MOS tube Q1, the source electrode of the MOS tube Q1 is used for being connected to a power supply interface, and the drain electrode of the MOS tube Q1 is used for being connected to the power supply end of the acquisition chip; the second switch circuit comprises a triode Q2, a collector electrode of the triode Q2 is used for being connected to a grid electrode of the MOS tube Q1, an emitter electrode of the triode Q2 is used for being connected to a grounding end, and a base electrode of the triode Q2 is used for being connected to a power supply interface through the control circuit; and the control circuit is used for realizing on-off control between the base electrode of the triode Q2 and the power supply interface. By designing the shutdown wake-up circuit comprising the control circuit, the first switch circuit and the second switch circuit, the intelligent control of the power supply state of the acquisition chip is realized, so that the electric quantity loss is effectively reduced in the standby or transportation process, the battery is protected, and the system stability is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a circuit technical field, specifically, a kind of collection chip shutdown wake-up circuit applied in energy storage field. BACKGROUND

[0002] With the continuous development of energy storage technology, collection chip plays a vital role in battery management system (BMS). Collection chip is responsible for monitoring the voltage, current and other key parameters of battery module to ensure the safe and efficient operation of battery system.

[0003] However, in practical application, the power supply of collection chip (such as AFE chip) is usually directly derived from battery module. During long standby or transportation process, since collection chip needs to work continuously to monitor battery status, it will cause a lot of power loss. More seriously, continuous power consumption may cause the battery to enter the state of power loss, which will damage the battery. UTILITY MODEL CONTENTS

[0004] The utility model relates to a kind of collection chip shutdown wake-up circuit applied in energy storage field, which can overcome certain or some defects of prior art.

[0005] A kind of collection chip shutdown wake-up circuit applied in energy storage field, it includes control circuit, first switch circuit and second switch circuit;

[0006] The first switch circuit includes MOS tube Q1, the source of MOS tube Q1 is used to access power supply interface, the drain of MOS tube Q1 is used to access the power supply end of collection chip;

[0007] The second switch circuit includes triode Q2, the collector of triode Q2 is used to access the gate of MOS tube Q1, the emitter of triode Q2 is used to access ground terminal, the base of triode Q2 is used to access power supply interface by control circuit;

[0008] Control circuit is used to realize the on-off control between the base of triode Q2 and power supply interface.

[0009] The utility model, through control circuit intelligently controls the on-off between the base of triode Q2 and power supply interface, and then controls the conduction and cut-off of MOS tube Q1, to realize the accurate management of the power supply state of collection chip. This design can significantly reduce the power loss of collection chip during long standby or transportation process, avoid the state of power loss of battery, protect the battery, and at the same time improve the stability and reliability of the whole battery management system.

[0010] As preferred, the source and drain of MOS tube Q1 are connected in parallel with first resistor R1.

[0011] By connecting the first resistor R1 in parallel between the source and the drain of the MOS tube Q1, the voltage fluctuation of the MOS tube Q1 during operation can be effectively stabilized, providing real-time monitoring and feedback of the MOS tube switching state, while enhancing the reliability and stability of the entire circuit. The presence of the first resistor R1 can also share the voltage between the source and the drain to some extent, reducing the voltage stress on the MOS tube, thereby prolonging its service life and improving the overall performance of the circuit.

[0012] As a preferred, the second resistor R2 is connected in series between the drain of the MOS tube Q1 and the collector of the transistor Q2.

[0013] By connecting the second resistor R2 in series between the drain of the MOS tube Q1 and the collector of the transistor Q2, the circuit can more effectively manage voltage distribution, reducing the direct voltage stress between the drain of the MOS tube Q1 and the collector of the transistor Q2, thereby protecting these components from potential voltage surges.

[0014] As a preferred, the control circuit includes a control unit U1 for generating a control signal based on the received CAN communication signal.

[0015] By including the control unit U1 in the control circuit, the control circuit can intelligently respond to external CAN signals, accurately regulate the on-off state of the transistor Q2 according to the signal content, and further control the conduction and cutoff of the MOS tube Q1, achieving precise management of the power supply state of the acquisition chip. This not only improves the intelligence level of the circuit, but also ensures that the acquisition chip can quickly wake up when needed, and enter a low-power shutdown state when not needed, thereby effectively prolonging the service life of the battery,

[0016] As a preferred, the control circuit further includes an optocoupler OM1 for controlling the on-off between the base of the transistor Q2 and the power supply interface according to the control signal output by the control unit U1.

[0017] By the optocoupler OM1 in the control circuit according to the control signal output by the control unit U1, the electrical isolation and accurate on-off control between the base of the transistor Q2 and the power supply interface are achieved. This not only improves the response speed and accuracy of the shutdown and wake-up circuit of the acquisition chip in the energy storage system, but also significantly enhances the safety and stability of the system.

[0018] As a preferred, the primary side of the optocoupler OM1 is used to access the output terminal of the control unit U1; the secondary side of the optocoupler OM1 has a first port and a second port, the first port is used to access the power supply interface, and the second port is used to access the base of the transistor Q2.

[0019] The output signal of the control unit U1 is electrically connected to the base of the transistor Q2 through the optical coupling OM1, wherein the primary side of the optical coupling OM1 is connected to the output end of the control unit U1, the first port of the secondary side is connected to the power supply interface, and the second port is connected to the base of the transistor Q2, so that the accurate transmission of the control signal and the electrical isolation of the circuit are realized, and the safety and stability of the shutdown wake-up circuit of the collection chip in the energy storage system are significantly improved.

[0020] Preferably, the first port is connected in series with the power supply interface through the diode D1.

[0021] By connecting the diode D1 in series between the first port and the power supply interface, the diode D1 has unidirectional conductivity, effectively preventing the reverse flow of current, thereby avoiding circuit damage caused by power polarity errors or external interference, and improving the reliability and safety of the shutdown wake-up circuit of the collection chip in the energy storage system.

[0022] Preferably, the first port is connected in series with the diode D1 through the third resistor R3.

[0023] By connecting the third resistor R3 in series between the first port and the diode D1, the circuit can more effectively control the current flowing through the diode, preventing component damage or performance degradation caused by excessive current. The third resistor R3 plays a role in current limiting protection, enhancing the reliability and safety of the circuit.

[0024] Preferably, the second port is connected in series with the base of the transistor Q2 through the fourth resistor R4.

[0025] By connecting the fourth resistor R4 in series between the second port and the base of the transistor Q2, the circuit can accurately control the current flowing to the base of the transistor, thereby achieving fine adjustment of the switching state of the transistor. The fourth resistor R4 not only plays a role in current limiting protection, preventing damage to the transistor due to excessive current, but also enhances the stability and reliability of the circuit.

[0026] Preferably, the base of the transistor Q2 is connected to the ground through the fifth resistor R5.

[0027] By connecting the base of the transistor Q2 to the ground through the fifth resistor R5, when the control circuit does not send a wake-up signal, the base of the transistor Q2 can be ensured to remain in a stable low-level state. The fifth resistor R5 provides a stable pull-down current path, effectively pulling the base potential of the transistor Q2 to the ground potential (GND), thereby ensuring that the transistor Q2 is in a reliable off state when it does not need to be awakened. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a circuit schematic diagram of a collection chip shutdown wake-up circuit applied in the energy storage field in Example 1. DETAILED DESCRIPTION

[0029] In order to further understand the content of the present application, the application will be described in detail in conjunction with the embodiments. It should be understood that the embodiments are merely an explanation of the present application and not a limitation.

[0030] Embodiment 1

[0031] As shown in the application of the collection chip shutdown wake-up circuit in the energy storage field in the embodiment 1, it comprises a control circuit, a first switch circuit and a second switch circuit; Figure 1

[0032] The first switch circuit comprises a MOS tube Q1, the source of the MOS tube Q1 is used for connecting the power supply interface, and the drain of the MOS tube Q1 is used for connecting the power supply end of the collection chip.

[0033] The second switch circuit comprises a triode Q2, the collector of the triode Q2 is used for connecting the gate of the MOS tube Q1, the emitter of the triode Q2 is used for connecting the ground, and the base of the triode Q2 is used for connecting the power supply interface through the control circuit.

[0034] The control circuit is used for realizing the on-off control between the base of the triode Q2 and the power supply interface.

[0035] Specifically, the circuit mainly comprises a control circuit, a first switch circuit and a second switch circuit. The core of the first switch circuit is a MOS tube Q1 (specifically a PMOS tube), the source of which is connected with the power supply interface, and the drain of which is connected with the power supply end of the collection chip. Such design makes the MOS tube Q1 be able to serve as a main switch to accurately control the power supply of the collection chip. The second switch circuit comprises a triode Q2, the collector of which is connected with the gate of the MOS tube Q1, and the emitter of which is grounded. The base of the triode Q2 is connected with the power supply interface through the control circuit, so that the control circuit can indirectly control the gate voltage of the MOS tube Q1 by controlling the base of the triode Q2, thereby realizing the accurate control of the switch state of the MOS tube Q1.

[0036] In the embodiment, the first resistor R1 is connected in parallel between the source and the drain of the MOS tube Q1.

[0037] ​Specifically, the first resistor R1 is connected in parallel between the source and the drain of the MOS tube Q1, which not only significantly reduces the voltage stress of the MOS tube during operation, effectively preventing the damage of the components caused by excessive voltage, but also realizes real-time monitoring and control of the circuit current through the voltage drop generated by the first resistor R1. When the current abnormally increases, the voltage drop on the first resistor R1 will also increase accordingly, thereby triggering the protection mechanism in time to limit the further increase of the current and ensure the safe operation of the circuit. In addition, the first resistor R1 also provides a stable discharge path for the circuit, accelerates the charge release of the MOS tube in the off state, and significantly improves the response speed and overall stability of the circuit.

[0038] In this embodiment, the second resistor R2 is connected in series between the drain of the MOS tube Q1 and the collector of the transistor Q2.

[0039] Specifically, the second resistor R2 is connected in series between the drain of the MOS tube Q1 and the collector of the transistor Q2. It can effectively reduce the direct voltage stress between the drain of the MOS tube Q1 and the collector of the transistor Q2, thereby protecting these two key components from potential voltage impact. At the same time, the second resistor R2 also acts as a current limiting element, limiting the size of the current passing through the transistor Q2, preventing overheating or damage of the components caused by excessive current. In addition, by connecting the second resistor R2 in series, we also achieve more precise control of the circuit state, making the entire circuit more stable and reliable during switching.

[0040] In this embodiment, the control circuit includes a control unit U1, which is configured to generate a control signal based on a received CAN communication signal.

[0041] Specifically, the control unit U1 has the ability to receive and process CAN (Controller Area Network) communication signals, and then generate corresponding control signals according to these signals. The control unit U1 is built-in with a CAN communication interface, which can receive data frames from the CAN bus in real time. These data frames may contain key information from other control units, sensors or actuators of the vehicle, such as state monitoring data, control instructions, etc. The control unit U1 generates control signals based on the received CAN communication signals, which not only improves the integration and reliability of the system, but also realizes remote monitoring and control, enhances the flexibility and scalability of the system, and improves the response speed and real-time performance of the system.

[0042] In this embodiment, the control circuit further includes an optocoupler OM1, which is configured to control the on-off between the base of the transistor Q2 and the power supply interface according to the control signal output by the control unit U1.

[0043] Specifically, the optocoupler OM1 is an optoelectronic conversion device that can convert an electrical signal into an optical signal, and then convert the optical signal back into an electrical signal through the photoelectric effect. In this embodiment, the input end of the optocoupler OM1 receives a control signal from the control unit U1, and the output end is connected to the base of the transistor Q2. When the control unit U1 outputs a high-level signal, the light-emitting diode inside the optocoupler OM1 emits light, exciting the phototransistor to conduct, thereby forming a path between the base of the transistor Q2 and the power supply interface. Conversely, when the control unit U1 outputs a low-level signal, the light-emitting diode inside the optocoupler OM1 does not emit light, and the phototransistor is cut off, and the base of the transistor Q2 and the power supply interface are in a disconnected state. The design of the control circuit in this embodiment realizes precise control of the on-off of the base of the transistor Q2 and the power supply interface by introducing the key component optocoupler OM1.

[0044] In this embodiment, the primary side of the optocoupler OM1 is used to access the output end of the control unit U1; the secondary side of the optocoupler OM1 has a first port and a second port, the first port is used to access the power supply interface, and the second port is used to access the base of the transistor Q2.

[0045] Specifically, the primary side (input end) of the optocoupler OM1 is directly connected to the output end of the control unit U1 for receiving control signals; and the secondary side (output end) includes two ports, the first port is connected to the stable power supply interface, providing power for the subsequent circuit such as the transistor Q2; the second port is connected to the base of the transistor Q2, and the on-off state of the phototransistor in the secondary side of the optocoupler OM1 is used to accurately control the switching action of the transistor Q2. When the control unit U1 outputs a high-level signal to the primary side of the optocoupler OM1, the LED emits light, causing the phototransistor in the secondary side to conduct, and the base of the transistor Q2 and the power supply interface form a path, making Q2 saturated and conducting. Conversely, if the control unit U1 outputs a low-level signal, the LED does not emit light, the phototransistor is cut off, and the base of the transistor Q2 and the power supply interface are disconnected, and Q2 is cut off. In this way, the optocoupler OM1 not only realizes precise control of the switching action of the transistor Q2, but also ensures electrical isolation between the control circuit and the power supply interface.

[0046] In this embodiment, the first port and the power supply interface are connected in series with the diode D1.

[0047] Specifically, the anode of diode D1 is connected to the power supply interface, and the cathode is connected to the secondary side first port of optocoupler OM1. It can ensure that the current can only flow from the power supply interface to the secondary side of optocoupler OM1, realizing unidirectional conductivity. When the power supply interface provides a forward voltage, diode D1 is in a conducting state, allowing current to pass and flow to the secondary side of optocoupler OM1, providing necessary power for subsequent circuit components (such as transistor Q2). If the power supply interface provides a reverse voltage or a voltage lower than the conduction voltage (i.e. threshold voltage) of the diode, diode D1 is in a cut-off state, preventing current from passing, thereby protecting subsequent circuits from damage.

[0048] In this embodiment, the third resistor R3 is connected in series between the first port and diode D1.

[0049] Specifically, the third resistor R3 is connected in series between the first port and the anode of diode D1. When the power supply interface provides a voltage, the current first passes through the third resistor R3, then flows to the diode D1, and then enters the secondary side of the optocoupler OM1. The main function of the third resistor R3 is to limit the current size passing through the circuit, preventing damage to diode D1, optocoupler OM1 or subsequent circuits due to excessive current. By selecting an appropriate resistance value, the circuit can be ensured to operate within the normal operating range.

[0050] In this embodiment, the fourth resistor R4 is connected in series between the second port and the base of transistor Q2.

[0051] Specifically, the fourth resistor R4 is connected in series between the secondary side second port of optocoupler OM1 and the base of transistor Q2, forming a current-controlled "buffer zone". When the optocoupler OM1 secondary side photosensitive transistor is turned on, the current flows through the fourth resistor R4 to the base of the transistor Q2, thereby controlling the switching state of Q2. The main function of the protection resistor R4 is to limit the current size flowing to the base of the transistor Q2, avoiding excessive current causing component damage or abnormal operation, ensuring that the transistor Q2 can operate stably under safe working conditions.

[0052] In this embodiment, the base of the transistor Q2 is connected to the ground through the fifth resistor R5.

[0053] Specifically, one end of the fifth resistor R5 is connected to the base of the transistor Q2, and the other end is directly connected to the ground terminal (usually referred to as "ground" or "GND") of the circuit. When the transistor Q2 is in the off state, the base current is almost zero, and at this time the fifth resistor R5 provides a low impedance path to the ground for the base, which helps to quickly discharge and stabilize the base potential. When the transistor Q2 is turned on, although most of the current flows through the secondary side of the optocoupler OM1 and the second port to the base, the fifth resistor R5 still plays a role in limiting the base current and stabilizing the potential. Not only does it provide a stable potential reference point for the transistor Q2, but it also effectively controls its operating state, significantly improving the overall stability and reliability of the circuit.

[0054] According to the above description, the control circuit intelligently controls the on-off state between the base of the transistor Q2 and the power supply interface according to the received CAN communication signal. When the control unit U1 does not receive an external CAN communication signal, the optocoupler OM1 in the control circuit is in a non-conductive state, and at this time the base of the transistor Q2 is pulled down to the ground potential (GND) through the resistor R5, ensuring that the transistor Q2 is off, and thus the MOS tube Q1 is closed, the acquisition chip enters a low-power or shutdown state, effectively saving energy. On the contrary, when the MCU receives a CAN signal, the optocoupler OM1 is saturated and conducts, driving the transistor Q2 to saturate and conduct, and then passing through resistors R1 and R2 to make the MOS tube Q1 conduct, thereby providing normal power supply for the acquisition chip, realizing a fast and reliable wake-up function. The design of the shutdown wake-up circuit of the utility model not only improves the intelligent level of the circuit, but also significantly enhances the energy-saving effect and response speed of the system.

[0055] It is easy to understand that those skilled in the art can combine, split, recombine, etc. the embodiments of the present application on the basis of one or more embodiments provided in the present application to obtain other embodiments, and these embodiments do not exceed the protection scope of the present application.

[0056] The above describes the utility model and its embodiments in a schematic manner, which is not restrictive, and the embodiments shown are only part of the embodiments of the utility model, and the actual structure is not limited thereto. Therefore, if those skilled in the art are inspired by it, without departing from the creative purpose of the utility model, similar structural modes and embodiments can be designed without creativity, which should belong to the protection scope of the utility model.

Claims

1. A power-on wake-up circuit for a collection chip used in the field of energy storage, characterized in that: comprising a control circuit, a first switch circuit and a second switch circuit; The first switch circuit includes a MOS transistor Q1, the source of the MOS transistor Q1 is used to connect to the power supply interface, and the drain of the MOS transistor Q1 is used to connect to the power supply end of the acquisition chip; The second switch circuit includes a transistor Q2, the collector of the transistor Q2 is used to connect to the gate of the MOS transistor Q1, the emitter of the transistor Q2 is used to connect to the ground terminal, and the base of the transistor Q2 is used to connect to the power supply interface through the control circuit; The control circuit is used to realize on / off control between the base of the transistor Q2 and the power supply interface.

2. The acquisition chip shutdown wake-up circuit according to claim 1, characterized in that: A first resistor R1 is connected in parallel between the source and drain of the MOS transistor Q1 .

3. The acquisition chip shutdown wake-up circuit according to claim 2, characterized in that: A second resistor R2 is connected in series between the drain of the MOS transistor Q1 and the collector of the transistor Q2.

4. The acquisition chip shutdown wake-up circuit according to claim 3, characterized in that: The control circuit includes a control unit U1 , which is configured to generate a control signal based on a received CAN communication signal.

5. The acquisition chip shutdown wake-up circuit according to claim 4, characterized in that: The control circuit further includes an optical coupler OM1 , which is used to control the connection and disconnection between the base of the transistor Q2 and the power supply interface according to the control signal output by the control unit U1 .

6. The acquisition chip shutdown wake-up circuit according to claim 5, characterized in that: The primary side of the optical coupler OM1 is used to connect to the output end of the control unit U1; the secondary side of the optical coupler OM1 has a first port and a second port, the first port is used to connect to the power supply interface, and the second port is used to connect to the base of the transistor Q2.

7. The acquisition chip shutdown wake-up circuit according to claim 5, characterized in that: A diode D1 is connected in series between the first port and the power supply interface.

8. The acquisition chip shutdown wake-up circuit according to claim 6, characterized in that: A third resistor R3 is connected in series between the first port and the diode D1 .

9. The acquisition chip shutdown wake-up circuit according to claim 7, characterized in that: A fourth resistor R4 is connected in series between the second port and the base of the transistor Q2 .

10. The acquisition chip shutdown wake-up circuit according to claim 8, characterized in that: The base of the transistor Q2 is connected to the ground terminal through the fifth resistor R5.

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