Trench gate MOSFET

Abstract

The utility model relates to the semiconductor device technology, and discloses a trench gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a drain metal layer, a substrate, a buffer layer, an N-type drift region, a P + base region, a source layer and a source metal layer which are sequentially arranged from bottom to top, a trench region is arranged at the hollow part in the middle of the upper layer of the N-type drift region, and the trench region also longitudinally penetrates through the P + base region, the source electrode layer and the source electrode metal layer; wherein the source electrode layer comprises a P + source electrode and an N + source electrode which are arranged side by side on the left side and an N + source electrode and a P + source electrode which are arranged side by side on the right side, and the N + source electrodes are all adjacent to the trench region; a P-type gate is arranged at the bottom of the trench region, and a trench gate wrapped and isolated by an oxide layer is arranged on the P-type gate; and the two N-type grids longitudinally penetrate through the substrate and the buffer layer and are connected with the N-type drift region and the drain metal layer. The utility model aims to reduce the on resistance of the MOSFET device and improve the electrical performance of the device.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor device, especially a trench gate MOSFET. BACKGROUND

[0002] Power MOSFET devices belong to gate-controlled unipolar devices because only majority carriers participate in conduction when forward conducting, so they have the advantage of fast switching speed, and are mainly applied in low-voltage and high-frequency fields. SiC MOSFETs are widely used in power switching devices because SiC has high thermal conductivity, high electron saturation velocity, high physical and chemical stability, and strong breakdown field.

[0003] The on-resistance of conventional planar gate SiC MOSFETs is mainly composed of trench resistance, accumulation layer resistance, JFET resistance, drift region resistance, and substrate resistance. The introduction of trench gate SiC MOSFETs eliminates the JFET region, increases the trench density, and reduces the on-resistance of the device. However, the gate oxide at the bottom of the trench is exposed to the high electric field of the SiC drift region, which limits the breakdown characteristics of the device. To solve this problem, a P + -SiC shielding region trench gate SiC MOSFET was proposed because the P + -SiC shielding region can effectively protect the gate oxide and improve the breakdown voltage of the device. However, the P + -SiC shielding region and P-type SiC base region form a JFET region resistance, thereby increasing the on-resistance of the device.

[0004] The above content is only used to assist in understanding the technical scheme of the utility model and does not represent the recognition of the above content as prior art. Utility model content

[0005] The utility model provides a kind of trench gate MOSFET, to reduce the on-resistance of MOSFET device, improve the electrical performance of device.

[0006] To achieve the above purpose, the utility model provides a kind of trench gate MOSFET, comprising:

[0007] From bottom to top, drain metal layer, substrate, buffer layer, N-type drift region, P+ base region, source layer and source metal layer are sequentially provided;

[0008] Trench region is provided in the hollow part in the middle of N-type drift region upper layer, and the trench region also longitudinally penetrates P+ base region, source layer and source metal layer;Among them, source layer includes left side side-by-side arranged P+ source and N+ source, right side side-by-side arranged N+ source and P+ source, and N+ source is adjacent to trench region;

[0009] A P-type gate is arranged at the bottom of the trench region, and a trench gate wrapped by an oxide layer is arranged above the P-type gate;

[0010] Two N-type gates longitudinally penetrating the substrate and the buffer layer, connecting the N-type drift region and the drain metal layer.

[0011] Optionally, the width of the trench region is 2.5-3.5 μm, and the depth is 2-5 μm.

[0012] Optionally, the width of the P-type gate is 2.5-3.5 μm, and the depth is 0.5-1.5 μm.

[0013] Optionally, the width of the N-type gate is 1.5-2.5 μm, and the depth is 5-7 μm.

[0014] Optionally, the thickness of the oxide layer is 50-300 nm.

[0015] Optionally, the thickness of the source layer is 0.15-0.3 μm.

[0016] Optionally, the thickness of the P+ base region is 0.8-1.0 μm.

[0017] Optionally, the thickness of the N-type drift region is 10-100 μm.

[0018] Optionally, the thickness of the buffer layer is 3-5 μm.

[0019] Optionally, the thickness of the substrate is 3-5 μm.

[0020] The trench gate MOSFET has the following advantages: the positive heterojunction structure formed by the P-type gate and the N-type drift region can reduce the JFET resistance formed by the P-type SiC shielding region and the P+ base region, thereby reducing the on-resistance of the device; when the body diode of the trench gate MOSFET is turned on, the holes are more easily discharged from the back heterojunction structure formed by the N-type gate and the N-type drift region, thereby reducing the reverse recovery time, effectively improving the reverse recovery characteristics of the MOSFET body diode, and improving the electrical performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 FIG. 1 is a structural schematic diagram of an embodiment of the trench gate MOSFET.

[0022] Legend of reference signs:

[0023] 1, substrate; 2, buffer layer; 3, N-type drift region; 4, P+ base region; 5, N+ source; 6, P+ source; 7, P-type gate; 8, oxide layer; 9, trench gate; 10, source metal layer; 11, N-type gate; 12, drain metal layer.

[0024] The realization, functional features and advantages of the utility model will be further explained in combination with embodiments with reference to the drawings. DETAILED DESCRIPTION

[0025] The embodiments of the utility model will be described clearly and completely in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only some of the embodiments in the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the ordinary skilled in the art without creative labor belong to the protection scope of the utility model.

[0026] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the utility model are only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directional indications also change accordingly.

[0027] It should also be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there can be a middle element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or there can be a middle element.

[0028] In addition, if the description of "first", "second", etc. is involved in the utility model, it is only for the purpose of description (such as for distinguishing the same or similar elements), and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that the ordinary skilled in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the utility model.

[0029] The utility model provides a kind of trench gate MOSFET, referring to Figure 1 The trench gate MOSFET includes: from bottom to top, drain metal layer 12, substrate 1, buffer layer 2, N-type drift region 3, P+ base region 4, source layer and source metal layer 10 are sequentially provided;

[0030] A trench region is provided in the hollowed-out middle portion of the upper layer of the N-type drift region 3, and the trench region also vertically penetrates the P+ base region 4, the source layer, and the source metal layer 10; wherein the source layer includes a P+ source 6 and an N+ source 5 arranged side by side on the left, and an N+ source 5 and a P+ source 6 arranged side by side on the right, and the N+ source 5 is adjacent to the trench region;

[0031] A P-type gate 7 is provided at the bottom of the trench region, and a trench gate 9 is provided on the P-type gate 7 and is wrapped and isolated by an oxide layer 8;

[0032] Two N-type gates 11 vertically penetrate the substrate 1 and the buffer layer 2 and connect the N-type drift region 3 and the drain metal layer 12 .

[0033] In this embodiment, the drain metal layer 12 is located at the bottom and serves as a drain ohmic contact for connecting to an external circuit load or power supply. The drain metal layer 12 serves as the drain of the trench gate MOSFET, providing a current outflow path.

[0034] The substrate 1 is on the drain metal layer 12 and can be made of SiC material (such as N + -SiC), which has high thermal conductivity and high-temperature stability, is responsible for providing mechanical support and electrical isolation of the device.

[0035] The buffer layer 2 is provided on the substrate 1 and can be made of a low-doped SiC material, such as an N-type SiC material. The buffer layer 2 is used to reduce the electric field strength between the substrate 1 and the drift region and improve the breakdown voltage.

[0036] The N-type drift region 3 is disposed on the buffer layer 2 and can be made of a highly doped N-type SiC material. The N-type drift region 3 provides a primary current path and withstands high voltage stress.

[0037] The P+ base region 4 is arranged on the N-type drift region 3 and can be made of a highly doped P-type SiC material.

[0038] The source layer is arranged on the P+ base region 4, including the P+ source 6 arranged side by side on the left (the N + -SiC source) and N+ source 5 (N-type SiC material can be used to make N + -SiC source), an N+ source 5 and a P+ source 6 are arranged side by side on the right, and the N+ source 5 on both sides are close to the trench area, and the P+ source 6 is on both sides of the device edge (that is, the N+ source 5 is arranged between the P+ source 6 and the trench area); the source layer is used to provide source contact, reduce source resistance, and optimize source current distribution.

[0039] The source metal layer 10 is disposed on the source layer and covers the source layer. The source metal layer 10 serves as a source metal contact and can provide a low-impedance current path.

[0040] A trench region is formed by longitudinally penetrating the P+ base region 4, the source layer and the source metal layer 10, and hollowing out the middle part of the upper layer of the N-type drift region 3. A P-type gate 7 is arranged at the bottom of the trench region and in contact with the N-type drift region 3. The P-type gate 7 can be made of P + -polySi.

[0041] A trench gate 9, which is wrapped and isolated by an oxide layer 8, is arranged above the P-type gate 7 in the trench region (i.e. the gate in the recess formed by the oxide layer 8; the oxide layer 8 is responsible for isolating the trench gate 9 from the various structures of the MOSFET, including the P-type gate 7, the N-type drift region 3, the P+ base region 4, the source layer, etc.); the trench gate 9 can be made of polysilicon material; the trench gate 9 is used to further optimize the gate voltage distribution and improve the gate control efficiency.

[0042] Two N-type gates 11 are arranged in the lower layer of the N-type drift region 3 and connected to the N-type drift region 3 and the drain metal layer 12 at both longitudinal penetrations of the substrate 1 and the buffer layer 2. The N-type gate 11 can be made of N + -polySi.

[0043] Referring to Figure 1 , the P-type gate 7 and the N-type drift region 3 can form a front heterojunction structure along the A1 to A2 direction (i.e. a front P + -polySi / SiC heterojunction structure); the N-type gate 11 and the N-type drift region 3 can form a back heterojunction structure along the B1 to B2 direction (i.e. a back N + -polySi / SiC heterojunction structure).

[0044] In the trench gate MOSFET proposed in an embodiment, the front heterojunction structure formed by the P-type gate 7 and the N-type drift region 3 can reduce the JFET resistance formed by the P-type SiC shielding region and the P+ base region 4, thereby reducing the on-resistance of the device; and when the body diode of the trench gate MOSFET is turned on, holes are more easily discharged from the back heterojunction structure formed by the N-type gate 11 and the N-type drift region 3, thereby reducing the reverse recovery time, effectively improving the reverse recovery characteristics of the MOSFET body diode, and improving the electrical performance of the device.

[0045] In an embodiment, on the basis of the above-mentioned embodiment, the width of the trench region is 2.5-3.5 μm, and the depth is 2-5 μm.

[0046] In this embodiment, the width of the trench region can be equal to the width of the P-type gate 7.

[0047] The width range is selected to balance the current density and the electric field distribution, that is, to ensure the stability of the device and to reduce the on-resistance of the device as much as possible.

[0048] In an embodiment, on the basis of the above embodiment, the width of the P-type gate 7 is 2.5-3.5 μm, and the depth is 0.5-1.5 μm.

[0049] In the embodiment, the appropriate gate width can improve the control ability of the gate to the trench, thereby improving the switching performance and conduction performance of the device; and the appropriate depth can help reduce the influence of the gate voltage change on the trench current, thereby improving the stability of the device under various operating conditions.

[0050] In an embodiment, on the basis of the above embodiment, the width of the N-type gate 11 is 1.5-2.5 μm, and the depth is 5-7 μm.

[0051] In the embodiment, the N-type gate 11 structure of the design, combined with the appropriate width and depth regulation, helps to improve the overall performance and reliability of the related MOSFET.

[0052] In an embodiment, on the basis of the above embodiment, the thickness of the oxide layer 8 is 50-300 nm.

[0053] In an embodiment, on the basis of the above embodiment, the thickness of the source layer is 0.15-0.3 μm.

[0054] In an embodiment, on the basis of the above embodiment, the thickness of the P+ base region 4 is 0.8-1.0 μm.

[0055] In an embodiment, on the basis of the above embodiment, the thickness of the N-type drift region 3 is 10-100 μm.

[0056] In an embodiment, on the basis of the above embodiment, the thickness of the buffer layer 2 is 3-5 μm.

[0057] In an embodiment, on the basis of the above embodiment, the thickness of the substrate 1 is 3-5 μm.

[0058] The above only describes some or preferred embodiments of the present application, and neither the text nor the drawings can limit the scope of protection of the present application, and any equivalent structural transformation or direct / indirect application in other related technical fields based on the content of the present application specification and drawings is included in the scope of protection of the present application.

Claims

1. A trench gate MOSFET, characterized in that: include: From bottom to top, there are a drain metal layer, a substrate, a buffer layer, an N-type drift region, a P+ base region, a source layer and a source metal layer; A trench region is provided in the hollowed-out middle portion of the upper layer of the N-type drift region, and the trench region also vertically penetrates the P+ base region, the source layer, and the source metal layer; wherein the source layer includes a P+ source and an N+ source arranged side by side on the left side, and an N+ source and a P+ source arranged side by side on the right side, and the N+ source is adjacent to the trench region; A P-type gate is provided at the bottom of the trench region, and a trench gate wrapped and isolated by an oxide layer is provided above the P-type gate; Two N-type gates vertically penetrate the substrate and the buffer layer and connect the N-type drift region and the drain metal layer.

2. The trench gate MOSFET according to claim 1, wherein The groove region has a width of 2.5-3.5 μm and a depth of 2-5 μm.

3. The trench gate MOSFET according to claim 1, wherein The width of the P-type gate is 2.5-3.5 μm and the depth is 0.5-1.5 μm.

4. The trench gate MOSFET according to claim 1, wherein The N-type gate has a width of 1.5-2.5 μm and a depth of 5-7 μm.

5. The trench gate MOSFET according to claim 1, wherein The thickness of the oxide layer is 50-300 nm.

6. The trench gate MOSFET according to claim 1, wherein The thickness of the source layer is 0.15-0.3 μm.

7. The trench gate MOSFET according to claim 1, wherein The thickness of the P+ base region is 0.8-1.0 μm.

8. The trench gate MOSFET according to claim 1, wherein The thickness of the N-type drift region is 10-100 μm.

9. The trench gate MOSFET according to claim 1, wherein The thickness of the buffer layer is 3-5 μm.

10. The trench gate MOSFET according to claim 1, wherein The thickness of the substrate is 3-5 μm.

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