Server node

Abstract

A server node is provided. The server node is provided with a shell, and the shell comprises a server node body used for containing a mother board. The mother board is provided with a BIOSBMC loader module, a first security chip of an ASTXXXX type and a second security chip of a CECXXX type. And the first security chip and the second security chip are connected to the BIOSBMC loader module through a switch. The switch is configured to selectively activate operation of the first security chip and the second security chip.

Description

TECHNICAL FIELD

[0001] The present technology relates to a computer node, and more particularly, to a computer node including a secure microchip. BACKGROUND

[0002] A server is a central computer that typically serves computers in a network environment and provides necessary functionality (e.g., storage, processing, and exchange of information) to these network computers. Conventional servers can be implemented similarly to conventional personal computers and generally include a central processing unit (CPU), memory, and input / output devices, all communicatively coupled together internally via a bus. These internal components of a server or server hardware operate according to inherent specifications and can be affected by external factors such as temperature, humidity, pressure, and the like. A server rack can encompass multiple computer nodes.

[0003] Computer nodes use firmware related to node boot-up functionality. The firmware first boots up hardware components, checks for driver errors, etc. In data center based solutions, it is critical to verify the hardware components and their immutability when loading a computer node and / or server rack. Specifically, when booting up a computer node and / or server rack, it is necessary to verify that there are no changes in the firmware of the server that could lead to security vulnerabilities (e.g., stealing data or generating false traffic). SUMMARY

[0004] Based on the knowledge of the needs of developers for firmware security measures, embodiments of the present technology have been developed. To this end, secure chips can be employed to provide protection against a wide range of cyber threats. The secure chips can incorporate advanced encryption, authentication, and intrusion detection mechanisms. The secure chips can also include tamper-proof features for thwarting physical attacks on the devices that house these chips.

[0005] However, developers have also realized that secure chips lack versatility or interoperability when integrated into a variety of devices and systems, ranging from personal computers, mobile devices, server racks, and / or other critical infrastructure components. Based on the knowledge of at least one technical problem associated with prior art solutions, embodiments of the present technology have been developed.

[0006] In one aspect of the technology, a server node is provided that includes a housing containing a server node body for housing a motherboard having (i) a BIOS\BMC loader module, (ii) a first secure chip of type AST XXXX, and (iii) a second secure chip of type CEC XXX. The first secure chip and the second secure chip are connected to the BIOS\BMC loader module via a switch. The switch is configured to selectively activate operation of the first secure chip and the second secure chip.

[0007] In some embodiments of the server node, the switch includes a first jumper wire associated with the first secure chip and a second jumper wire associated with the second secure chip.

[0008] In some embodiments of the server node, the switch includes a programmable element.

[0009] In some embodiments of the server node, the programmable element is a field programmable gate array (FPGA).

[0010] In some embodiments of the server node, the first jumper wire is a first hardware jumper wire and the second jumper wire is a second hardware jumper wire.

[0011] In some embodiments of the server node, the first jumper wire is a first software jumper wire and the second jumper wire is a second software jumper wire. BRIEF DESCRIPTION OF DRAWINGS

[0012] These and other features, aspects, and advantages of the technology will become better understood with respect to the following description, appended claims, and accompanying drawings where:

[0013] Figure 1 is a front left perspective view of a server rack housing a chassis structure;

[0014] Figure 2 is Figure 1 a front left perspective view of the chassis structure of

[0015] Figure 3 is Figure 1 a front left perspective view of the chassis of the chassis structure of

[0016] Figure 4 is Figure 2 a front left exploded view of the chassis and second computer node of

[0017] Figure 5 is Figure 2 a left front perspective view of the chassis structure of

[0018] Figure 6 is Figure 5 a left front perspective view of the chassis structure of

[0019] Figure 7 is Figure 2 a top plan view of the chassis structure of

[0020] Figure 8 is Figure 2 a right rear perspective view of the chassis structure of

[0021] Figure 9 is Figure 2 a circuit diagram of the motherboard of the second computer node of

[0022] Figure 10 is a subsystem of the motherboard of Figure 9 implemented in accordance with some embodiments of the present technology. DETAILED DESCRIPTION

[0023] Example and conditional language used herein generally

[0024] Furthermore, to aid in understanding, the following description will describe relative simple implementations of the present technology. As will be understood by those skilled in the art, various implementations of the present technology can have greater complexity.

[0025] In some cases, useful examples that are believed to be modifications of the present technology can also be set forth. This is done merely to aid in understanding, and it is reiterated that no limitation as to the scope of the present technology or the bounds of the present technology is intended by doing so. These modifications are not an exhaustive list, and others can be made by those skilled in the art while still remaining within the scope of the present technology. Furthermore, no examples of modifications should be interpreted as meaning that no modifications are possible and / or that what is described is the only way to implement the recited elements of the present technology, even if no examples of modifications are set forth.

[0026] Chassis structure

[0027] Reference is made to Figure 1depicting server rack 1200 housing chassis structure 100 among a plurality of chassis structures (not numbered). Thus, it can be said that chassis structure 100 is configured to be housed in server rack 1200. Broadly, one or more chassis structures of server rack 1200 are configured to process processable requests and / or tasks for external clients. For example, data indicative of a given processable request can be acquired by one or more electronic components of chassis structure 100 (and / or by electronic components of other chassis structures of server rack 1200). This data can then be processed and / or stored by one or more electronic components of chassis structure 100.

[0028] As Figure 2 depicted in FIG. 1, chassis structure 100 includes chassis 200 and two computer nodes, namely first computer node 301 and second computer node 302. Chassis structure 100 also includes fan 400 located at a rear portion thereof. It is contemplated that, in alternative embodiments of the present technology, fan 400 can be omitted. It is further contemplated that fan 400 can alternatively be disposed on a rear portion of server rack 1200. It is noted that, in some embodiments of the present technology, first computer node 301 can be identical to second computer node 302.

[0029] Chassis

[0030] Reference will now be made to FIG. 2, which depicts how chassis 200 of chassis structure 100 can be implemented in at least some embodiments of the present technology. Figure 3

[0031] As Figure 3 depicted in FIG. 2, chassis 200 includes first bottom panel 202, first side wall 204, second side wall 206, partition wall 208, and rear wall 210. First side wall 204 and second side wall 206 extend longitudinally in chassis 200 and are positioned on respective sides of first bottom panel 202. Partition wall 208 also extends longitudinally in chassis 200 and is positioned between first side wall 204 and second side wall 206. Partition wall 208 is generally parallel to first side wall 204 and second side wall 206. Rear wall 210 extends transversely between first side wall 204 and second side wall 206 at a rear portion of chassis 200 and is connected to first side wall 204 and second side wall 206.

[0032] For example, first side wall 204, second side wall 206, partition wall 208, and rear wall 210 are attached to first bottom panel 202 of chassis 200 using any suitable attachment members, such as bolts and / or screws. Alternatively, first side wall 204, second side wall 206, partition wall 208, and rear wall 210 can be integrally formed with first bottom panel 202 for providing chassis 200.

[0033] ​The rear wall 210 is also configured to house, among other things, a power supply connector 214, a motherboard connector 216, and other connectors (not numbered), which will be discussed in further detail herein below. The rear wall 210 is provided with apertures 212, which generally serve to allow fluid communication between the interior of the chassis 200 and the exterior of the chassis 200 through the rear wall 210.

[0034] It is noted that in the non-limiting embodiment depicted in Figure 3 , the fan 400 is removably attached to the rear wall 210 on the exterior of the chassis 200. As illustrated, when the fan 400 is removably attached to the rear wall 210, the fan 400 is longitudinally aligned with the respective aperture 212. As will be described in further greater detail herein below, having the fan 400 so positioned relative to the aperture 212 allows the fan 400 to generate a fluid flow according to the direction 250 (i.e., from the interior of the chassis 200, through the rear wall 210, towards the exterior of the chassis 200).

[0035] It is noted that the first side wall 204, the second side wall 206, the partition wall 208, and the rear wall 210, as well as the first bottom panel 202, define two storage spaces in the chassis 200, namely a first storage space 270 and a second storage space 260.

[0036] The first storage space 270 is defined by the first bottom panel 202, the first side wall 204 on the left, the partition wall 208 on the right, and the rear wall 210 at the back. Similarly, the second storage space 260 is defined by the first bottom panel 202, the second side wall 206 on the right, the partition wall 208 on the left, and the rear wall 210 at the back. The two storage spaces 270 and 260 are disposed on respective sides of the partition wall 208. In certain non-limiting embodiments of the technology, the two storage spaces 270 and 260 can be substantially identical to each other.

[0037] A chassis handle 285 is disposed on the first bottom panel 202 and extends forward away from the chassis 200.

[0038] The first storage space 270 of the chassis 200 is configured to house a first computer node 301 (see Figure 1 ), and the second storage space 260 of the chassis 200 is configured to house a second computer node 302 (see Figure 1 ), and vice versa. It can be said that a given one of the two storage spaces 270 and 260 houses a respective one of the computer nodes 301 and 302.

[0039] Computer node

[0040] Reference will now be made to Figure 4It is described how the second computer node 302 is implemented. However, it should be noted that the first computer node 301 can be implemented in a similar manner as the second computer node 302 without departing from the scope of the present technology.

[0041] In Figure 4 The representation 300 of the chassis 200 and the second computer node 302 is illustrated in exploded view. It should be noted that, for simplicity, the internal components of the first computer node 301 and the chassis structure 100 have been omitted from the illustration of the representation 300. Figure 4 The internal components of the first computer node 301 and the chassis structure 100 have been omitted from the illustration of the representation 300. Moreover, for simplicity, the representation 300 of the chassis 200 and the second computer node 302 is only a simplified representation of the chassis 200 and the second computer node 302.

[0042] As seen, the second computer node 302 comprises a main body 304, a tray frame 320 and a sliding assembly 325, which will now be described in turn.

[0043] The main body 304 comprises a second bottom panel 306, a third side wall 308 and a fourth side wall 310. The third side wall 308 and the fourth side wall 310 extend longitudinally in the main body 304 and are positioned on respective sides of the second bottom panel 306. The computer node handle 280 is provided on the second bottom panel 306 and extends forwardly away from the main body 304. The third side wall 308 and the fourth side wall 310 are attached to the second bottom panel 306, but could alternatively be integrally formed with the second bottom panel 306.

[0044] It should be noted that a given computer node is configured to be removed from the respective storage space, which can be desirable for various reasons. For example, an operator can remove a given computer node from the respective storage space for maintenance and / or replacement purposes. Thus, it can be said that the main body 304 is configured to be removably stored in the second storage space 260. Thus, it can be said that the second computer node 302 is removably storable in the second storage space 260.

[0045] Moreover, the main body 304 has a front portion 312 thereof and a rear portion 314 thereof. The front portion 312 of the main body 304 and the rear portion 314 of the main body 304 are sequentially disposed longitudinally in the main body 304 from a front end thereof to a rear end thereof.

[0046] The front portion 312 of the main body 304 is configured to accommodate the tray frame 320. The tray frame 320 has two sides (not numbered) and comprises a top access opening 322. The tray handle 290 is provided on one of the two sides of the tray frame 320 and extends forwardly away from the tray frame 320. The tray frame 320 is slidably movable from a received position to at least one extracted position, such that when the tray frame 320 is in the received position, the tray frame 320 is positioned in the front portion 312 of the main body 304.

[0047] It is noted that the tray frame 320 is configured for slidable movement between a received position and at least one extracted position due to a sliding assembly 325 of the second computer node 302. The sliding assembly 325 is located in a front portion of the body 304. The sliding assembly 325 includes a given side of the tray frame 320 and a corresponding fourth side wall 310 of the body 304. However, the sliding assembly 325 can include another side of the tray frame 320 and a corresponding third side wall 308. However, in some embodiments, the second computer node 302 can have two sliding assemblies, one on each side of the tray frame 320, and implemented in a similar manner to that of the sliding assembly 325.

[0048] In one embodiment, a given side of the tray frame 320 can be nested in a corresponding side wall of the body 304 for providing the sliding assembly 325. In other words, the corresponding side wall of the body can be configured for receiving the given side of the tray frame 320 in a nested manner for providing the sliding assembly. In another embodiment, the corresponding side wall of the body can be adapted for receiving the given side of the tray frame 320 in a nested manner for providing the sliding assembly. In another embodiment, the given side of the tray frame 320 and the corresponding side wall of the body 304 can have suitable track structures for providing the sliding assembly 325.

[0049] It is noted that the sliding assembly 325 can be implemented in a variety of ways for the particular application of the present technology. However, the sliding assembly 325 is configured for longitudinally and slidable movement of a respective tray frame of a given computer node between (i) a received position (see Figure 2 ), (ii) a first extracted position (see Figure 5 ), and (iii) a second extracted position (see Figure 6 ). As will become apparent from the further description herein below, the purpose of slidable movement of a given tray frame is to provide access or additional access to at least some electronic components of the respective computer node without the need to remove the respective computer node from the chassis 200.

[0050] It is also noted that the second computer node 302 also includes a chain structure 3020 (see Figure 7 ). The chain structure 3020 is attached at one end thereof to (i) the tray frame 320 at a rear portion thereof, and (ii) at the other end thereof to the second bottom panel 306 of the body 304. Generally, the chain structure 3020 is provided for avoiding the risk of extracting the tray frame 320 from the body 304 to a point where it is disconnected from the body 304. It can be said that the chain structure 3020 can restrict the position of the tray frame 320 and cooperate with the sliding assembly 325 to prevent the tray frame 320 from accidentally falling off or being disconnected from the body 304.

[0051] With consideration, in at least some embodiments of the present technology, the chain structure 3020 can be pivotably attached to the tray frame 320 at a rear portion of the tray frame 320 at one end thereof, and pivotably attached to the second bottom panel 306 of the main body 304 at the other end thereof.

[0052] In addition to connecting the tray frame 320 with the main body 304, the chain structure 3020 can also define a hollow passageway (not numbered) for housing cables for electrically coupling at least some electronic components in the tray frame 320 to at least some other electronic components in the main body 304.

[0053] Electronic assembly

[0054] As mentioned above, the second computer node 302 is configured to house electronic components for data processing and / or storage purposes. It should be noted that at least some electronic components are housed in the tray frame 320, while other electronic components are housed in the main body 304. Which electronic components of the second computer node 302 are housed in the tray frame 320 (e.g., in the front portion 312 of the main body 304) and which electronic components of the second computer node 302 are housed in the main body 304 (e.g., the rear portion 314 of the main body 304) will now be described with reference to both Figure 7 and 8 .

[0055] The second computer node 302 houses a first electronic component 1000 and a fourth electronic component 2000 in the tray frame 320. Generally, the first electronic component 1000 and the fourth electronic component 2000 can be different types of storage media. For example, the first electronic component 1000 can be a hard disk drive (HDD). The fourth electronic component 2000 can be a solid state drive (SSD) or a non-volatile memory express (NVME) storage media. The first electronic component 1000 can be disposed at a front portion of the tray frame 320, and the fourth electronic component 2000 can be disposed at a rear portion of the tray frame 320 (longitudinally behind the first electronic component 1000).

[0056] The rear portion 314 of the second computer node 302 houses a motherboard 3000. The motherboard 3000 is electrically coupled to the first electronic component 1000 and the fourth electronic component 2000 via cables (not depicted), as is known in the art. The motherboard 3000 is also electrically coupled to the power connector 214 via the motherboard connector 216. For example, the power connector 214 can be electrically coupled to a power bus of the server rack 1200 (see Figure 1 ) and in turn to a power source, and can provide power to the motherboard 3000 and other electronic components of the second computer node 302.

[0057] Motherboard

[0058] Reference Figure 9 Motherboard 3000 will be described in further detail. Motherboard 3000 includes two central processing units (CPUs), a first CPU 3014 and a second CPU 3016. First CPU 3014 and second CPU 3016 are connected to motherboard 3000. It is contemplated that first CPU 3014 and second CPU 3016 can be communicatively coupled and / or electrically connected to one or more other electronic components via to motherboard 3000. In some embodiments of the technology, each of the first and second CPUs 3014, 3016 can be plugged into a respective socket on motherboard 3000. In some embodiments, the sockets are identical, such that the first and second CPUs 3014, 3016 can be interchangeable. In alternative embodiments, one socket is configured to receive the first CPU 3014 and the other socket is configured to receive the second CPU 3016, such that one socket is dedicated to the first CPU 3014 and the other socket is dedicated to the second CPU 3016. It is contemplated that although two CPUs 3014, 3016 are depicted, any number of CPUs can be connected to motherboard 3000 without departing from the scope of the technology.

[0059] Motherboard 3000 includes a platform controller hub 3018. Platform controller hub 3018 is connected to motherboard 3000. It is contemplated that platform controller hub 3018 can be communicatively coupled and / or electrically connected to one or more other electronic components via to motherboard 3000. Platform controller hub 3018 is further connected to first CPU 3014 and second CPU 3016.

[0060] It should be noted that a platform controller hub (PCH) is a component in computer architecture that acts as a central hub for managing and controlling various functions of a computer motherboard, such as motherboard 3000. It acts as a communication and management center that facilitates data flow between one or more CPUs, memory, storage devices, and / or peripheral devices. It is contemplated that PCH 3018 can also be used for tasks such as connecting USB ports, SATA ports, Ethernet ports, audio components, and other input / output interfaces to motherboard 3000. PCH 3018 can also handle power management, system configuration, and various low-level operations that allow different hardware components to work together. By incorporating one or more of these functions into a single chip, PCH 3018 helps streamline communication and coordination between different hardware components, and thereby optimizes overall system performance and efficiency. It is contemplated that PCH 3018 can support different interface and connectivity options.

[0061] Motherboard 3000 further includes a baseboard management controller (BMC) chip 3021 for remote management, monitoring, and control of hardware. BMC chip 3021 can include a serial peripheral interface (SPI) flash device 3043. BMC chip 3021 is integrated into motherboard 3000 and connected via SPI bus 3044. In some embodiments of the technology, BMC chip 3021 can be connected via internal integrated circuit (I2C) 3040 and / or system management bus (SMBus). BMC chip 3021 includes firmware storage containing code for remote management and monitoring functions, and is typically stored in a flash memory chip that is disposed on motherboard 3000. As Figure 9 As depicted in FIG. 3, BMC chip 3021 is connected to platform controller hub 3018 via first multiplexer 3024.

[0062] It is contemplated that the BMC can be implemented as a dedicated microcontroller embedded on a computer motherboard, such as motherboard 3000. As such, the BMC chip can be responsible for monitoring, managing, and controlling various aspects of the system, even if the CPU is powered off or unresponsive. BMC chip 3021 can be used for remote management, system health monitoring, maintenance of servers, networking equipment, and other enterprise-level hardware. For example, BMC chip 3021 can be used for system security by enabling features like remote BIOS updates, monitoring intrusion detection sensors, and providing a secure interface for managing encryption keys.

[0063] An SPI flash device 3022 for a basic input output system (BIOS) is connected to motherboard 3000. SPI flash device 3022 is connected to motherboard 3000 via SPI bus 3042. In some embodiments of the technology, SPI flash device 3022 can be connected via I3C or SMBus. SPI flash device 3022 stores instructions in memory for hardware initialization and boot-up processes, as well as facilitating communication between the operating system and hardware components during boot-up. As Figure 9 As depicted in FIG. 3, SPI flash device 3022 is connected to PCH 3018 via second multiplexer 3026.

[0064] Broadly speaking, SPI flash devices are a type of non-volatile memory used in electronic devices, such as embedded systems, microcontrollers, and other hardware components. SPI flash devices can store data when power is removed and are accessed using the SPI protocol. SPI flash memory comes in a variety of capacities and is used for firmware storage, boot sequences, configuration data, and other information that needs to be preserved across power cycles. The SPI protocol is a synchronous communication protocol commonly used to connect microcontrollers, sensors, and other peripherals to a CPU or other microcontroller. It involves a master-slave architecture, where one device (the master) controls communication with one or more peripheral devices (the slaves). SPI uses a clock signal and multiple data lines to transfer data between devices. The clock signal synchronizes data transfer, and data can be exchanged in full-duplex mode, allowing for simultaneous data send and receive operations. The SPI protocol is commonly used for tasks that include reading and writing to memory devices like SPI flash, controlling peripherals such as sensors and displays, and enabling communication between microcontrollers in various embedded systems. It can require more pins, for example, compared to other communication protocols like I2C.

[0065] Upon starting the server, verification of software and / or hardware components should be completed to determine if they have been altered by a hacker or fraudulent user that can change the server's firmware to steal data and / or generate false traffic. A microchip that includes security checks can be implemented that can check the server's operating system and hardware components. Specifically, the present technology implements a microchip from the ASTxxxx chip 3021 series from Aspeed Tech TM in relation to the BMC chip 3021. It should be appreciated that in this context, the identifier of xxxx indicates a serial number associated with the ASTxxxx type chip series. In embodiments of the present technology, an AST2xxx chip 3021 can be used, such as an AST2600. The present technology implements a microchip from the CECxxx chip 3023 series from Microchip TM in relation to the BIOS chip 3023. It should be appreciated that in this context, the identifier of xxx indicates a serial number associated with the CECxxx type chip series. In embodiments of the present technology, a CEC173x chip 3023 is implemented.

[0066] The AST2xxx chip 3021 provides security features, such as secure boot, encryption, and remote authentication, to protect the server and its management functions. The AST2xxx chip 3021 uses a special memory section of one-time write instructions, preventing any ability to overwrite the instructions.

[0067] The CEC173x chip 3023 acts as a root of trust, providing robust security features such as hardware-based encryption acceleration, secure boot, secure key storage, and encryption capabilities, which make the CEC173x chip suitable for advanced data protection.

[0068] Both the AST2xxx chip 3021 and the CEC173x chip 3023 are integrated in the motherboard 3000. Having both the AST2xxx chip 3021 and the CEC173x chip 3023 on the same motherboard 3000 provides flexibility and adaptability to the end user to optimize chip selection to meet server / data center requirements. In other words, the end user can choose whether to connect the AST2xxx chip 3021 or the CEC173x chip to best suit the end user’s needs.

[0069] Each of the AST2xxx chip 3021 and the CEC173x chip 3023 can be connected to the motherboard 3000 via respective jumpers 3028, 3029. The host RST line 3045 is used in conjunction with the jumper 3028, and the BMC RST line 3046 is used in conjunction with the jumper 3029. Broadly speaking, the host RST line 3045 and the BMC RST line 3046 correspond to wired (circuit) communication lines for the transmission of a reboot command to reboot the host and the BMC, respectively.

[0070] Broadly speaking, a jumper connection (often simply referred to as a “jumper”) is an electrical component used in electronic and computer hardware to configure and / or modify the behavior of a device and / or circuit. In some implementations, a jumper includes a pair of electrically conductive metal pins or “terminals” that can be connected and / or disconnected using a plastic cap or metal bridge. Jumper connections are used to set up specific settings and modes on a circuit board, such as a motherboard. They allow an operator to select options without necessarily needing specialized software or programming. By placing or removing a jumper cap across the appropriate pins, a particular function or configuration can be selectively enabled or disabled.

[0071] In some cases, jumpers can be used to configure hardware parameters such as drive master / slave settings, clock frequencies, voltage levels, and data transfer modes. For example, on a hard disk drive, it can determine whether a drive is set as a master or slave drive in a dual drive configuration. In other cases, a given motherboard can be implemented with jumpers for clearing BIOS or CMOS settings, effectively resetting the hardware to default values. In further cases, jumpers can enable or disable specific features or components on a circuit board, as will be discussed herein.

[0072] In some embodiments, one or more jumpers can be implemented as software jumpers as opposed to physical / hardware jumpers. In a sense, software jumpers can achieve the same functionality as hardware jumpers using software commands without necessarily requiring physical manipulation. It is contemplated that software jumpers can allow for changing configuration settings through a software interface or command, which can be easily and remotely changed if compared to hardware jumpers. This virtual approach to jumper functionality allows for dynamic reconfiguration and customization. It provides flexibility to adjust system behavior, settings, and / or operational modes without requiring an operator to access physical hardware. This simplifies maintenance, troubleshooting, and system upgrades. In some embodiments, software jumpers can be implemented via one or more integrated BIOS commands.

[0073] It is noted that the AST2xxx chip 3021 is associated with a first jumper 3028 and the CEC173x chip 3023 is associated with a second jumper 3029. In this embodiment, the first and second jumpers 3028, 3029 are physical connectors with jumper caps that are used to close a circuit on the motherboard 3000. An end user can select whether to connect the AST2xxx chip 3021 or the CEC173x chip by connecting the respective jumper 3028, 3029. Specifically, when the first jumper 3028 is connected, the AST2xxx chip 3021 is connected. Similarly, when the second jumper 3029 is connected, the CEC173x chip is connected. It is contemplated that in other embodiments of the technology, the first and second jumpers 3028, 3029 can be other forms of connectors without departing from the scope of the technology.

[0074] In some embodiments, a server node is provided. The server node can include a body that houses a motherboard. More specifically, the motherboard includes (i) a loader module, such as a BIOS\BMC module, (ii) a first security chip, such as an AST2xxx chip, and (iii) a second security chip, such as a CEC173x chip. The first security chip is associated with a first connection and a first jumper on the motherboard, and the second security chip is associated with a second connection and a second jumper on the motherboard.

[0075] During operation, one or more components of the motherboard can be configured to employ at least one of the first security chip and the second security chip by closing and / or opening at least one of the first jumper or the second jumper. In some embodiments, one or more components of the motherboard can utilize the first jumper and the second jumper to selectively and interchangeably employ the first security chip and the second security chip during operation of the server node.

[0076] In some embodiments, the functionality of the one or more jumpers can be implemented by a switch comprising programmable elements. For example, the switch can comprise a field programmable gate array (FPGA), which is an integrated circuit that provides reconfigurable hardware functionality. Unlike traditional application specific integrated circuits (ASICs), FPGAs can be programmed and reprogrammed after manufacture, enabling rapid customization for a variety of computing tasks. FPGAs are composed of a matrix of programmable logic blocks interconnected by configurable routing channels, allowing a user to create custom digital circuits or even entire processors.

[0077] In some embodiments, the motherboard 3000 can be configured to implement one or more secure boot mechanisms. It should be noted that both the first secure chip and the second secure chip can include respective roots-of-trust (RoTs) that can be used to verify firmware and / or generate a reset signal for the application processor. It is contemplated that the first RoT of the first secure chip or the second RoT of the second secure chip can be selectively used, depending, among other things, on the needs or configuration of the client system.

[0078] Reference is made to Figure 10 depicts a subsystem 1000 that includes a RoT device 1002, an application processor 1004, and a flash device 1006. Broadly, the RoT device 1002 is a hardware component configured to store cryptographic keys used in a “chain-of-trust” (CoT), where the code to be executed is initially verified. In computer security, a CoT is established by verifying each component in hardware and software from an end entity up to a root certificate. It is desirable to ensure that only trusted software and hardware can be used while still maintaining flexibility.

[0079] During a check operation, a cryptographic signature can be computed and verified by the RoT device 1002 if the code is valid / legitimate to execute at a given point in time and / or at a given server state. A public and private key pair is used in this process - the private key is used to generate the signature, and the public key is used to verify that the signature is correct (i.e., that the signed file has not been modified). In one aspect, access to the private key is controlled or the environment in which the signature is generated is kept “secret.” In another aspect, the public key is written onto the RoT device 1002 and used by the hardware for firmware verification.

[0080] Additionally or alternatively, the RoT device 1002 can be configured to perform data encryption and / or decryption mechanisms (without exposing the keys), key generation mechanisms, key revocation mechanisms, storage of at least some boot settings, and the like. While the RoT device 1002 is considered to be “secure” (i.e., it is complex to retrieve cryptographic data from the device), developers of the present technology recognize that it can be beneficial to avoid storing the private key in the RoT device for security purposes.

[0081] Upon consideration, it is further possible to employ one-time programmable (OTP) memory devices to store cryptographic data and hardware settings. Depending on the particular implementation of the RoT device, hardware boot and other settings can also be stored in corresponding OTP memory devices. In some implementations, write operations onto configurable regions of the OTP memory devices can be performed after initial OTP provisioning to support key revocation mechanisms.

[0082] In some embodiments, upon consideration, the RoT device 1002 can be used to prevent the execution of untrusted / unauthenticated code on the motherboard 3000 and / or one or more components of the subsystem 1000. To this end, during the power-on phase, the RoT device 1002 can generate a reset signal for the application processor 1004, e.g., a BMC or host device, such that the CPU of the application processor 1004 is not allowed to run. Further, the RoT device 1002 can read data from the firmware of the application processor 1004, generate a signature and perform a verification against the keys in the OTP memory device. In case of a verification failure, the RoT device 1002 can, among other things, program a golden image (known to be a secure unchangeable firmware) into the SPI image of the application processor 1004. Additionally or alternatively, the RoT device 1002 can further transmit a signal for reporting the current verification status to an external subsystem, e.g., a BMC, e.g., via an I2C interface.

[0083] Modifications and improvements to the aforementioned embodiments of the present technology can become apparent to those skilled in the art. The foregoing description is intended to be exemplary rather than limiting. Thus, the scope of the present technology should be determined by the scope of the appended claims, and their equivalents.

Claims

1. A server node, characterized by It comprises: a housing containing a server node body for housing a motherboard; the motherboard has (i) a BIOS\BMC loader module, (ii) a first security chip of type AST XXXX, and (iii) a second security chip of type CEC XXX; the first security chip and the second security chip are connected to the BIOS\BMC loader module via a switch; the switch is configured to selectively activate operation of the first security chip and the second security chip.

2. The server node of claim 1, wherein the switch comprises a first jumper wire associated with the first security chip and a second jumper wire associated with the second security chip.

3. The server node of claim 1, wherein the switch comprises a programmable element.

4. The server node of claim 3, wherein the programmable element is a field programmable gate array, FPGA.

5. The server node of claim 2, wherein the first jumper wire is a first hardware jumper wire and the second jumper wire is a second hardware jumper wire.

6. The server node of claim 2, wherein the first jumper wire is a first software jumper wire and the second jumper wire is a second software jumper wire.

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