Data line interface circuit
By combining processing modules, switching modules, interface modules, and circuit protection modules, the surge and electrostatic interference problems of the data cable during charging are solved, the voltage resistance and safety of the data cable are improved, the circuit structure is simplified, and the production cost is reduced.
Patent Information
- Application Number
- CN202422895955.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2034-11-26
AI Technical Summary
Existing data cables are susceptible to surges and static electricity during charging, resulting in a short service life and low safety of charging equipment. Existing protective structures are complex and have insufficient anti-static capabilities.
The system employs a combination of a processing module, a switching module, a first interface module, a second interface module, a voltage divider module, and a circuit protection module. The voltage divider module serves to divide voltage and limit current between the processing module and the switching module, while the circuit protection module protects against instantaneous voltage and, combined with ESD protection circuitry, prevents surges and electrostatic interference.
It effectively protects against surges and electrostatic interference, improves the circuit's voltage resistance and safety, while simplifying the circuit structure and reducing production costs.
Smart Images
Figure CN223462748U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to electronic fittings technical field, especially relate to a data line interface circuit. BACKGROUND
[0002] With the fast development of the times, people's living standards are constantly improving, in daily life or in the workplace, all kinds of electrical products will be used, and the use of electronic products in the process of data connection and charging needs to be connected through the data line to realize conduction. The function of data line is usually to connect mobile devices and computers to achieve data transmission or communication purposes. However, there are common surge, static and other interference problems when charging the data line, which will make the service life of the charging device not good, and the existing most charging data line surge protection structure is relatively complex, and the anti-static ability is low, it is difficult to effectively prevent high-strength static electricity from damaging the charging data line, resulting in low safety. INVENTION CONTENTS
[0003] In view of the above problems, the utility model provides a data line interface circuit, can realize the effective protection of surge, static interference, also improves the voltage resistance performance of circuit, and the circuit structure is simple, and the following technical scheme is concretely adopted to realize.
[0004] In order to realize the above object, the utility model adopts the following technical scheme:
[0005] The utility model provides a data line interface circuit, including processing module, switch module, first interface module, second interface module, voltage division module and circuit protection module, first interface module, second interface module, voltage division module, circuit protection module all are connected with processing module, first interface module, second interface module, voltage division module all are connected with switch module, first interface module, second interface module all are connected with circuit protection module, first interface module is connected with voltage division module.
[0006] As the preferred of the above technical scheme, the processing module includes chip U1, capacitor C1 and capacitor C2, capacitor C1, capacitor C2 is connected the pin cc cap, pin VCC of chip U1 respectively, the pin aid of chip U1 is connected with second interface module.
[0007] As the preferred of the above technical scheme, the voltage division module includes resistance R2 and resistance R3, resistance R2, resistance R3 are connected with switch module, resistance R2 is connected with resistance R3, resistance R2 is connected with first interface module, resistance R3 is connected with the pin out1 of chip U1, and the resistance value of resistance R3 is greater than the resistance value of resistance R2.
[0008] As the preferred of the above technical solution, the switch module comprises a resistor R1 and a MOS tube Q1, a gate of the MOS tube Q1 is connected with a resistor R2 and a resistor R3, the resistor R1 is connected with a source and a drain of the MOS tube Q1, the first interface module is connected with the source of the MOS tube Q1, and the second interface module is connected with the drain of the MOS tube Q1.
[0009] As the preferred of the above technical solution, the circuit protection module comprises a resistor R4, a first ESD protection circuit and a second ESD protection circuit, the resistor R4 and the first ESD protection circuit are connected to a pin cc of the chip U1, the second ESD protection circuit is connected to a pin aid of the chip U1, the first ESD protection circuit and the second ESD protection circuit are connected with the first interface module, and the first ESD protection circuit and the second ESD protection circuit each comprise a transient voltage suppressor and a capacitor in parallel.
[0010] As the preferred of the above technical solution, the processing module comprises a chip U2, a capacitor C3, a capacitor C4, a resistor R8 and a resistor R9, the capacitor C3 and the capacitor C4 are connected with a pin VDD-H and a pin VDDC of the chip U2 respectively, one end of the resistor R8 is connected with a pin SDQ of the chip U2, the other end of the resistor R8 is connected with the second interface module, one end of the resistor R9 is connected with a pin CC of the chip U2, and the other end of the resistor R9 is connected with the first interface module.
[0011] As the preferred of the above technical solution, the model of the chip U2 is PD008B.
[0012] As the preferred of the above technical solution, the circuit protection module comprises a TVS diode D4 and a TVS diode D5, the TVS diode D5 is connected with a pin SDQ of the chip U1, the TVS diode D4 is connected with a pin CC of the chip U2, and the TVS diode D4 and the TVS diode D5 are connected with the first interface module.
[0013] As the preferred of the above technical solution, the switch module comprises a MOS tube Q2, a resistor R5 and a TVS diode D1, the resistor R5 is connected with a source and a drain of the MOS tube Q2, the TVS diode D1 is connected with a source and a gate of the MOS tube Q2, and a drain of the MOS tube Q2 is connected with the second interface module.
[0014] As the preferred technical scheme, the voltage dividing module comprises a resistor R6 and a resistor R7, the gate of the MOS tube Q2, the TVS diode D1 and the resistor R7 are connected, the resistor R6 and the resistor R7 are connected to the pin MOS of the chip U2, and the first interface module and the source of the MOS tube Q2 are connected to the resistor R6.
[0015] Compared with the prior art, the utility model has the advantages that:
[0016] By setting the processing module, the switch module, the first interface module, the second interface module, the voltage dividing module and the circuit protection module in the circuit, the circuit protection module can effectively protect the instantaneous voltage input by the first interface module from surge, the voltage dividing module is connected between the processing module and the switch module, can play the role of voltage division and current limiting, thereby effectively inhibiting the surge voltage and discharging the static electricity, increasing the voltage resistance of the product, making the second interface module output normal and safe voltage or current, improving the use safety of the product, and the circuit structure is simple, which reduces the production cost of the product to a certain extent. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 The utility model provides a data line interface circuit's structure block diagram;
[0018] Figure 2 The utility model provides a chip U1 circuit diagram;
[0019] Figure 3 The utility model provides a chip U2 circuit diagram.
[0020] The main element symbol is explained as follows:
[0021] 100-processing module;110-switch module;120-first interface module;130-second interface module;140-voltage dividing module;150-circuit protection module. DETAILED DESCRIPTION
[0022] The technical scheme in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model, and obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments.
[0023] In the description of the utility model, need understanding is, the term "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "straight", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and so on indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawing, just is for the convenience of describing the utility model and simplifying the description, and is not the indication or implicit device or element that the indicated device or element must have a particular orientation, constructs and operates with a particular orientation, therefore can not be understood as the restriction of the utility model.
[0024] Referring to Figure 1 And Figure 2 The utility model provides a kind of data line interface circuit, including processing module 100, switch module 110, first interface module 120, second interface module 130, voltage division module 140 and circuit protection module 150, the first interface module 120, the second interface module 130, the voltage division module 140, the circuit protection module 150 are connected with the processing module 100, the first interface module 120, the second interface module 130, the voltage division module 140 are connected with the switch module 110, the first interface module 120, the second interface module 130 are connected with the circuit protection module 150, the first interface module 120 is connected with the voltage division module 140.
[0025] In the embodiment, the processing module 100 includes a chip U1, a capacitor C1 and a capacitor C2, the capacitor C1 and the capacitor C2 are connected to the pins cc cap and VCC of the chip U1 respectively, and the pin aid of the chip U1 is connected to the second interface module 130. The voltage division module 140 includes resistors R2 and R3, the resistors R2 and R3 are connected to the switch module 110, the resistor R2 is connected to the resistor R3, the resistor R2 is connected to the first interface module 120, the resistor R3 is connected to the pin out1 of the chip U1, and the resistance value of the resistor R3 is greater than that of the resistor R2. The switch module 110 includes a resistor R1 and a MOS tube Q1, the gate of the MOS tube Q1 is connected to the resistors R2 and R3, the resistor R1 is connected to the source and drain of the MOS tube Q1, the first interface module 120 is connected to the source of the MOS tube Q1, and the second interface module 130 is connected to the drain of the MOS tube Q1. The circuit protection module 150 includes a resistor R4, a first ESD protection circuit and a second ESD protection circuit, the resistor R4 and the first ESD protection circuit are connected to the pin cc of the chip U1, the second ESD protection circuit is connected to the pin aid of the chip U1, the first ESD protection circuit and the second ESD protection circuit are connected to the first interface module, and the first ESD protection circuit and the second ESD protection circuit each include a transient voltage suppressor and a capacitor in parallel.
[0026] It should be noted that the first interface module 120 is Header 5 and is marked as P2, and the second interface module is IP8P and is marked as P1. The first interface module 120 can be a Type-C interface, and the second interface module 130 can be a Ligtning interface. The first interface module 120 includes 5 pins of VIN, CC1, D-, D+ and GND1, and the second interface module 130 includes 16 pins of GND1, D+, D-, IDA, VOUT, CC1 and the like. The first interface module 120 and the second interface module 130 can charge or transmit data. The resistor R1 is 120R, the MOS tube Q1 is 3117C, the resistor R2 is 100K, and the resistor R3 is 5.1K. The VIN end of the first interface module 120 is connected to the source of the MOS tube Q1, the VOUT end of the second interface module 130 is connected to the drain of the MOS tube Q1, and the resistors R2 and R3 are connected to the gate of the MOS tube Q1 to form a gate resistor structure, which can play a role in voltage division and current limiting.
[0027] Specifically, the model of the chip U1 is C9419, the chip U1 includes six pins of cc cap, gnd, vcc, aid, cc and out1, the resistance R3 is connected with the pin out1 of the chip U1, one end of the capacitor C1 is connected with the pin cc cap of the chip U1, one end of the capacitor C2 is connected with the pin vcc of the chip U1, the pin cc of the chip U1 is connected with the resistance R4 and the TVS diode D2, the TVS diode D3 and the IDA of the second interface module 130 are connected with the pin aid of the chip U1, the TVS diode D2, the TVS diode D3, the GND1 of the first interface, the capacitor C1, the capacitor C2 and the pin gnd of the chip U1 are connected, the TVS diode D2 and the TVS diode D3 are respectively connected with a capacitor in parallel, the model of the TVS diode D2 and the TVS diode D3 is D0402-BI, the capacitor C1 is 220nF, and the capacitor C2 is 47nF. The voltage dividing module 140 is connected between the processing module 100 and the switch module 110, can play a role of voltage division and current limiting, thereby effectively inhibiting the surge voltage. The first ESD protection circuit is connected between the first interface module 120 and the chip U1, and the second ESD protection circuit is connected between the second interface module 130 and the chip U2, which can effectively protect the surge and improve the working reliability of the product.
[0028] Optionally, referring to Figure 1 and Figure 3 , the processing module 100 includes a chip U2, a capacitor C3, a capacitor C4, a resistance R8 and a resistance R9, the capacitor C3 and the capacitor C4 are respectively connected with the pins VDD-H and VDDC of the chip U2, one end of the resistance R8 is connected with the pin SDQ of the chip U2, the other end of the resistance R8 is connected with the second interface module 130, one end of the resistance R9 is connected with the pin CC of the chip U2, and the other end of the resistance R9 is connected with the first interface module 120.
[0029] In this embodiment, the model of the chip U2 is PD008B, the circuit protection module 150 includes a TVS diode D4 and a TVS diode D5, the TVS diode D5 is connected with the pin SDQ of the chip U1, the TVS diode D4 is connected with the pin CC of the chip U2, and the TVS diode D4 and the TVS diode D5 are connected to the first interface module 120. The switch module 110 includes a MOS tube Q2, a resistor R5 and a TVS diode D1, the resistor R5 is connected with the source and the drain of the MOS tube Q2, the TVS diode D1 is connected with the source and the gate of the MOS tube Q2, and the drain of the MOS tube Q2 is connected with the second interface module 130. The voltage division module 140 includes a resistor R6 and a resistor R7, the gate of the MOS tube Q2 and the TVS diode D1 are connected with the resistor R7, the resistor R6 is connected with the resistor R7 to the pin MOS of the chip U2, and the first interface module 120 and the source of the MOS tube Q2 are connected with the resistor R6.
[0030] It should be noted that the first interface module 120 is denoted as P4, the second interface module 130 is denoted as P3, and the structures of P4 and P3 are the same as those of P2 and P1 respectively, which will not be described here. The switch module 110 includes a MOS tube Q2, a resistor R5 and a TVS diode D1, the MOS tube Q2 is FH3419, one end of the TVS diode D1 is connected with the VIN of the first interface module 120, the resistor R6, the resistor R5 and the MOS tube Q2, the other end of the TVS diode D1 is connected with the gate of the MOS tube Q2 and the resistor R7, one end of the resistor R6 is connected with the VIN of the first interface module 120 and the source of the MOS tube Q2, the other end of the resistor R6 is connected with the resistor R7 and the pin MOS of the chip, the resistor R6 is preferably 3.9K, the resistor R7 is preferably 100K, the resistor R5 is preferably 120R, the resistor R8 is preferably 20R, and the resistor R9 is preferably 200R. The resistor R9 is connected with the CC1 of the first interface module 120, the pin CC of the chip U2 and the TVS diode D4, the pin SDQ of the chip U2 is connected with the TVS diode D5 and one end of the resistor R8, the other end of the resistor R8 is connected with the IDA of the second interface module 130, and the TVS diode D4 and the TVS diode D5 are both 5V ESD, which can realize surge protection of the chip U2.
[0031] Specifically, the capacitor C3 and the capacitor C4 are connected with the pin VDD-H and VDDC of the chip U2 respectively, the capacitor C3, the capacitor C4, the TVS diode D4 and the TVS diode D5 are connected with the GND of the first interface module, the resistor R7 and the resistor R6 constitute the gate drive resistor structure of the MOS tube Q2, current limiting and voltage division can be realized, so that the protection effect of the circuit is realized, wherein when the two poles of the TVS diode D4 and the TVS diode D5 are subjected to reverse transient high-energy impact, the high impedance between the two poles can be quickly changed to low impedance, high surge power is absorbed, the voltage between the two poles is clamped to a preset value, the chip U2 is effectively protected to work normally, so as to avoid damage caused by surge pulse.
[0032] It should be understood that by arranging the processing module 100, the switch module 110, the first interface module 120, the second interface module 130, the voltage division module 140 and the circuit protection module 150 in the circuit, the circuit protection module 150 can effectively protect the surge of the transient voltage input by the first interface module 110, the voltage division module 140 is connected between the processing module 100 and the switch module 110, which can play a role in voltage division and current limiting, thereby effectively suppressing the surge voltage and discharging static electricity, and also increasing the voltage resistance of the product, so that the second interface module 130 outputs normal and safe voltage or current, improving the use safety of the product, and the circuit structure is simple, which also reduces the production cost of the product to a certain extent.
[0033] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this, any skilled person in the art can make equivalent replacement or change according to the technical scheme and the inventive concept of the present application within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.
Claims
1. A data line interface circuit, characterized by The application relates to a circuit module, which comprises a processing module, a switch module, a first interface module, a second interface module, a voltage division module and a circuit protection module.
2. The data line interface circuit of claim 1, wherein, The processing module comprises a chip U1, a capacitor C1 and a capacitor C2, the capacitor C1 and the capacitor C2 are connected to the pins cc cap and VCC of the chip U1 respectively, and the pin aid of the chip U1 is connected to the second interface module.
3. The data line interface circuit of claim 2, wherein, The voltage division module comprises a resistor R2 and a resistor R3, the resistor R2 and the resistor R3 are connected to the switch module, the resistor R2 is connected to the resistor R3, the resistor R2 is connected to the first interface module, the resistor R3 is connected to the pin out1 of the chip U1, and the resistance value of the resistor R3 is greater than that of the resistor R2.
4. The data line interface circuit of claim 3, wherein, The switch module comprises a resistor R1 and a MOS tube Q1, the gate of the MOS tube Q1 is connected to the resistors R2 and R3, the resistor R1 is connected to the source and the drain of the MOS tube Q1, the first interface module is connected to the source of the MOS tube Q1, and the second interface module is connected to the drain of the MOS tube Q1.
5. The data line interface circuit of claim 4, wherein, The circuit protection module comprises a resistor R4, a first ESD protection circuit and a second ESD protection circuit, the resistor R4 and the first ESD protection circuit are connected to the pin cc of the chip U1, the second ESD protection circuit is connected to the pin aid of the chip U1, the first ESD protection circuit and the second ESD protection circuit are connected to the first interface module, and the first ESD protection circuit and the second ESD protection circuit each comprise a transient voltage suppressor and a capacitor in parallel.
6. The data line interface circuit of claim 1, wherein, The processing module comprises a chip U2, a capacitor C3, a capacitor C4, a resistor R8 and a resistor R9, the capacitor C3 and the capacitor C4 are connected to the pins VDD-H and VDDC of the chip U2 respectively, one end of the resistor R8 is connected to the pin SDQ of the chip U2, the other end of the resistor R8 is connected to the second interface module, one end of the resistor R9 is connected to the pin CC of the chip U2, and the other end of the resistor R9 is connected to the first interface module.
7. The data line interface circuit of claim 6, wherein, The model of the chip U2 is PD008B.
8. The data line interface circuit of claim 6, wherein, The circuit protection module comprises a TVS diode D4 and a TVS diode D5, the TVS diode D5 is connected to the pin SDQ of the chip U1, the TVS diode D4 is connected to the pin CC of the chip U2, and the TVS diode D4 and the TVS diode D5 are connected to the first interface module.
9. The data line interface circuit of claim 8, wherein, The switch module comprises a MOS tube Q2, a resistor R5 and a TVS diode D1, the resistor R5 is connected with the source and drain of the MOS tube Q2, the TVS diode D1 is connected with the source and gate of the MOS tube Q2, and the drain of the MOS tube Q2 is connected with the second interface module.
10. The data line interface circuit of claim 9, wherein, The voltage division module comprises a resistor R6 and a resistor R7, the gate of the MOS tube Q2 and the TVS diode D1 are connected with the resistor R7, the resistor R6 is connected with the resistor R7 to the pin MOS of the chip U2, and the first interface module and the source of the MOS tube Q2 are connected with the resistor R6.