Chip test tool
By designing chip testing fixtures and using adapter boards, test jigs, and FPC line interfaces to connect chip pins, the problem of inaccurate testing after chip packaging was solved, achieving efficient and reliable chip testing and improving yield.
Patent Information
- Application Number
- CN202422717174.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2034-11-08
AI Technical Summary
In existing technologies, it is impossible to accurately determine the cause of chip defects during post-packaging testing, resulting in low PCBA yield, especially for small-batch or experimental products, where there is a lack of effective testing fixtures.
A chip testing fixture was designed, including an adapter board, a test fixture, and an FPC line interface. The chip pins are connected to the data acquisition system through a conductive layer to achieve reliable chip testing. A heat dissipation channel is provided to ensure a stable testing environment.
This improved the efficiency and quality of chip testing, ensured chip reliability, and increased PCBA yield.
Smart Images
Figure CN223471116U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip testing, in particular to a chip testing tool. BACKGROUND
[0002] At present, special tests are arranged when chips are packaged, but the equipment investment is large, and some small quantities or experimental products are often not considered to be invested, instead, the chips are directly tested after SMT on the circuit board, but there are factors such as poor chip welding, chip abnormalities and PCB abnormalities, which cannot correctly judge whether the chip is defective, and will lead to low yield of PCBA finished products. Therefore, there is an urgent need for reliable testing tools to screen incoming chips to judge the chip state and improve the yield of the detector. CONTENT OF THE UTILITY MODEL
[0003] In order to improve the problems in the above background art, the present application provides a chip testing tool.
[0004] The chip testing tool provided by the present application adopts the following technical scheme:
[0005] A chip testing tool, comprising an adapter plate, the adapter plate is used for mounting a chip to be tested, a detection port for placing the chip to be tested is arranged on the adapter plate, and a plurality of insertion slots for inserting chip pins are arranged on the bottom wall of the detection port; a test fixture, the test fixture is installed on the adapter plate, the test fixture is used for clamping the chip to be tested on the adapter plate, a clamping hole for the chip to be clamped and then falling into the detection port is formed on the test fixture; an FPC line interface, the FPC line interface is installed on the adapter plate, so that the chip pin output end is connected to the connection end of the FPC line interface through a circuit after the chip pin is inserted into the insertion slot; and the FPC line interface is externally connected to a data acquisition system.
[0006] Preferably, the clamping hole is square, and a relief slot is formed at each of the four corners of the clamping hole; and a flexible protective pad is arranged at the slot opening of the relief slot.
[0007] Preferably, a plurality of auxiliary holes are formed around the test fixture and are in communication with the clamping hole.
[0008] Preferably, a conductive layer is arranged on the inner side wall of the insertion slot, and the thickness of the conductive layer is 5-10 μm.
[0009] Preferably, an adjustable height supporting leg is arranged at the bottom of the adapter plate, and the adapter plate can be kept horizontal on different planes through the supporting leg.
[0010] Preferably, the supporting leg comprises a supporting column and a hemispherical base, one end of the supporting column in the length direction is fixedly connected to the base, the other end is threadedly connected to the adapter plate, and the arc surface of the hemispherical base is used for abutting against the placing plane.
[0011] Preferably, the adapter plate is provided with a plurality of heat dissipation channels, which communicate with the detection port.
[0012] To sum up, the present application has at least one of the following beneficial technical effects: in actual use of the chip testing tool, the chip to be tested is placed into the clamping hole of the test fixture, the chip falls into the detection port of the adapter plate through the clamping hole, and the chip pin is inserted into the slot in the bottom wall of the detection port. At this time, the chip is clamped and fixed by the test fixture, the chip pin is electrically connected to the FPC line interface through the conductive layer on the inner wall of the slot, and the external data acquisition system can start testing the chip to be tested, thereby ensuring the testing efficiency of the chip and the quality of the chip. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 is a top view of a chip testing tool in the embodiment of the present application.
[0014] Figure 2 is a front view of a chip testing tool in the embodiment of the present application.
[0015] Reference signs: 1, adapter plate; 2, detection port; 3, slot; 31, conductive layer; 4, test fixture; 41, clamping hole; 42, clearance groove; 43, auxiliary hole; 5, supporting leg; 51, base; 52, supporting column; 6, heat dissipation channel; 7, FPC line interface. DETAILED DESCRIPTION
[0016] The following will be described in detail in combination with the accompanying Figures 1-2 The present application will be further described in detail.
[0017] The embodiment of the present application discloses a chip testing tool. Referring to Figure 1 and Figure 2 , the testing tool comprises an adapter plate 1, the adapter plate 1 is used for mounting a chip to be tested, the adapter plate 1 is provided with a downwardly recessed detection port 2 for placing the chip to be tested, the bottom wall of the detection port 2 is provided with a plurality of slots 3 for inserting the pins of the chip, the inner wall of the slot 3 is provided with a conductive layer 31, the conductive layer 31 is a copper plating layer, the thickness of the copper plating layer is 5-10 μm, which helps to ensure good electrical connection between the pins of the chip and the test circuit; a test fixture 4, the test fixture 4 is installed on the adapter plate 1, the test fixture 4 is used for clamping the chip to be tested on the adapter plate 1, the test fixture 4 is provided with a clamping hole 41 for clamping the chip to be tested and then falling into the detection port 2; an FPC line interface 7, the FPC line interface 7 is installed on the adapter plate 1, so that after the pins of the chip to be tested are inserted into the slot 3, the output end of the pin of the chip to be tested is connected to the connection end of the FPC line interface 7 through the circuit; the FPC line interface 7 is externally connected to a data acquisition system.
[0018] Referring to Figure 1 andFigure 2 The card hole 41 is square, and a clearance groove 42 is arranged at each of the four corners of the card hole 41, so as to facilitate the workers to take and place the chip to be tested and facilitate the fingers to be placed. The auxiliary holes 43 are arranged around the test fixture 4 and communicate with the card hole 41. The bottom of the adapter plate 1 is provided with the support feet 5 with adjustable height, so that the adapter plate 1 can be kept horizontal on different planes through the support feet 5. The support feet 5 include the support column 52 and the hemispherical base 51. One end of the support column 52 in the length direction is fixedly connected to the base 51, and the other end is threadedly connected to the adapter plate 1. The arc surface of the hemispherical base 51 is used to abut against the placing plane. The adapter plate 1 is provided with the heat dissipation channels 6, which communicate with the detection opening 2, and are beneficial to the heat dissipation of the chip during the test.
[0019] The implementation principle of the chip test tool is as follows: when the chip test tool is actually used, first, the adapter plate 1 is placed on a suitable plane and kept horizontal through the adjustment of the support feet 5. Then, the chip to be tested is placed into the card hole 41 of the test fixture 4, and the chip falls into the detection opening 2 of the adapter plate 1 through the card hole 41, and the chip pin is inserted into the slot 3 of the bottom wall of the detection opening 2. At this time, the chip is clamped and fixed by the test fixture 4, the chip pin is connected in circuit with the FPC line interface through the conductive layer 31 of the inner wall of the slot 3, and the external data acquisition system can start to test the chip to be tested. During the test, the heat dissipation channels 6 can dissipate heat for the chip, so as to ensure the stability of the test environment.
[0020] The above are the preferred embodiments of the present application, and do not limit the protection scope of the present application. Therefore, equivalent changes made on the basis of the structure, shape and principle of the present application should be covered within the protection scope of the present application.
Claims
1. A chip testing tool, characterized by: The application relates to a chip testing device, which comprises an adapter plate (1) for mounting a chip to be tested, wherein a detection opening (2) for placing the chip to be tested is concavely arranged downwards on the adapter plate (1), and a bottom wall of the detection opening (2) is provided with a plurality of insertion grooves (3) for inserting chip pins; A test clamp (4) is mounted on the adapter plate (1) and used for clamping the chip to be tested on the adapter plate (1), wherein a clamping hole (41) is formed in the test clamp (4) and used for clamping the chip to fall into the detection opening (2); An FPC line interface (7) is mounted on the adapter plate (1), so that, after the chip pins of the chip to be tested are inserted into the insertion grooves (3), the chip pin output ends are connected to the connection end of the FPC line interface (7) through a circuit; and the FPC line interface (7) is externally connected to a data acquisition system.
2. The chip testing tool of claim 1, wherein: The clamping hole (41) is square, and a clearance groove (42) is formed at each of four corners of the clamping hole (41).
3. The chip testing tool of claim 2, wherein: Auxiliary holes (43) are formed around the test clamp (4) and communicated with the clamping hole (41).
4. The chip testing tool of claim 1, wherein: An electrically-conductive layer (31) is arranged on the inner side wall of the insertion groove (3) and has a thickness of 5-10 mu m.
5. The chip testing tool of claim 1, wherein: An adjustable height supporting leg (5) is arranged at the bottom of the adapter plate (1) and used for keeping the adapter plate (1) horizontal on different planes.
6. The chip testing tool of claim 5, wherein: The supporting leg (5) comprises a supporting column (52) and a hemispherical base (51), one end of the supporting column (52) is fixedly connected to the base (51) in the length direction, the other end is threadedly connected to the adapter plate (1), and the arc surface of the hemispherical base (51) is used for abutting against a placing plane.
7. The chip testing tool of claim 1, wherein: A plurality of heat dissipation channels (6) are arranged on the adapter plate (1) and communicated with the detection opening (2).