Memory

Abstract

The utility model relates to the technical field of storage, and provides a memory which comprises a shell, a first transmission interface, a main control chip arranged in the shell, second transmission interfaces and flash memory chips which are arranged in the shell and are in one-to-one correspondence with the second transmission interfaces, the housing is provided with second transmit-receive keys in one-to-one correspondence with the second transmission interfaces and first transmit-receive keys in one-to-one correspondence with the second transmit-receive keys. The main control chip is electrically connected with the first transmission interface, the flash memory chip, the second transmission interface, the second transceiving key and the first transceiving key; and when the first transceiving key and / or the second transceiving key are / is clicked, data on the first equipment connected with the first transmission interface is interacted to the second equipment connected with the second transmission interface. The memory provided by the utility model can be used for conveniently and directly transmitting data between equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a memory. BACKGROUND

[0002] U disk, namely USB flash drive, is a kind of micro high-capacity mobile storage product using USB interface without physical drive. It is connected with computer through USB interface to realize the function of plug and play. The emergence of U disk is a great breakthrough in the field of mobile storage technology. It is small and portable, and is especially suitable for carrying around. It can exchange data at any time and anywhere, and is an ideal mobile office and data storage exchange product.

[0003] However, the existing U disk only realizes the transmission of files between U disk and computer, and fails to realize the direct transmission of files between computers. If U disk is used to realize the transmission of files between computers, not only U disk needs to be repeatedly moved and plugged, but also the computer needs to be repeatedly read, which is not only inconvenient to operate, but also time-consuming. CONTENT OF THE UTILITY MODEL

[0004] The present application provides a memory which can conveniently transmit data directly between devices.

[0005] The present application provides a memory, which comprises a shell, a first transmission interface, a master control chip built-in the shell, at least one second transmission interface and a flash memory chip built-in the shell corresponding to the second transmission interface;

[0006] The shell is provided with a second transceiver key corresponding to the second transmission interface and a first transceiver key corresponding to the second transceiver key;

[0007] The master control chip is electrically connected with the first transmission interface, the flash memory chip, the second transmission interface, the second transceiver key and the first transceiver key;

[0008] When the first transceiver key is pressed, the data on the first device connected with the first transmission interface is transmitted into the corresponding flash memory chip, and then when the second transceiver key is pressed, the data in the flash memory chip is transmitted to the second device connected with the second transmission interface through the second transmission interface; or when the second transceiver key is pressed, the data on the second device connected with the second transmission interface is transmitted into the corresponding flash memory chip, and then when the first transceiver key is pressed, the data in the flash memory chip is transmitted to the first device connected with the first transmission interface through the first transmission interface.

[0009] From the above technical solutions provided by the present application, the memory includes a shell, a first transmission interface, a master control chip built-in the shell, a second transmission interface and a flash memory chip built-in the shell and corresponding to the second transmission interface, the shell is provided with a second transceiver key corresponding to the second transmission interface and a first transceiver key corresponding to the second transceiver key. Compared with the inconvenience of repeatedly moving and plugging the U disk for realizing the file transmission between computers using the existing U disk, when the first transceiver key of the memory of the present application is pressed, the first transmission interface transmits the data on the first device connected thereto into the corresponding flash memory chip, and then the second transceiver key is pressed, the data in the flash memory chip is transmitted to the second device connected with the second transmission interface through the second transmission interface; or when the second transceiver key is pressed, the second transmission interface transmits the data on the second device connected with the second transmission interface into the corresponding flash memory chip, and then the first transceiver key is pressed, the data in the flash memory chip is transmitted to the first device connected with the first transmission interface through the first transmission interface, therefore, the present application can realize the direct data transmission between devices without unplugging the memory, which is convenient to operate. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0011] Figure 1 is a structural schematic diagram of the memory provided by the present application;

[0012] Figure 2 is a structural schematic diagram of the memory provided by another embodiment of the present application;

[0013] Figure 3 is a structural schematic diagram of the memory provided by another embodiment of the present application;

[0014] Figure 4 is a structural schematic diagram of the memory provided by another embodiment of the present application;

[0015] Figure 5 is a structural schematic diagram of the memory provided by another embodiment of the present application;

[0016] Figure 6 is a structural schematic diagram of the memory provided by another embodiment of the present application;

[0017] Figure 7a is a structural schematic diagram of the memory provided by another embodiment of the present application;

[0018] Figure 7b is a structural schematic diagram of a memory provided by another embodiment of the present application. DETAILED DESCRIPTION

[0019] Embodiments of the present application will be described in more detail by referring to the drawings. Although embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present application will be more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0020] The terminology used in the present application is merely for the purpose of describing particular embodiments and is not intended to limit the present application. As used in the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used herein, refer to and encompass any or all possible combinations of one or more of the associated listed items.

[0021] It should be understood that although the terms "first," "second," "third," etc. can be employed in the present application to describe various information, such information should not be limited by these terms. These terms are only used to distinguish one piece of information from another. For example, a first information can also be termed a second information, and, similarly, a second information can also be termed a first information, without departing from the scope of the present application. Therefore, features defined with "first," "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0022] In the specification of the present application, the sizes of the various parts shown in the drawings are not drawn in accordance with the actual proportions.

[0023] The existing U disk only realizes the transmission of files between the U disk and the computer, and fails to realize the direct transmission of files between computers. If the U disk is used to realize the transmission of files between computers, not only the U disk needs to be repeatedly moved and plugged, but also the computer needs to be repeatedly read, which is not only inconvenient to operate, but also time-consuming.

[0024] In view of the above problems, the embodiments of the present application provide a memory which can conveniently transmit data directly between devices.

[0025] The memory of the embodiment of the application comprises a shell, a first transmission interface, a master control chip built in the shell, a second transmission interface, and a flash memory chip built in the shell and corresponding to the second transmission interface; the shell is provided with a second transceiver key corresponding to the second transmission interface and a first transceiver key corresponding to the second transceiver key; the master control chip is electrically connected with the first transmission interface, the flash memory chip, the second transmission interface, the second transceiver key, and the first transceiver key; when the first transceiver key is pressed, the first transmission interface transmits the data on the first device connected therewith into the corresponding flash memory chip; then the second transceiver key is pressed, and the data in the flash memory chip is transmitted to the second device connected with the second transmission interface through the second transmission interface; or when the second transceiver key is pressed, the second transmission interface transmits the data on the second device connected therewith into the corresponding flash memory chip; then the first transceiver key is pressed, and the data in the flash memory chip is transmitted to the first device connected with the first transmission interface through the first transmission interface. That is, the first transmission interface can transmit the data on the first device (for example, a computer or other electronic device) connected therewith to the second device (for example, another computer or other electronic device) connected with the second transmission interface through the second transmission interface, or transmit the data on the second device (for example, a computer or other electronic device) connected therewith to the first device (for example, a computer or other electronic device) connected with the first transmission interface through the second transmission interface. Compared with the inconvenience of repeatedly moving and plugging the existing U disk to realize the file transmission between computers, when the first transceiver key is pressed, the first transmission interface transmits the data on the first device connected therewith into the corresponding flash memory chip; then the second transceiver key is pressed, and the data in the flash memory chip is transmitted to the second device connected with the second transmission interface through the second transmission interface; or when the second transceiver key is pressed, the second transmission interface transmits the data on the second device connected therewith into the corresponding flash memory chip; then the first transceiver key is pressed, and the data in the flash memory chip is transmitted to the first device connected with the first transmission interface through the first transmission interface. Therefore, the application can realize the direct data transmission between devices without unplugging the memory, which is convenient to operate.

[0026] It should be noted that the number of flash memory chips, second transceiver keys, and first transceiver keys corresponds to the number of second transmission interfaces, and the number of second transmission interfaces can be one, two, or more. In the embodiment, a memory comprising three second transmission interfaces, three flash memory chips, three second transceiver keys, three first transceiver keys, and three indicator lights is taken as an example to illustrate the technical solution of the application. As shown in the accompanying Figure 1 The memory further comprises indicator lights, which are arranged on the shell and correspond to the second transceiver keys one by one, and are electrically connected with the master control chip. The indicator lights can prompt whether the transmission path is established, the transmission state, and the like, which will be described in detail below.

[0027] Figure 1 The memory of the example mainly comprises a shell 15, a first transmission interface 12, a master chip 11 built in the shell 15, three second transmission interfaces 13, and three flash memory chips 14 corresponding to the three second transmission interfaces 13 built in the shell 15. The shell 15 is provided with three second transceiver keys 16 (as shown by the ellipses in the figure) corresponding to the three second transmission interfaces 13, first transceiver keys 18 (as shown by the regular pentagons in the figure) corresponding to the three second transceiver keys 16, and indicator lights 17 corresponding to the three second transceiver keys 16 or the three first transceiver keys 18, as shown by the circles in the figure. The master chip 11 is electrically connected with the first transmission interface 12, the three second transmission interfaces 13, the three second transceiver keys 16, the three first transceiver keys 18, and the three indicator lights 17, which means that the master chip 11 can control the first transmission interface 12, the second transmission interface 13, the second transceiver key 16, the first transceiver key 18, and the indicator light 17.

[0028] The three flash memory chips 14 can store files in categories to avoid centralized storage in one space. When the first transmission interface 12 is connected with a device (for example, a computer, a mobile phone, or other electronic devices), the three flash memory chips 14 are displayed in the form of icons on the device, and the user operates the files on the device to store them in the three flash memory chips 14 or any one of the flash memory chips, which automatically allocates the corresponding storage space and transmission path. In this way, each corresponding file can be accurately transmitted to the device connected with the second transmission interface 13, without the need for each device connected with the second transmission interface 13 to pick files from the memory.

[0029] Figure 1 The three indicator lights 17 are mainly used to indicate whether the transmission path is established. For example, when the first transmission interface 12 is connected with a computer, the first first transceiver key (from top to bottom in the figure, the first first transceiver key is arranged at the top, and the third first transceiver key is arranged at the bottom) is pressed, the first indicator light 17 (from top to bottom in the figure, the first indicator light is arranged at the top, and the third indicator light is arranged at the bottom) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first flash memory chip 14 (from top to bottom in the figure, the first flash memory chip 14 is arranged at the top, and the third flash memory chip 14 is arranged at the bottom) has been established, and data can be transmitted from the computer connected with the first transmission interface 12 to the first flash memory chip 14. When the first first transceiver key (from top to bottom in the figure, the first first transceiver key is arranged at the top, and the third first transceiver key is arranged at the bottom) is pressed, if the first second transmission interface 13 (from top to bottom in the figure, the first second transmission interface 13 is arranged at the top, and the third second transmission interface 13 is arranged at the bottom) is connected with a device, the data can be transmitted from the computer connected with the first transmission interface 12 to the device connected with the first second transmission interface 13. Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 ​​​​For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13. Figure 1 For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13.

[0030] For example, when the first transmission interface 12 and the first second transmission interface 13 are connected to a computer respectively, and the first first transceiver key (1) and the first second transceiver key (2) are pressed, the first indicator light 17 (1) is lit or flashes, indicating that the transmission path from the first transmission interface 12 to the first second transmission interface 13 has been established, and data can be transmitted from the computer connected to the first transmission interface 12 to the computer connected to the first second transmission interface 13.

[0031] It should be noted that the above operation is reversible, that is, when it is needed to transmit data from the device connected to the second transmission interface 13 to the device connected to the first transmission interface 12, the first transceiving key 18 and / or the second transceiving key 16 can be pressed, and the corresponding indicator light is lit, indicating that the transmission path has been established, and the data transmission can be started. For example, when it is needed to send a file from the second device connected to the first second transmission interface 13 to the first device connected to the first transmission interface 12, the first second transceiving key and the first first transceiving key are pressed, and the file can be transmitted from the second device to the first device. Figure 1

[0032] Figure 1 It should be noted that the above operation is reversible, that is, when it is needed to transmit data from the device connected to the second transmission interface 13 to the device connected to the first transmission interface 12, the first transceiving key 18 and / or the second transceiving key 16 can be pressed, and the corresponding indicator light is lit, indicating that the transmission path has been established, and the data transmission can be started. For example, when it is needed to send a file from the second device connected to the first second transmission interface 13 to the first device connected to the first transmission interface 12, the first second transceiving key and the first first transceiving key are pressed, and the file can be transmitted from the second device to the first device. Figure 2 The memory of the example can further include a data routing support chip electrically connected with the master control chip 11, the first transmission interface 12, the at least one flash memory chip 14, and the at least one second transmission interface 13. The data routing support chip can be integrated in the master control chip, as shown in the memory provided by another embodiment of the present application. Figure 3 The data routing support chip is responsible for intelligently managing and coordinating data flow, so as to realize efficient data transmission between multiple devices connected with the memory. For example, a device A (for example, a PC) sends a large file to the memory through the first transmission interface 12; the data routing support chip determines through which of the three second transmission interfaces 13 to exchange data by analyzing the data source and the target receiving device; after routing scheduling, it is directly transmitted to the cache of the three flash memory chips 14 of the memory and transmitted to a device B (for example, another computer) through the second of the three second transmission interfaces 13; at the same time, a device C (for example, a printer) can receive a small file through the third of the three second transmission interfaces 13, and the data routing support chip forwards it to the third of the three second transmission interfaces 13 and performs parallel data transmission.

[0033] The data routing support chip can be independent of the master control chip and work cooperatively with the master control chip 11, the first transmission interface 12, the at least one flash memory chip 14, and the at least one second transmission interface 13 through electrical connection, as shown in the memory provided by another embodiment of the present application. Figure 2 The data routing support chip can be independent of the master control chip and work cooperatively with the master control chip 11, the first transmission interface 12, the at least one flash memory chip 14, and the at least one second transmission interface 13 through electrical connection, as shown in the memory provided by another embodiment of the present application.

[0034] It should be noted that the above operation is reversible, that is, when it is needed to transmit data from the device connected to the second transmission interface 13 to the device connected to the first transmission interface 12, the first transceiving key 18 and / or the second transceiving key 16 can be pressed, and the corresponding indicator light is lit, indicating that the transmission path has been established, and the data transmission can be started. For example, when it is needed to send a file from the second device connected to the first second transmission interface 13 to the first device connected to the first transmission interface 12, the first second transceiving key and the first first transceiving key are pressed, and the file can be transmitted from the second device to the first device. Figure 3 or Figure 2 ​The example data routing support chip can be a network router chip, for example, a high-performance network router chip produced by companies such as Broadcom and Qualcomm, for example, the Broadcom StrataXGS series or the Qualcomm IPQ series, which are usually used to process the routing of a large number of data packets and can support intelligent data exchange between multiple devices. Figure 3 Or Figure 2 The example data routing support chip can also be a switching chip (Switching Chips), for example, the Prestera series switching chips of Marvell, which are specially used for high-bandwidth, low-latency data exchange applications and can efficiently process data transmission between multiple channels of devices and support data flow management between multiple devices. Figure 3 Or Figure 1 The example data routing support chip can also be a smart control chip (SoC), for example, the BlueField data center processor of NVIDIA, which is embedded with multiple network interfaces and routing functions and can intelligently allocate bandwidth and schedule data flow between multiple devices.

[0035] Figure 1 The example memory can be affected by the size of the data when transmitting large files, in order to reduce the amount of data during transmission and improve transmission efficiency, Figure 4 The example memory can also include a hardware compression chip that is electrically connected to the main control chip 11, the first transmission interface 12, at least one flash memory chip 14, and at least one second transmission interface 13. Similar to the data routing support chip, the hardware compression chip can also be integrated into the main control chip 11, for example, as shown in Figure 1 The storage device provided by another embodiment of the present application. The hardware compression chip is used to compress and decompress data when the data is transmitted between devices to reduce bandwidth requirements and improve transmission efficiency. For example, a large capacity file needs to be transmitted from a first device connected to the first transmission interface 12 to a second device connected to any one of the three second transmission interfaces 13, and before transmission, the hardware compression chip compresses the large capacity file and then transmits it through the path between the first device and the second device, which can greatly improve the transmission efficiency. Figure 4 Or Figure 5 The example data routing support chip can be a network router chip, for example, a high-performance network router chip produced by companies such as Broadcom and Qualcomm, for example, the Broadcom StrataXGS series or the Qualcomm IPQ series, which are usually used to process the routing of a large number of data packets and can support intelligent data exchange between multiple devices.

[0036] The hardware compression chip can be independent of the main control chip and work cooperatively with the main control chip 11, the first transmission interface 12, at least one flash memory chip 14, and at least one second transmission interface 13 through electrical connection, for example, as shown in Figure 1The memory provided by another embodiment of the application is shown. The master chip 11 determines whether to start the hardware compression function according to factors such as data type, target bandwidth, and transmission delay. Once it is determined to enable the hardware compression function, the master chip 11 starts the compression or decompression process through a control instruction, and transmits data to the hardware compression chip for compression and transmission. In an embodiment of the application, the acceleration chip based on the LZ77 and LZ4 algorithms, such as the series of acceleration chips of LZ77, LZ4, Snappy, the compression accelerator of Broadcom, the GPU acceleration compression module of NVIDIA, and the special compression chip of Level 3 and CXL compression card, can be integrated into the master chip 11 or independent of the master chip 11 as the hardware compression chip.

[0037] In view of the fact that the memory may need to be optimized in terms of power consumption during long-time use, in order to improve the endurance of the memory through low-power design, especially in the scenarios of wireless transmission or long-time operation, Figure 6 The memory of the example can also include a voltage frequency adjuster, which is electrically connected to the master chip 11, such as Figure 6 The memory provided by another embodiment of the application is shown. In an embodiment of the application, the voltage frequency adjuster can include a voltage regulator, a clock generator, and a power management chip, etc. to achieve this. These hardware components can dynamically adjust the working frequency and voltage according to the load change in the master chip 11. Specifically, the voltage regulator works with the clock generator in the voltage frequency adjuster to dynamically adjust the output voltage. The clock generator provides a clock signal to the processor or other digital circuits to control their working frequency. By adjusting the clock frequency, the working speed of the master chip 11 can be dynamically reduced or increased. The power management chip adjusts the voltage output of different voltage rails according to the working load of the master chip 11 to reduce unnecessary power consumption.

[0038] In an embodiment of the application, Figure 7a The voltage frequency adjuster of the example can be an ADM8317 power management chip.

[0039] In view of the fact that the devices connected by the first transmission interface 12 and the second transmission interface 13 have different data throughput capabilities, in order to coordinate the synchronization and efficient access of data transmission between the two devices, in another embodiment of the application, the memory can also include at least one buffer corresponding to the flash chip 14, which is electrically connected to the master chip 14, the first transmission interface 12, and at least one second transmission interface 13. For example, the buffer can be DDR4 or LPDDR5.

[0040] In order to improve the use range of the memory, the memory further comprises a first transmission interface and a second transmission interface connected through a data line between the shell, which can increase the transmission distance between devices; and the data line is telescopic, and by adjusting the length of the telescopic data line, the distance is more flexible, such as Figure 7b and ​ The structure diagram of the memory provided by another embodiment of the application is shown.

[0041] In the above embodiment, the first transmission interface and the second transmission interface can be tpcy-c interfaces.

[0042] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the application. The specific working process of the units and modules in the above device can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0043] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in a certain embodiment can be referred to the related description of other embodiments.

[0044] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0045] In the embodiments of the present application, it should be understood that the disclosed apparatuses / devices and methods can be implemented in other manners. For example, the embodiments of the apparatuses / devices described above are merely illustrative. For example, the division of the modules or units can be different, and each can include a plurality of units or a plurality of modules. For example, a plurality of units or a plurality of modules can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0046] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0047] In addition, the functional units in each embodiment of the present application can be integrated into a processing unit, or each unit can be a physically independent unit, or two or more units can be integrated into a unit.

[0048] The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A memory, comprising: The memory comprises a shell, a first transmission interface, a master control chip built-in the shell, a second transmission interface and a flash memory chip built-in the shell corresponding to the second transmission interface; The shell is provided with a second transceiver key corresponding to the second transmission interface and a first transceiver key corresponding to the second transceiver key; The master control chip is electrically connected with the first transmission interface, the flash memory chip, the second transmission interface, the second transceiver key and the first transceiver key; When the first transceiver key is pressed, the first transmission interface transmits the data on the first device connected therewith into the corresponding flash memory chip, and when the second transceiver key is pressed, the data in the flash memory chip is transmitted to the second device connected with the second transmission interface through the second transmission interface; or when the second transceiver key is pressed, the second transmission interface transmits the data on the second device connected therewith into the corresponding flash memory chip, and when the first transceiver key is pressed, the data in the flash memory chip is transmitted to the first device connected with the first transmission interface through the first transmission interface.

2. The memory of claim 1, wherein, The memory further comprises an indicator light provided on the shell and corresponding to the second transceiver key, and the indicator light is electrically connected with the master control chip.

3. The memory of claim 1, wherein, The first transmission interface and the second transmission interface are provided with a retractable data line between the shell.

4. The memory of claim 1, wherein, The memory further comprises a data routing support chip, and the data routing support chip is electrically connected with the master control chip, the first transmission interface, the flash memory chip and the second transmission interface.

5. The memory of claim 4, wherein, The data routing support chip is integrated in the master control chip or independent of the master control chip.

6. The memory of claim 1, wherein, The memory further comprises a hardware compression chip, and the hardware compression chip is electrically connected with the master control chip, the first transmission interface, the flash memory chip and the second transmission interface.

7. The memory of claim 6, wherein, The hardware compression chip is integrated in the master control chip or independent of the master control chip.

8. The memory of claim 1, wherein, The memory further comprises a voltage frequency adjuster, and the voltage frequency adjuster is electrically connected with the master control chip.

9. The memory of claim 8, wherein, The voltage frequency adjuster is an ADM8317 power management chip.

10. The memory of any one of claims 1 to 9, wherein, The memory further comprises a buffer corresponding to the flash memory chip, and the buffer is electrically connected with the master control chip, the first transmission interface and the second transmission interface.

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