Data protection circuit

Abstract

The utility model relates to a data protection circuit, which is characterized in that the anode of a voltage-regulator tube is grounded, and the cathode of the voltage-regulator tube is respectively connected with the inverting input end of an operational amplifier and a sixth resistor; one end of the seventh resistor is grounded, and the other end is respectively connected with the non-inverting input end of the operational amplifier and the eighth resistor; the other end of the sixth resistor is respectively connected with the anode of the second diode, the anode of the fourth diode and the fifth resistor; power voltage is connected with the anode of the second diode and one end of the operational amplifier. The cathode of the second diode is connected with the anode of the third diode; the cathode of the third diode is respectively connected with the anode of a fifth diode and the anode of a 3.6 V battery through a ninth resistor; the cathode of the fourth diode and the cathode of the fifth diode are connected with the vcc end of the data storage chip. The negative electrode of the 3.6 V battery is grounded; the other end of the fifth resistor is connected with an eighth resistor; the other end of the operational amplifier is grounded. Control signals of a circuit with data are shielded in advance, and reliable data protection is achieved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a data protection circuit. BACKGROUND

[0002] Data protection circuit, generally in many equipment's design all have, they generally adopt in the circuit that needs protection just add a spare battery, cannot do to the control signal of the circuit that has data to carry out in advance shielding, makes it unable reliably protects data.

[0003] Therefore, provide a kind of data protection circuit. INVENTION CONTENTS

[0004] The utility model aims at overcoming the defect of prior art and provides a kind of data protection circuit, to the control signal of the circuit that has data to carry out in advance shielding, reliably to data protection.

[0005] The technical scheme for achieving the above-mentioned purposes is:

[0006] A kind of data protection circuit, comprising: stabilivolt, seventh resistance, power supply voltage, data piece selection signal, write signal and clock piece selection signal,

[0007] The anode of stabilivolt is connected, and the cathode is connected to the inverting input terminal of operational amplifier and sixth resistance respectively;

[0008] One end of the seventh resistance is grounded, and the other end is connected to the noninverting input terminal of operational amplifier and eighth resistance respectively;

[0009] The other end of the sixth resistance is connected to the anode of second diode, the anode of fourth diode and fifth resistance respectively;

[0010] The power supply voltage is connected to the anode of second diode and one end of operational amplifier respectively;

[0011] The cathode of second diode is connected to the anode of third diode;

[0012] The cathode of third diode is connected to the anode of fifth diode and the positive pole of 3.6V battery through ninth resistance respectively;

[0013] The cathode of fourth diode and the cathode of fifth diode are connected to the vcc end of data storage chip;

[0014] The negative pole of 3.6V battery is grounded;

[0015] The other end of the fifth resistance is connected to the eighth resistance;

[0016] The other end of operational amplifier is grounded;

[0017] The output end of the operational amplifier is connected with the other end of the eighth resistor, the input end of the first NAND gate, the input end of the second NAND gate and the input end of the third NAND gate respectively.

[0018] The other input end of the first NAND gate is connected with a data chip selection signal, one end of the first NAND gate is connected with the vcc end of the data storage chip, the other end is grounded, and the output end is connected with the CS end of the data storage chip.

[0019] The input end of the first NAND gate is connected with a write signal, one end of the first NAND gate is connected with the power supply voltage, the other end is grounded, and the output end is connected with the other input end of the second NAND gate.

[0020] The input end of the second NAND gate is connected with a clock chip selection signal, and the output end of the second NAND gate is connected with the other input end of the third NAND gate.

[0021] The output end of the first NAND gate is connected with the WR end of the data storage chip and the WR end of the clock chip respectively.

[0022] The output end of the second NAND gate is connected with the CS end of the clock chip.

[0023] Preferably, the resistance value of the fifth resistor is R1, and the resistance value of the seventh resistor is R2, and the voltage of the non-inverting input end of the operational amplifier is R2 / (R1+R2)*power supply voltage.

[0024] Preferably, when the power supply voltage is higher than 4.3v, the output end of the operational amplifier outputs high voltage, and the data chip selection signal, the write signal and the clock chip selection signal perform read-write operation on the data storage chip and the clock chip through the first NAND gate, the second NAND gate and the third NAND gate.

[0025] Preferably, when the power supply voltage is lower than 4.3v, the output end of the operational amplifier outputs low voltage, controls the first NAND gate, the second NAND gate and the third NAND gate to output high level, and blocks the data chip selection signal, the write signal and the clock chip selection signal, so as to stop the operation on the data storage chip and the clock chip in advance before the interference signal or power failure.

[0026] The utility model discloses a beneficial effect is: in the utility model, when power voltage is higher than 4.3v, the output end of operational amplifier exports high voltage, and data piece selects signal, write signal and clock piece selects signal through first NAND gate, second NAND gate and third NAND gate to data storage chip and clock chip read and write operation are carried out, when power voltage is lower than 4.3v, the output end of operational amplifier exports low voltage, and control first NAND gate, second NAND gate and third NAND gate export high level, and close data piece selects signal, write signal and clock piece selects signal, stop operating to data storage chip and clock chip in advance before interference signal or power failure, to reach the protection effect of data, in order to not lose data in the state of power failure, add spare 3.6v battery in circuit design, when there is electricity, through the second diode, third diode and ninth resistance to spare battery charging, through the fourth diode and the fifth diode or relation, when there is electricity and no electricity, carry out automatic seamless switching, and add electricity to data storage chip, guarantee that data is not lost when there is no electricity. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a circuit diagram of the data protection circuit of the utility model. DETAILED DESCRIPTION

[0028] The technical scheme of the utility model will be described clearly and completely below in connection with the drawings. In the description of the utility model, it needs to be explained that the orientation or position relation of the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like is based on the orientation or position relation shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as the restriction of the utility model. In addition, the terms "first", "second", "third" are only for the description purpose, and cannot be understood as indicating or implying the opposite importance.

[0029] The utility model will be described further below in connection with the drawings.

[0030] For example, Figure 1As shown, a data protection circuit comprises: a voltage stabilizing tube D1, a seventh resistor R7, a power supply voltage VCC, a data chip selection signal, a write signal and a clock chip selection signal, the anode of the voltage stabilizing tube D1 is connected to the ground, and the cathode is connected to the inverting input terminal of an operational amplifier U1 and a sixth resistor R6 respectively; one end of the seventh resistor R7 is connected to the ground, and the other end is connected to the non-inverting input terminal of the operational amplifier U1 and an eighth resistor R8 respectively; the other end of the sixth resistor R6 is connected to the anode of a second diode D2, the anode of a fourth diode D4 and a fifth resistor R5 respectively; the power supply voltage VCC is connected to the anode of the second diode D2 and one end of the operational amplifier U1 respectively; the cathode of the second diode D2 is connected to the anode of a third diode D3; the cathode of the third diode D3 is connected to the anode of a fifth diode D5 and the positive pole of a 3.6V battery through a ninth resistor R9 respectively; the cathode of the fourth diode D4 and the cathode of the fifth diode D5 are connected to the vcc end of a data storage chip respectively; the negative pole of the 3.6V battery is connected to the ground; the other end of the fifth resistor R5 is connected to the eighth resistor R8; the other end of the operational amplifier U1 is connected to the ground; the output terminal of the operational amplifier U1 is connected to the other end of the eighth resistor R8, the input terminal of a first NAND gate U4, the input terminal of a second NAND gate U5 and the input terminal of a third NAND gate U6 respectively; the other input terminal of the first NAND gate U4 is connected to the data chip selection signal, one end of the first NAND gate U4 is connected to the vcc end of the data storage chip, the other end is connected to the ground, and the output terminal is connected to the CS end of the data storage chip; the write signal is connected to the input terminal of a first NOT gate U2, one end of the first NOT gate U2 is connected to the power supply voltage VCC, the other end is connected to the ground, and the output terminal is connected to the other input terminal of the second NAND gate U5; the clock chip selection signal is connected to the input terminal of a second NOT gate U3, and the output terminal of the second NOT gate U3 is connected to the other input terminal of the third NAND gate U6; the output terminal of the first NOT gate U2 is connected to the WR end of the data storage chip and the WR end of a clock chip respectively; and the output terminal of the second NOT gate U3 is connected to the cs end of the clock chip.

[0031] In the embodiment, the resistance value of the fifth resistor R5 is R1, and the resistance value of the seventh resistor R7 is R2, so the voltage at the non-inverting input terminal of the operational amplifier U1 = R2 / R1 + R2*power supply voltage VCC.

[0032] In the embodiment, when the power supply voltage VCC is higher than 4.3V, the output terminal of the operational amplifier U1 outputs a high voltage, and the data chip selection signal, the write signal and the clock chip selection signal perform read and write operations on the data storage chip and the clock chip through the first NAND gate U4, the second NAND gate U5 and the third NAND gate U6.

[0033] In the embodiment, when the power supply voltage VCC is lower than 4.3V, the output terminal of the operational amplifier U1 outputs a low voltage, controls the first NAND gate U4, the second NAND gate U5 and the third NAND gate U6 to output a high level, and blocks the data chip selection signal, the write signal and the clock chip selection signal, so as to stop the operation on the data storage chip and the clock chip in advance before the interference signal or power failure.

[0034] In the embodiment, in order to not lose data in the state of power failure, a backup 3.6V battery is added in the circuit design, when there is power, the backup battery is charged through the second diode D2, the third diode D3 and the ninth resistor R9, and through the relationship of the fourth diode D4 and the fifth diode D5, automatic seamless switching is carried out when there is power and when there is no power, power is added to the data storage chip, so that data is not lost when there is no power.

[0035] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data protection circuit, characterized by The application relates to a data storage chip and clock chip read-write control circuit, which comprises the following components: a voltage stabilizing tube (D1), a seventh resistor (R7), a power voltage (VCC), a data chip selection signal, a write signal and a clock chip selection signal, the anode of the voltage stabilizing tube (D1) is connected to the ground, and the cathode is connected to the inverting input end of an operational amplifier (U1) and a sixth resistor (R6) respectively; one end of the seventh resistor (R7) is connected to the ground, and the other end is connected to the non-inverting input end of the operational amplifier (U1) and an eighth resistor (R8) respectively; the other end of the sixth resistor (R6) is connected to the anode of a second diode (D2), the anode of a fourth diode (D4) and a fifth resistor (R5) respectively; the power voltage (VCC) is connected to the anode of the second diode (D2) and one end of the operational amplifier (U1) respectively; the cathode of the second diode (D2) is connected to the anode of a third diode (D3); the cathode of the third diode (D3) is connected to the anode of a fifth diode (D5) and the positive pole of a 3.6V battery through a ninth resistor (R9) respectively; the cathode of the fourth diode (D4) and the cathode of the fifth diode (D5) are both connected to the vcc end of a data storage chip; the negative pole of the 3.6V battery is connected to the ground; the other end of the fifth resistor (R5) is connected to the eighth resistor (R8); the other end of the operational amplifier (U1) is connected to the ground; the output end of the operational amplifier (U1) is connected to the other end of the eighth resistor (R8), the input end of a first NAND gate (U4), the input end of a second NAND gate (U5) and the input end of a third NAND gate (U6) respectively; the other input end of the first NAND gate (U4) is connected to the data chip selection signal, one end of the first NAND gate (U4) is connected to the vcc end of the data storage chip, the other end is connected to the ground, and the output end is connected to the CS end of the data storage chip; the write signal is connected to the input end of a first NOT gate (U2), one end of the first NOT gate (U2) is connected to the power voltage (VCC), the other end is connected to the ground, and the output end is connected to the other input end of the second NAND gate (U5); the clock chip selection signal is connected to the input end of a second NOT gate (U3), and the output end of the second NOT gate (U3) is connected to the other input end of the third NAND gate (U6); the output end of the first NOT gate (U2) is connected to the WR end of the data storage chip and the WR end of a clock chip respectively; the output end of the second NOT gate (U3) is connected to the CS end of the clock chip.

2. A data protection circuit according to claim 1, characterized in that If the resistance value of the fifth resistor (R5) is R1 and the resistance value of the seventh resistor (R7) is R2, then the voltage at the non-inverting input end of the operational amplifier (U1) is R2 / (R1+R2)*power voltage (VCC).

3. A data protection circuit according to claim 1, wherein, When the power voltage (VCC) is higher than 4.3V, the output end of the operational amplifier (U1) outputs high voltage, and the data chip selection signal, the write signal and the clock chip selection signal perform read-write operation on the data storage chip and the clock chip through the first NAND gate (U4), the second NAND gate (U5) and the third NAND gate (U6).

4. The data protection circuit of claim 1, wherein, When the power voltage (VCC) is lower than 4.3v, the output of the operational amplifier (U1) outputs low voltage, controls the first NAND gate (U4), the second NAND gate (U5) and the third NAND gate (U6) to output high level, and closes the data chip selection signal, the write signal and the clock chip selection signal, so as to stop the operation of the data storage chip and the clock chip in advance before the interference signal or power failure.

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