Band-gap reference circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a band-gap reference circuit, chip and electronic equipment, relate to integrated circuit technical field, include current control module, current mirror module and voltage output module, through current control module and current mirror module cooperation, generate the current of zero temperature coefficient, output the voltage output module. The zero-temperature-coefficient current is copied and output to the voltage output module through the current mirror module, then multiple zero-temperature-coefficient voltages are generated and output through the voltage output module according to the zero-temperature-coefficient current, and due to the fact that the voltage values of all the zero-temperature-coefficient voltages are different, the requirements for multiple voltage values can be met; and the adaptability of the band-gap reference circuit to various voltage value requirements is improved.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a bandgap reference circuit, chip, and electronic device. Background Technology

[0002] A bandgap reference circuit is an electronic circuit designed based on the band structure and temperature characteristics of semiconductor materials. It is used to output a reference voltage that is independent of temperature, i.e., a reference voltage with zero temperature coefficient.

[0003] In the prior art, the bandgap reference circuit outputs a fixed voltage value (typically 1.25 volts) with a zero temperature coefficient.

[0004] In the process of developing this application, the inventors discovered that the prior art has at least the following problems: since the voltage value of the output voltage of the bandgap reference circuit is fixed, it cannot meet the requirements for multiple voltage values, resulting in poor adaptability of the bandgap reference circuit to multiple voltage value requirements. Utility Model Content

[0005] This invention provides a bandgap reference circuit, chip, and electronic device to at least solve the problem in the prior art where the fixed voltage value of the output voltage of the bandgap reference circuit cannot meet the requirements for multiple voltage values, resulting in poor adaptability of the bandgap reference circuit to multiple voltage value requirements.

[0006] In a first aspect, this utility model provides a bandgap reference circuit, including: a current control module, a current mirror module, and a voltage output module;

[0007] The current control module is electrically connected to the current mirror module, and the current control module is used to cooperate with the current mirror module to generate a current with zero temperature coefficient.

[0008] The current mirror module is electrically connected to the voltage output module, and the current mirror module is used to copy the zero temperature coefficient current and output it to the voltage output module;

[0009] The voltage output module is used to generate and output multiple zero-temperature coefficient voltages based on the zero-temperature coefficient current.

[0010] The voltage value of each of the zero temperature coefficient voltages is different.

[0011] Optionally, the current mirror module includes a first transistor group, a second transistor group, and a third transistor group; a first terminal of the first transistor group is electrically connected to a first power supply, a second terminal of the first transistor group is electrically connected to a first terminal of the current control module, and a control terminal of the first transistor group is electrically connected to the control terminals of the second transistor group and the third transistor group, respectively; a first terminal of the second transistor group is electrically connected to the first power supply, and a second terminal of the second transistor group is electrically connected to a second terminal of the current control module; a first terminal of the third transistor group is electrically connected to the first power supply, a second terminal of the third transistor group is electrically connected to a first terminal of the voltage output module, and a control terminal of the third transistor group is electrically connected to the control terminal of the second transistor group; a third terminal of the current control module is electrically connected to the control terminals of the first transistor group, the second transistor group, and the third transistor group, respectively; and a second terminal of the voltage output module is grounded.

[0012] Optionally, the current control module includes an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth transistor group, and a fifth transistor group; the inverting input terminal of the operational amplifier is electrically connected to the first terminal of the third resistor and the first terminal of the fourth transistor group, respectively; the non-inverting input terminal of the operational amplifier is electrically connected to the first terminal of the first resistor and the first terminal of the second resistor, respectively; the output terminal of the operational amplifier is electrically connected to the control terminals of the first transistor group, the second transistor group, and the third transistor group, respectively; the first terminal of the first resistor is electrically connected to the second terminal of the second transistor group, and the second terminal of the first resistor is electrically connected to the first terminal of the fifth transistor group; the first terminal of the second resistor is electrically connected to the second terminal of the second transistor group, and the second terminal of the second resistor is grounded; the first terminal of the third resistor is electrically connected to the second terminal of the first transistor group, and the second terminal of the third resistor is grounded; the first terminal of the fourth transistor group is electrically connected to the second terminal of the first transistor group, and the control terminal of the fourth transistor group is electrically connected to the second terminal of the fourth transistor group, and the second terminal of the fourth transistor group is grounded; the control terminal of the fifth transistor group is electrically connected to the second terminal of the fifth transistor group, and the second terminal of the fifth transistor group is grounded.

[0013] Optionally, the fourth transistor group includes n first transistors, and the fifth transistor group includes m second transistors, where n is a positive integer greater than 1, m is a positive integer greater than or equal to 1, and the ratio of n to m is a positive integer greater than 1. In the fourth transistor group, the first terminal of the first first transistor is electrically connected to the second terminal of the first transistor group; the second terminal of the i-th first transistor is electrically connected to the first terminal of the (i+1)-th first transistor; the second terminal of the n-th first transistor is electrically connected to the control terminal of each first transistor, and the second terminal of the n-th first transistor is grounded, where i is a positive integer less than n. In the fifth transistor group, the first terminal of the first second transistor is electrically connected to the second terminal of the first resistor; the second terminal of the j-th second transistor is electrically connected to the first terminal of the (j+1)-th second transistor; the second terminal of the m-th second transistor is electrically connected to the control terminal of each second transistor, and the second terminal of the m-th second transistor is grounded, where j is a positive integer less than m.

[0014] Optionally, the first transistor may be a PNP transistor or an NPN transistor, and the second transistor may be a PNP transistor or an NPN transistor; the types of each first transistor and each second transistor are the same.

[0015] Optionally, the resistance value of the second resistor is equal to the resistance value of the third resistor.

[0016] Optionally, the voltage output module includes p fourth resistors, where p is a positive integer; the voltage output module also includes p voltage output terminals, each fourth resistor having a corresponding voltage output terminal; the first terminal of the first fourth resistor is electrically connected to the second terminal of the third transistor group; the first terminal of the kth fourth resistor is electrically connected to the voltage output terminal corresponding to the kth fourth resistor, and the second terminal of the kth fourth resistor is electrically connected to the first terminal of the (k+1)th fourth resistor; the second terminal of the pth fourth resistor is grounded, where k is a positive integer less than p.

[0017] Optionally, the first transistor group, the second transistor group, and the third transistor group are all transistor groups comprising q MOSFETs, where q is a positive integer; in the first transistor group, the first terminal of the first MOSFET is electrically connected to the first power supply; the second terminal of the r-th MOSFET is electrically connected to the first terminal of the (r+1)-th MOSFET; the second terminal of the q-th MOSFET is electrically connected to the first terminal of the current control module, where r is a positive integer less than q; in the second transistor group, the first terminal of the first MOSFET is electrically connected to the first power supply; the second terminal of the r-th MOSFET is electrically connected to the first terminal of the current control module. The second terminal of the S-transistor is electrically connected to the first terminal of the (r+1)th MOS transistor; the second terminal of the qth MOS transistor is electrically connected to the second terminal of the current control module; in the third transistor group, the first terminal of the first MOS transistor is electrically connected to the first power supply; the second terminal of the rth MOS transistor is electrically connected to the first terminal of the (r+1)th MOS transistor; the second terminal of the qth MOS transistor is electrically connected to the first terminal of the voltage output module; the control terminals of each MOS transistor are electrically connected to each other; the third terminal of the current control module is electrically connected to the control terminal of each MOS transistor.

[0018] Optionally, each of the MOS transistors is a PMOS transistor.

[0019] Optionally, the current mirror module includes a first transistor group, a second transistor group, a third transistor group, a sixth transistor group, and a seventh transistor group; a first terminal of the first transistor group is electrically connected to a first power supply, a second terminal of the first transistor group is electrically connected to the first terminal of the sixth transistor group, and a control terminal of the first transistor group is electrically connected to the control terminals of the second transistor group and the third transistor group, respectively; a first terminal of the second transistor group is electrically connected to the first power supply, and a second terminal of the second transistor group is electrically connected to the second terminal of the seventh transistor group; a first terminal of the third transistor group is electrically connected to the first power supply, a second terminal of the third transistor group is electrically connected to the first terminal of the voltage output module, and a control terminal of the third transistor group is electrically connected to the control terminal of the second transistor group; a second terminal of the sixth transistor group is electrically connected to the first terminal of the current control module, and a control terminal of the sixth transistor group is electrically connected to a second power supply; a second terminal of the seventh transistor group is electrically connected to the second terminal of the current control module, and a control terminal of the seventh transistor group is electrically connected to the second power supply; a third terminal of the current control module is electrically connected to the control terminals of the first transistor group, the second transistor group, and the third transistor group, respectively; and a second terminal of the voltage output module is grounded.

[0020] Secondly, embodiments of the present invention also provide a chip, including the bandgap reference circuit as described in the first aspect.

[0021] Thirdly, embodiments of the present invention also provide an electronic device, including a bandgap reference circuit as described in the first aspect, or a chip as described in the second aspect.

[0022] In this embodiment of the invention, a zero-temperature coefficient current is generated by the cooperation of the current control module and the current mirror module. The zero-temperature coefficient current is then copied by the current mirror module and output to the voltage output module. The voltage output module then generates and outputs multiple zero-temperature coefficient voltages based on the zero-temperature coefficient current. Since each zero-temperature coefficient voltage has a different voltage value, it can meet the requirements for multiple voltage values ​​and improve the adaptability of the bandgap reference circuit to multiple voltage value requirements. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a bandgap reference circuit provided in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the specific structure of a bandgap reference circuit provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of another bandgap reference circuit provided in this embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the specific structure of a transistor group including 7 MOS transistors provided in an embodiment of the present invention.

[0028] Reference numerals:

[0029] 10 - Current control module; 20 - Current mirror module; 30 - Voltage output module; 31 - Voltage output terminal; P - Operational amplifier; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; Q1 - First transistor group; Q2 - Second transistor group; Q3 - Third transistor group; Q4 - Fourth transistor group; Q5 - Fifth transistor group; Q6 - Sixth transistor group; Q7 - Seventh transistor group. Detailed Implementation

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] Reference Figure 1 This utility model provides a bandgap reference circuit, including: a current control module 10, a current mirror module 20, and a voltage output module 30; the current control module 10 is electrically connected to the current mirror module 20, and the current control module 10 is used to cooperate with the current mirror module 20 to generate a zero-temperature coefficient current; the current mirror module 20 is electrically connected to the voltage output module 30, and the current mirror module 20 is used to copy the zero-temperature coefficient current and output it to the voltage output module 30; the voltage output module 30 is used to generate and output multiple zero-temperature coefficient voltages based on the zero-temperature coefficient current; wherein, the voltage value of each zero-temperature coefficient voltage is different.

[0032] It should be noted that the current value of a zero-temperature coefficient current does not change with time, and the voltage value of a zero-temperature coefficient voltage does not change with time.

[0033] The current mirror module 20 is also used for electrical connection with the power supply, and the current control module 10 is also used for grounding. The current mirror module 20 inputs current to the current control module 10, and through the adjustment of the current control module 10, the current mirror module 20 obtains a current with zero temperature coefficient.

[0034] In this embodiment of the invention, the current control module 10 and the current mirror module 20 work together to generate a zero-temperature coefficient current. The current mirror module 20 then copies the zero-temperature coefficient current and outputs it to the voltage output module 30. The voltage output module 30 then generates and outputs multiple zero-temperature coefficient voltages based on the zero-temperature coefficient current. Since each zero-temperature coefficient voltage has a different voltage value, it can meet the requirements for multiple voltage values, thus improving the adaptability of the bandgap reference circuit to multiple voltage value requirements.

[0035] Optional, refer to Figure 2In some embodiments, the current mirror module 20 includes a first transistor group Q1, a second transistor group Q2, and a third transistor group Q3; a first terminal of the first transistor group Q1 is electrically connected to a first power supply, a second terminal of the first transistor group Q1 is electrically connected to a first terminal of the current control module 10, and a control terminal of the first transistor group Q1 is electrically connected to the control terminals of the second transistor group Q2 and the third transistor group Q3, respectively; a first terminal of the second transistor group Q2 is electrically connected to the first power supply, and a second terminal of the second transistor group Q2 is electrically connected to a second terminal of the current control module 10; a first terminal of the third transistor group Q3 is electrically connected to the first power supply, and a second terminal of the third transistor group Q3 is electrically connected to a first terminal of the voltage output module 30; a third terminal of the current control module 10 is electrically connected to the control terminals of the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3, respectively; and a second terminal of the voltage output module 30 is grounded.

[0036] Specifically, in some embodiments, the types of the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 are all the same.

[0037] In this embodiment of the invention, the first transistor group Q1 and the second transistor group Q2 form a current mirror circuit, such that the current input from the first transistor group Q1 to the current control module 10 is the same as the current input from the second transistor group Q2 to the current control module 10. Specifically, the current value input from the first transistor group Q1 to the current control module 10 is equal to the current value input from the second transistor group Q2 to the current control module 10. The second transistor group Q2 and the third transistor group Q3 form a current mirror circuit, such that the current input from the second transistor group Q2 to the current control module 10 is the same as the current input from the third transistor group Q3 to the voltage output module 30. Specifically, the current value input from the second transistor group Q2 to the current control module 10 is equal to the current value input from the third transistor group Q3 to the voltage output module 30.

[0038] Optionally, in some embodiments, the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 are all transistor groups including q MOS transistors, where q is a positive integer; in the first transistor group Q1, the first terminal of the first MOS transistor is electrically connected to the first power supply; the second terminal of the r-th MOS transistor is electrically connected to the first terminal of the (r+1)-th MOS transistor; the second terminal of the q-th MOS transistor is electrically connected to the first terminal of the current control module 10, where r is a positive integer less than q; in the second transistor group Q2, the first terminal of the first MOS transistor is electrically connected to the first power supply; the second terminal of the r-th MOS transistor is electrically connected to the first terminal of the current control module 10; and the third transistor is electrically connected to the first terminal of the current control module 10. The second terminals of the r MOS transistors are electrically connected to the first terminals of the (r+1)th MOS transistor; the second terminal of the qth MOS transistor is electrically connected to the second terminal of the current control module 10; in the third transistor group Q3, the first terminal of the first MOS transistor is electrically connected to the first power supply; the second terminal of the rth MOS transistor is electrically connected to the first terminals of the (r+1)th MOS transistor; the second terminal of the qth MOS transistor is electrically connected to the first terminal of the voltage output module 30; the control terminals of each MOS transistor are electrically connected to each other; the third terminal of the current control module 10 is electrically connected to the control terminals of each MOS transistor.

[0039] It should be noted that MOS transistor stands for Metal-Oxide-Semiconductor Field-Effect Transistor.

[0040] For example, refer to Figure 4The first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 are all transistor groups comprising seven MOSFETs, namely MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M5, MOSFET M6, and MOSFET M7. The first terminal of MOSFET M1 is the first terminal S of the transistor group comprising the seven MOSFETs. The second terminal of MOSFET M1 is electrically connected to the first terminal of MOSFET M2. The second terminal of MOSFET M2 is electrically connected to the first terminal of MOSFET M3. The second terminal of MOSFET M3 is electrically connected to the first terminal of MOSFET M4. The second terminal of MOSFET M4 is electrically connected to the first terminal of MOSFET M5. The second terminal of MOSFET M5 is electrically connected to the first terminal of MOSFET M6. Electrically connected, the second terminal of MOSFET M6 is electrically connected to the first terminal of MOSFET M7. The second terminal of MOSFET M7 is the second terminal D of the transistor group consisting of 7 MOSFETs. The control terminals of MOSFETs M1, M2, M3, M4, M5, M6, and M7 are all electrically connected to the common gate terminal G of the transistor group consisting of 7 MOSFETs. The control terminals of MOSFETs M1, M2, M3, M4, M5, M6, and M7 are all electrically connected to each other through the common gate terminal G.

[0041] It should be noted that, for the first transistor group Q1, the first terminal of the first transistor group Q1 is the first terminal S of the transistor group including 7 MOS transistors, the second terminal of the first transistor group Q1 is the second terminal D of the transistor group including 7 MOS transistors, and the control terminal of the first transistor group Q1 is the common gate terminal G of the transistor group including 7 MOS transistors; in the first transistor group Q1, the first terminal of MOS transistor M1 is used to be electrically connected to the first power supply, and the second terminal of MOS transistor M7 is electrically connected to the first terminal of the current control module 10;

[0042] For the second transistor group Q2, the first terminal of the second transistor group Q2 is the first terminal S of the transistor group including 7 MOS transistors, the second terminal of the second transistor group Q2 is the second terminal D of the transistor group including 7 MOS transistors, and the control terminal of the second transistor group Q2 is the common gate terminal G of the transistor group including 7 MOS transistors; in the second transistor group Q2, the first terminal of MOS transistor M1 is used to be electrically connected to the first power supply, and the second terminal of MOS transistor M7 is electrically connected to the second terminal of the current control module 10;

[0043] For the third transistor group Q3, the first terminal of the third transistor group Q3 is the first terminal S of the transistor group including 7 MOS transistors, the second terminal of the third transistor group Q3 is the second terminal D of the transistor group including 7 MOS transistors, and the control terminal of the third transistor group Q3 is the common gate terminal G of the transistor group including 7 MOS transistors; in the third transistor group Q3, the first terminal of MOS transistor M1 is used to be electrically connected to the first power supply, and the second terminal of MOS transistor M7 is electrically connected to the first terminal of the voltage output module 30.

[0044] In this embodiment of the invention, the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 are all composed of multiple MOS transistors. By connecting multiple MOS transistors in the first transistor group Q1 in parallel, the gate length of the first transistor group Q1 is increased compared to a single MOS transistor, thereby reducing the current of the first transistor group Q1 and lowering the power consumption of the bandgap reference circuit. Similarly, by connecting multiple MOS transistors in the second transistor group Q2 in parallel, the gate length of the second transistor group Q2 is increased compared to a single MOS transistor, thereby reducing the current of the second transistor group Q2 and lowering the power consumption of the bandgap reference circuit. Likewise, by connecting multiple MOS transistors in the third transistor group Q3 in parallel, the gate length of the third transistor group Q3 is increased compared to a single MOS transistor, thereby reducing the current of the third transistor group Q3 and lowering the power consumption of the bandgap reference circuit.

[0045] Optionally, in some embodiments, each of the MOS transistors is a PMOS transistor.

[0046] It should be noted that PMOS transistors are positive channel metal-oxide-semiconductor transistors.

[0047] In this embodiment of the invention, the first end of the MOS transistor is the source of the PMOS transistor, the second end of the MOS transistor is the drain of the PMOS transistor, and the control end of the MOS transistor is the gate of the PMOS transistor; the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 are all transistor groups including multiple PMOS transistors, such that the first transistor group Q1 and the second transistor group Q2 form a PMOS current mirror circuit, and the second transistor group Q2 and the third transistor group Q3 form a PMOS current mirror circuit.

[0048] Optionally, in some embodiments, the current control module 10 includes an operational amplifier P, a first resistor R1, a second resistor R2, a third resistor R3, a fourth transistor group Q4, and a fifth transistor group Q5; the inverting input terminal of the operational amplifier P is electrically connected to the first terminal of the third resistor R3 and the first terminal of the fourth transistor group Q4, respectively; the non-inverting input terminal of the operational amplifier P is electrically connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively; the output terminal of the operational amplifier P is electrically connected to the control terminals of the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3, respectively; the first terminal of the first resistor R1 is electrically connected to the second terminal of the second transistor group Q2. The first resistor R1 is electrically connected to the second terminal of the fifth transistor group Q5; the second resistor R2 is electrically connected to the second terminal of the second transistor group Q2, and the second terminal of the second resistor R2 is grounded; the third resistor R3 is electrically connected to the second terminal of the first transistor group Q1, and the second terminal of the third resistor R3 is grounded; the first terminal of the fourth transistor group Q4 is electrically connected to the second terminal of the first transistor group Q1, the control terminal of the fourth transistor group Q4 is electrically connected to the second terminal of the fourth transistor group Q4, and the second terminal of the fourth transistor group Q4 is grounded; the control terminal of the fifth transistor group Q5 is electrically connected to the second terminal of the fifth transistor group Q5, and the second terminal of the fifth transistor group Q5 is grounded.

[0049] In this embodiment of the invention, the operational amplifier P, the first resistor R1, the second resistor R2, the third resistor R3, the fourth transistor group Q4, and the fifth transistor group Q5 work together to make the current passing through the second transistor group Q2 a current with zero temperature coefficient.

[0050] Optionally, in some embodiments, the fourth transistor group Q4 includes n first transistors, and the fifth transistor group Q5 includes m second transistors, where n is a positive integer greater than 1, m is a positive integer greater than or equal to 1, and the ratio of n to m is a positive integer greater than 1; in the fourth transistor group Q4, the first terminal of the first first transistor is electrically connected to the second terminal of the first transistor group Q1; the second terminal of the ith first transistor is electrically connected to the first terminal of the (i+1)th first transistor; the second terminal of the nth first transistor is... The first terminal of the first transistor is electrically connected to the control terminal of each of the first transistors, and the second terminal of the nth first transistor is grounded, where i is a positive integer less than n; in the fifth transistor group Q5, the first terminal of the first second transistor is electrically connected to the second terminal of the first resistor R1; the second terminal of the jth second transistor is electrically connected to the first terminal of the (j+1)th second transistor; the second terminal of the mth second transistor is electrically connected to the control terminal of each of the second transistors, and the second terminal of the mth second transistor is grounded, where j is a positive integer less than m.

[0051] It should be noted that the ratio of n to m is the ratio obtained by dividing m by n.

[0052] For example, the fourth transistor group Q4 includes six first transistors, and the fifth transistor group Q5 includes two second transistors. In the fourth transistor group Q4, the first terminal of the first first transistor is electrically connected to the second terminal of the first transistor group Q1; the second terminal of the first first transistor is electrically connected to the first terminal of the second first transistor, the second terminal of the second first transistor is electrically connected to the first terminal of the third first transistor, the second terminal of the third first transistor is electrically connected to the first terminal of the fourth first transistor, the second terminal of the fourth first transistor is electrically connected to the first terminal of the fifth first transistor, and the second terminal of the fifth first transistor is electrically connected to the first terminal of the sixth first transistor; the second terminal of the sixth first transistor is electrically connected to the control terminal of each first transistor, and the second terminal of the sixth first transistor is grounded.

[0053] In the fifth transistor group Q5, the first terminal of the first second transistor is electrically connected to the second terminal of the first resistor R1; the second terminal of the first second transistor is electrically connected to the first terminal of the second second transistor; the second terminal of the second second transistor is electrically connected to the control terminal of each second transistor respectively, and the second terminal of the second second transistor is grounded.

[0054] For example, the fourth transistor group Q4 includes three first transistors, and the fifth transistor group Q5 includes one second transistor. In the fourth transistor group Q4, the first terminal of the first first transistor is electrically connected to the second terminal of the first transistor group Q1; the second terminal of the first first transistor is electrically connected to the first terminal of the second first transistor, and the second terminal of the second first transistor is electrically connected to the first terminal of the third first transistor; the second terminal of the third first transistor is electrically connected to the control terminal of each first transistor, and the second terminal of the third first transistor is grounded. In the fifth transistor group Q5, the first terminal of the second transistor is electrically connected to the second terminal of the first resistor R1, the second terminal of the second transistor is electrically connected to the control terminal of the second transistor, and the second terminal of the second transistor is grounded.

[0055] In this embodiment of the present invention, since the fourth transistor group Q4 includes n first transistors, the first terminal of the first first transistor in the fourth transistor group Q4 is electrically connected to the second terminal of the first transistor group Q1, the second terminal of the i-th first transistor is electrically connected to the first terminal of the (i+1)-th first transistor, the second terminal of the n-th first transistor is electrically connected to the control terminal of each first transistor, and the second terminal of the n-th first transistor is grounded, so that the control terminal of the fourth transistor group Q4 is electrically connected to the second terminal of the fourth transistor group Q4. Therefore, the fourth transistor group Q4 is equivalent to a diode device.

[0056] Since the fifth transistor group Q5 includes m second transistors, in the fifth transistor group Q5, the first terminal of the first second transistor is electrically connected to the second terminal of the first resistor R1; the second terminal of the j-th second transistor is electrically connected to the first terminal of the (j+1)-th second transistor; the second terminal of the m-th second transistor is electrically connected to the control terminal of each second transistor, and the second terminal of the m-th second transistor is grounded, so that the control terminal of the fifth transistor group Q5 is electrically connected to the second terminal of the fifth transistor group Q5. Therefore, the fifth transistor group Q5 is equivalent to a diode device.

[0057] Since the fourth transistor group Q4 includes n first transistors and the fifth transistor group Q5 includes m second transistors, and the ratio of n to m is a positive integer greater than 1, the ratio of the emitter area of ​​the fourth transistor group Q4 to the emitter area of ​​the fifth transistor group Q5 is also a positive integer greater than 1. This ensures that the voltage difference between the fourth transistor group Q4 and the fifth transistor group Q5 is equal to U. T One of the conditions for lnN is that N is the ratio of n to m, i.e., N = n / m, U T Let the thermal voltage be the expression for the thermal voltage:

[0058]

[0059] Where T is the absolute temperature, K is the Boltzmann constant, and Q is the electron charge.

[0060] Optionally, in some embodiments, the first transistor may be a PNP transistor or an NPN transistor, and the second transistor may be a PNP transistor or an NPN transistor; the types of each first transistor and each second transistor are the same.

[0061] It should be noted that an NPN transistor consists of three semiconductors: two N (Negative Electricity) semiconductors (electron semiconductors) and one P (Positive Electricity) semiconductor (hole semiconductor), with the P-type semiconductor in the middle and the two N-type semiconductors on either side; a PNP transistor consists of three semiconductors: one N-type semiconductor and two P-type semiconductors, with the N-type semiconductor in the middle and the two P-type semiconductors on either side.

[0062] When the first transistor is a PNP transistor, the first terminal of the first transistor is the emitter, the second terminal is the collector, and the control terminal is the base. When the first transistor is an NPN transistor, the first terminal is the collector, the second terminal is the emitter, and the control terminal is the base.

[0063] When the second transistor is a PNP type transistor, the first terminal of the transistor is the emitter, the second terminal is the collector, and the control terminal is the base. When the second transistor is an NPN type transistor, the first terminal is the collector, the second terminal is the emitter, and the control terminal is the base.

[0064] In this embodiment of the invention, since the fourth transistor group Q4 includes n first transistors and the fifth transistor group Q5 includes m second transistors, the ratio of n to m is a positive integer greater than 1. Since the type of each first transistor and the type of each second transistor are the same, the ratio of the emitter area of ​​the fourth transistor group Q4 to the emitter area of ​​the fifth transistor group Q5 is a positive integer greater than 1. This ensures that the voltage difference between the fourth transistor group Q4 and the fifth transistor group Q5 is equal to U. T One of the conditions for lnN.

[0065] Optionally, in some embodiments, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3.

[0066] In this embodiment of the invention, since the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3, and due to the "virtual short" effect of the operational amplifier P, the voltage value of the second resistor R2 is equal to the voltage value of the third resistor R3, and therefore the current value of the second resistor R2 is equal to the current value of the third resistor R3.

[0067] In this embodiment of the invention, due to the "virtual short" effect of operational amplifier P, the voltage value at the inverting input terminal of operational amplifier P is equal to the voltage value at the non-inverting input terminal of operational amplifier P. Therefore:

[0068] U Q4 =U R3 =U R1 +U Q5 =U R2

[0069] Among them, U Q4 U is the voltage value of the fourth transistor group Q4. R3 U is the voltage value of the third resistor R3. R1 U is the voltage value across the first resistor R1. Q5 U is the voltage value of the fifth transistor group Q5. R2 The voltage value of the second resistor R2 is equal to the voltage value of the fourth transistor group Q4, which is equal to the voltage value of the third resistor R3, and the voltage value of the fourth transistor group Q4 is equal to the sum of the voltage values ​​of the first resistor R1 and the voltage values ​​of the fifth transistor group Q5.

[0070] Therefore, we can conclude that:

[0071] The expression for the current value of the third resistor R3 is:

[0072]

[0073] Among them, I R3 r3 is the current value of the third resistor R3, and r3 is the resistance value of the third resistor R3. The current value of the third resistor R3 is equal to the quotient of the voltage value of the fourth transistor group Q4 divided by the resistance value of the third resistor R3.

[0074] The expression for the current value of the first resistor R1 is:

[0075]

[0076] Among them, I R1 Let r1 be the current value of the first resistor R1, r1 be the resistance value of the first resistor R1, the voltage value of the first resistor R1 be equal to the voltage difference between the fourth transistor group Q4 and the fifth transistor group Q5, and the current value of the first resistor R1 be equal to the quotient of the voltage difference between the fourth transistor group Q4 and the fifth transistor group Q5 divided by the resistance value of the first resistor R1.

[0077] Because the resistance value of the second resistor R2 is the same as the resistance value of the third resistor R3, and U R3 =U R2 Then I R2 =I R3 , where I R2 Let R2 be the current value of the second resistor. Then, the expression for the current value through the second transistor group Q2 is:

[0078]

[0079] Among them, I Q2 This represents the current value of the second transistor group Q2.

[0080] Since each first transistor in the fourth transistor group Q4 is of the same type as each second transistor in the fifth transistor group Q5, the saturation current value of each first transistor and the saturation current value of each second transistor are equal; since the first transistor group Q1 and the second transistor group Q2 form a current mirror circuit, then I Q1 =I Q2 , where I Q1 This represents the current value of the first transistor group Q1.

[0081] And I R2 =I R3 Therefore, the expression for the voltage difference between the fourth transistor group Q4 and the fifth transistor group Q5 can be obtained as follows:

[0082]

[0083] Among them, I Q4 I represents the current value of the fourth transistor group Q4. Q5 Let I be the current value of the fifth transistor group Q5, and let I be the saturation current value of each first transistor and each second transistor. S .

[0084] but:

[0085]

[0086] and then:

[0087]

[0088] Explain the current value I of the first resistor R1. R1 The current in the first resistor R1 is positively correlated with temperature and has a positive temperature coefficient.

[0089] Since the fourth transistor group Q4 is equivalent to a diode device, then:

[0090]

[0091] Among them, U be M represents the voltage difference between the control terminal and the second terminal of the fourth transistor group Q4, where M is 1.5 and E is... g This refers to the band gap of semiconductor materials (typically, the band gap of silicon is 1.12 eV). Under normal circumstances:

[0092]

[0093] For example, at room temperature (T = 300K), U be If the voltage is 750mV, then:

[0094]

[0095] but:

[0096]

[0097] Explain the current value I of the second resistor R2. R2 The current in the second resistor R2 is negatively correlated with temperature, and has a negative temperature coefficient.

[0098] and:

[0099]

[0100] By setting N (the ratio of the number of first transistors in the fourth transistor group Q4 to the number of second transistors in the fifth transistor group Q5), it is possible to:

[0101]

[0102] Even if the current value of the second transistor group Q2 does not change with temperature, the current value of the second transistor group Q2 is the current value with zero temperature coefficient.

[0103] The present invention enables the superposition of a current with a positive temperature coefficient (i.e., the current of the first resistor R1) and a current with a negative temperature coefficient (i.e., the current of the second resistor R2) to obtain a current with a zero temperature coefficient (i.e., the current of the second transistor group Q2).

[0104] Since the second transistor group Q2 and the third transistor group Q3 form a current mirror circuit, the current value input by the second transistor group Q2 to the current control module 10 (i.e., the current value of the second transistor group Q2) is equal to the current value input by the third transistor group Q3 to the voltage output module 30. Therefore, the current value input by the third transistor group Q3 to the voltage output module 30 is a current value with zero temperature coefficient.

[0105] Optionally, in some embodiments, the voltage output module 30 includes p fourth resistors R4, where p is a positive integer; the voltage output module 30 also includes p voltage output terminals 31, each fourth resistor R4 having a corresponding voltage output terminal 31; the first terminal of the first fourth resistor R4 is electrically connected to the second terminal of the third transistor group Q3; the first terminal of the kth fourth resistor R4 is electrically connected to the voltage output terminal 31 corresponding to the kth fourth resistor R4, and the second terminal of the kth fourth resistor R4 is electrically connected to the first terminal of the (k+1)th fourth resistor R4; the second terminal of the pth fourth resistor R4 is grounded, where k is a positive integer less than p.

[0106] For example, refer to Figure 2 The voltage output module 30 includes two fourth resistors R4 and two voltage output terminals 31. The first terminal of the first fourth resistor R4 is electrically connected to the second terminal of the third transistor group Q3. The first terminal of the first fourth resistor R4 is electrically connected to the voltage output terminal 31 corresponding to the first fourth resistor R4. The first terminal of the second fourth resistor R4 is electrically connected to the voltage output terminal 31 corresponding to the second fourth resistor R4. The second terminal of the first fourth resistor R4 is electrically connected to the first terminal of the second fourth resistor R4. The second terminal of the second fourth resistor R4 is grounded. The zero-temperature coefficient voltage value output by the voltage output terminal 31 corresponding to the first fourth resistor R4 is equal to the zero-temperature coefficient current value multiplied by the sum of the resistance values ​​of the two fourth resistors R4. The zero-temperature coefficient voltage value output by the voltage output terminal 31 corresponding to the second fourth resistor R4 is equal to the zero-temperature coefficient current value multiplied by the resistance value of the second fourth resistor R4.

[0107] In this embodiment of the present invention, since the voltage output module 30 is connected in series with multiple fourth resistors R4, the current value with zero temperature coefficient input from the third transistor group Q3 to the voltage output module 30 is converted into multiple voltage values ​​with zero temperature coefficient through the multiple fourth resistors R4. The voltage values ​​with zero temperature coefficient are output through the voltage output terminal 31 of the voltage output module 30, and the zero temperature coefficient voltage values ​​output by each voltage output terminal 31 are different.

[0108] In this embodiment of the invention, the expression for the zero-temperature coefficient voltage value output by the voltage output terminal 31 corresponding to the second fourth resistor R4 is:

[0109]

[0110] Among them, U OUT I is the zero-temperature coefficient voltage value output from the voltage output terminal 31 corresponding to the second fourth resistor R4. R4 r1 is the current value of the fourth resistor R4, r2 is the resistance value of the fourth resistor R4, and r2 is the resistance value of the second resistor R2.

[0111] The output voltage of the bandgap reference circuit in the related technology is 1.25 volts, while the input voltage (power supply voltage) is greater than 1.25 volts. Therefore, the bandgap reference circuit in the related technology is not suitable for applications where the input voltage is less than or equal to 1.25 volts. The expression for the output voltage of the bandgap reference circuit in the related technology is as follows:

[0112]

[0113] Therefore, compared with related technologies, in this embodiment of the present invention, by adjusting the resistance value of the fourth resistor R4 and the resistance value of the second resistor R2, the output voltage value of the bandgap reference circuit can be made less than 1.25 volts. The bandgap reference circuit provided by this embodiment of the present invention can adapt to usage scenarios where the input voltage value is less than or equal to 1.25 volts. Therefore, the bandgap reference circuit provided by this embodiment of the present invention can be used in low-power circuits where the power supply voltage value is less than or equal to 1.25 volts.

[0114] Optional, refer to Figure 3 In some embodiments, the current mirror module 20 includes a first transistor group Q1, a second transistor group Q2, a third transistor group Q3, a sixth transistor group Q6, and a seventh transistor group Q7; a first terminal of the first transistor group Q1 is electrically connected to a first power supply, a second terminal of the first transistor group Q1 is electrically connected to the first terminal of the sixth transistor group Q6, and a control terminal of the first transistor group Q1 is electrically connected to the control terminals of the second transistor group Q2 and the third transistor group Q3, respectively; a first terminal of the second transistor group Q2 is electrically connected to the first power supply, and a second terminal of the second transistor group Q2 is electrically connected to the second terminal of the seventh transistor group Q7; a first terminal of the third transistor group Q3 is electrically connected to the first power supply, and the second terminal of the third transistor group Q6 is electrically connected to the first power supply. The second terminal of the three-transistor group Q3 is electrically connected to the first terminal of the voltage output module 30; the control terminal of the third transistor group Q3 is electrically connected to the control terminal of the second transistor group Q2; the second terminal of the sixth transistor group Q6 is electrically connected to the first terminal of the current control module 10, and the control terminal of the sixth transistor group Q6 is used to be electrically connected to the second power supply; the second terminal of the seventh transistor group Q7 is electrically connected to the second terminal of the current control module 10, and the control terminal of the seventh transistor group Q7 is used to be electrically connected to the second power supply; the third terminal of the current control module 10 is electrically connected to the control terminals of the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 respectively; the second terminal of the voltage output module 30 is grounded.

[0115] Specifically, in some embodiments, the second terminal of the sixth transistor group Q6 is electrically connected to the first terminal of the third resistor R3 and the first terminal of the fourth transistor group Q4, respectively, and the second terminal of the seventh transistor group Q7 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2, respectively.

[0116] Specifically, in some embodiments, the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 are all transistor groups including multiple MOS transistors; the sixth transistor group Q6 and the seventh transistor group Q7 are both transistor groups including one PMOS transistor. The first terminal of the sixth transistor group Q6 is the source of the PMOS transistor, the second terminal of the sixth transistor group Q6 is the drain of the PMOS transistor, and the control terminal of the sixth transistor group Q6 is the gate of the PMOS transistor. The first terminal of the seventh transistor group Q7 is the source of the PMOS transistor, the second terminal of the seventh transistor group Q7 is the drain of the PMOS transistor, and the control terminal of the seventh transistor group Q7 is the gate of the PMOS transistor.

[0117] In this embodiment of the present invention, compared with the embodiment in which the current mirror module 20 includes a first transistor group Q1, a second transistor group Q2, and a third transistor group Q3, in the embodiment in which the current mirror module 20 includes a first transistor group Q1, a second transistor group Q2, a third transistor group Q3, a sixth transistor group Q6, and a seventh transistor group Q7, the sixth transistor group Q6 increases the gate length of one path of the first transistor group Q1 to reduce the current of the first transistor group Q1 and reduce the power consumption of the bandgap reference circuit. The seventh transistor group Q7 increases the gate length of one path of the second transistor group Q2 to reduce the current of the second transistor group Q2 and reduce the power consumption of the bandgap reference circuit.

[0118] Compared to current mirror circuits composed of a single large-gate transistor group, the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3 that make up the current mirror circuit are all transistor groups including multiple small-gate MOSFETs to meet the 12nm process. By adjusting the number of MOSFETs in the first transistor group Q1, the second transistor group Q2, and the third transistor group Q3, the magnitude of the zero-temperature coefficient current can be adjusted. The first transistor group Q1, the second transistor group Q2, the third transistor group Q3, the fourth transistor group Q4, the fifth transistor group Q5, the sixth transistor group Q6, and the seventh transistor group Q7 all operate in the subthreshold region, making the zero-temperature coefficient current in the nanoampere range. Compared with related technologies, this reduces the zero-temperature coefficient current, lowers the power consumption of the bandgap reference circuit, and allows the zero-temperature coefficient voltage value to be lower than 1.25 volts in related technologies.

[0119] Therefore, in this embodiment of the invention, the fourth transistor group Q4 and the fifth transistor group Q5 operate in the subthreshold region, the zero temperature coefficient current is controlled in the nanoampere level, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are all in the megaohm level, the first transistor group Q1, the second transistor group Q2 and the third transistor group Q3 all reduce the aspect ratio by connecting MOSFETs in parallel, and by adjusting the number of MOSFETs in the first transistor group Q1, the second transistor group Q2 and the third transistor group Q3, the magnitude of the zero temperature coefficient current can be adjusted, thereby achieving low power consumption.

[0120] This utility model embodiment also provides a chip, including the bandgap reference circuit as described above.

[0121] The implementation of the bandgap reference circuit in the chip is similar to that described above, and will not be repeated here. This chip includes a processor or microprocessor.

[0122] This utility model embodiment also provides an electronic device, including the bandgap reference circuit as described above, or the chip as described above.

[0123] The implementation of bandgap reference circuits in electronic devices is similar to that of the aforementioned bandgap reference circuits, and will not be repeated here.

[0124] In summary, in this embodiment of the present invention, the current control module 10 and the current mirror module 20 cooperate to generate a zero-temperature coefficient current. The current mirror module 20 then copies the zero-temperature coefficient current and outputs it to the voltage output module 30. The voltage output module 30 then generates and outputs multiple zero-temperature coefficient voltages based on the zero-temperature coefficient current. Since each zero-temperature coefficient voltage has a different voltage value, it can meet the requirements for multiple voltage values, thereby improving the adaptability of the bandgap reference circuit to various voltage value requirements.

[0125] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0127] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A bandgap reference circuit, characterized in that, include: The current control module (10), the current mirror module (20), and the voltage output module (30) are included. The current control module (10) is electrically connected to the current mirror module (20). The current control module (10) is used to cooperate with the current mirror module (20) to generate a current with zero temperature coefficient. The current mirror module (20) is electrically connected to the voltage output module (30), and the current mirror module (20) is used to copy the zero temperature coefficient current and output it to the voltage output module (30); The voltage output module (30) is used to generate and output multiple zero-temperature coefficient voltages based on the zero-temperature coefficient current. The voltage value of each of the zero temperature coefficient voltages is different.

2. The bandgap reference circuit according to claim 1, characterized in that, The current mirror module (20) includes a first transistor group (Q1), a second transistor group (Q2), and a third transistor group (Q3); The first terminal of the first transistor group (Q1) is used to be electrically connected to the first power supply, the second terminal of the first transistor group (Q1) is electrically connected to the first terminal of the current control module (10), and the control terminal of the first transistor group (Q1) is electrically connected to the control terminal of the second transistor group (Q2) and the control terminal of the third transistor group (Q3), respectively. The first terminal of the second transistor group (Q2) is electrically connected to the first power supply, and the second terminal of the second transistor group (Q2) is electrically connected to the second terminal of the current control module (10). The first terminal of the third transistor group (Q3) is electrically connected to the first power supply, the second terminal of the third transistor group (Q3) is electrically connected to the first terminal of the voltage output module (30), and the control terminal of the third transistor group (Q3) is electrically connected to the control terminal of the second transistor group (Q2). The third terminal of the current control module (10) is electrically connected to the control terminal of the first transistor group (Q1), the control terminal of the second transistor group (Q2), and the control terminal of the third transistor group (Q3); the second terminal of the voltage output module (30) is grounded.

3. The bandgap reference circuit according to claim 2, characterized in that, The current control module (10) includes an operational amplifier (P), a first resistor (R1), a second resistor, a third resistor (R3), a fourth transistor group (Q4), and a fifth transistor group (Q5); The inverting input terminal of the operational amplifier (P) is electrically connected to the first terminal of the third resistor (R3) and the first terminal of the fourth transistor group (Q4), respectively. The non-inverting input terminal of the operational amplifier (P) is electrically connected to the first terminal of the first resistor (R1) and the first terminal of the second resistor, respectively. The output terminal of the operational amplifier (P) is electrically connected to the control terminal of the first transistor group (Q1), the control terminal of the second transistor group (Q2), and the control terminal of the third transistor group (Q3), respectively. The first terminal of the first resistor (R1) is electrically connected to the second terminal of the second transistor group (Q2), and the second terminal of the first resistor (R1) is electrically connected to the first terminal of the fifth transistor group (Q5). The first terminal of the second resistor is electrically connected to the second terminal of the second transistor group (Q2), and the second terminal of the second resistor is grounded; The first terminal of the third resistor (R3) is electrically connected to the second terminal of the first transistor group (Q1), and the second terminal of the third resistor (R3) is grounded; The first terminal of the fourth transistor group (Q4) is electrically connected to the second terminal of the first transistor group (Q1), the control terminal of the fourth transistor group (Q4) is electrically connected to the second terminal of the fourth transistor group (Q4), and the second terminal of the fourth transistor group (Q4) is grounded. The control terminal of the fifth transistor group (Q5) is electrically connected to the second terminal of the fifth transistor group (Q5), and the second terminal of the fifth transistor group (Q5) is grounded.

4. The bandgap reference circuit according to claim 3, characterized in that, The fourth transistor group (Q4) includes n first transistors, and the fifth transistor group (Q5) includes m second transistors, where n is a positive integer greater than 1, m is a positive integer greater than or equal to 1, and the ratio of n to m is a positive integer greater than 1. In the fourth transistor group (Q4), the first terminal of the first transistor is electrically connected to the second terminal of the first transistor group (Q1); the second terminal of the i-th transistor is electrically connected to the first terminal of the (i+1)-th transistor; the second terminal of the n-th transistor is electrically connected to the control terminal of each transistor; and the second terminal of the n-th transistor is grounded, where i is a positive integer less than n. In the fifth transistor group (Q5), the first terminal of the first second transistor is electrically connected to the second terminal of the first resistor (R1); the second terminal of the j-th second transistor is electrically connected to the first terminal of the (j+1)-th second transistor; the second terminal of the m-th second transistor is electrically connected to the control terminal of each second transistor, and the second terminal of the m-th second transistor is grounded, where j is a positive integer less than m.

5. The bandgap reference circuit according to claim 4, characterized in that, The first transistor can be either a PNP transistor or an NPN transistor, and the second transistor can be either a PNP transistor or an NPN transistor. The first transistor and the second transistor are of the same type.

6. The bandgap reference circuit according to claim 3, characterized in that, The resistance value of the second resistor is equal to the resistance value of the third resistor (R3).

7. The bandgap reference circuit according to claim 2, characterized in that, The voltage output module (30) includes p fourth resistors (R4), where p is a positive integer; the voltage output module (30) also includes p voltage output terminals (31), each fourth resistor (R4) having a corresponding voltage output terminal (31); The first terminal of the first fourth resistor (R4) is electrically connected to the second terminal of the third transistor group (Q3); the first terminal of the kth fourth resistor (R4) is electrically connected to the voltage output terminal (31) corresponding to the kth fourth resistor (R4); the second terminal of the kth fourth resistor (R4) is electrically connected to the first terminal of the (k+1)th fourth resistor (R4); the second terminal of the pth fourth resistor (R4) is grounded, where k is a positive integer less than p.

8. The bandgap reference circuit according to claim 2, characterized in that, The first transistor group (Q1), the second transistor group (Q2), and the third transistor group (Q3) are all transistor groups comprising q MOS transistors, where q is a positive integer; In the first transistor group (Q1), the first terminal of the first MOS transistor is electrically connected to the first power supply; the second terminal of the r-th MOS transistor is electrically connected to the first terminal of the (r+1)-th MOS transistor; the second terminal of the q-th MOS transistor is electrically connected to the first terminal of the current control module (10), where r is a positive integer less than q; In the second transistor group (Q2), the first terminal of the first MOS transistor is electrically connected to the first power supply; the second terminal of the r-th MOS transistor is electrically connected to the first terminal of the (r+1)-th MOS transistor; and the second terminal of the q-th MOS transistor is electrically connected to the second terminal of the current control module (10). In the third transistor group (Q3), the first terminal of the first MOS transistor is electrically connected to the first power supply; the second terminal of the r-th MOS transistor is electrically connected to the first terminal of the (r+1)-th MOS transistor; and the second terminal of the q-th MOS transistor is electrically connected to the first terminal of the voltage output module (30). The control terminals of each of the MOS transistors are electrically connected to each other; the third terminal of the current control module (10) is electrically connected to the control terminal of each of the MOS transistors.

9. The bandgap reference circuit according to claim 8, characterized in that, Each of the aforementioned MOS transistors is a PMOS transistor.

10. The bandgap reference circuit according to any one of claims 1 to 9, characterized in that, The current mirror module (20) includes a first transistor group (Q1), a second transistor group (Q2), a third transistor group (Q3), a sixth transistor group (Q6), and a seventh transistor group (Q7); The first terminal of the first transistor group (Q1) is electrically connected to the first power supply, the second terminal of the first transistor group (Q1) is electrically connected to the first terminal of the sixth transistor group (Q6), and the control terminal of the first transistor group (Q1) is electrically connected to the control terminal of the second transistor group (Q2) and the control terminal of the third transistor group (Q3), respectively. The first terminal of the second transistor group (Q2) is electrically connected to the first power supply, and the second terminal of the second transistor group (Q2) is electrically connected to the second terminal of the seventh transistor group (Q7). The first terminal of the third transistor group (Q3) is electrically connected to the first power supply, the second terminal of the third transistor group (Q3) is electrically connected to the first terminal of the voltage output module (30), and the control terminal of the third transistor group (Q3) is electrically connected to the control terminal of the second transistor group (Q2). The second terminal of the sixth transistor group (Q6) is electrically connected to the first terminal of the current control module (10), and the control terminal of the sixth transistor group (Q6) is used to be electrically connected to the second power supply. The second terminal of the seventh transistor group (Q7) is electrically connected to the second terminal of the current control module (10), and the control terminal of the seventh transistor group (Q7) is used to be electrically connected to the second power supply; The third terminal of the current control module (10) is electrically connected to the control terminal of the first transistor group (Q1), the control terminal of the second transistor group (Q2), and the control terminal of the third transistor group (Q3); the second terminal of the voltage output module (30) is grounded.

11. A chip, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1 to 10.

12. An electronic device, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1 to 10, or the chip as described in claim 11.

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