Inner electrode pattern of chip multilayer ceramic capacitor

Abstract

The utility model discloses an inner electrode pattern of a chip multilayer ceramic capacitor. Wherein the inner electrode pattern of the chip multilayer ceramic capacitor comprises four sub-regions taking a horizontal axis and a vertical axis of a plane where the center of the inner electrode pattern is located as boundaries; each sub-region comprises an effective electrode region and an edge electrode region; the edge electrode region is arranged around the effective electrode region; the edge electrode area comprises a plurality of edge electrode patterns; the effective electrode region is a grid formed by a plurality of rectangular patterns with the same shape; the horizontal length difference values of the left side edge electrode patterns and the right side edge electrode patterns of any two sub-regions which are centrosymmetric by taking the dead center as a symmetric point are the same; the horizontal length and the vertical length of the upper side edge electrode pattern and the lower side edge electrode pattern of any two sub-regions which are axisymmetric about the horizontal axis are the same. The utility model can be widely applied to the technical field of electronic components.

Description

Technical Field

[0001] This application relates to the field of electronic components technology, and in particular to an internal electrode pattern for a chip multilayer ceramic capacitor. Background Technology

[0002] Multilayer ceramic capacitors (MLCCs) are among the most commonly used electronic components and are widely used in home appliances, mobile phones, computers and other intelligent control circuits. Generally speaking, the capacitance of an MLCC is closely related to the number of layers and the printed internal electrodes. The higher the number of layers and the thinner the printed internal electrodes, the more miniaturized and high-capacitance MLCC products can be manufactured. Based on this, higher requirements are placed on the quality of the layer stack.

[0003] In existing lamination processes, a ceramic sheet is first prepared, and internal electrodes are then printed onto the ceramic sheet using a screen printing machine to obtain a printed sheet. These printed sheets are then misaligned by horizontal or vertical translation before being laminated to obtain a complete laminated block. However, due to the structural limitations of the printing screen, this method results in poor overall lamination quality of the printed sheets, making it particularly unsuitable for the preparation of thin, high-capacity products. It also easily leads to edge damage of the printed sheet, resulting in low utilization of the printed sheets and a reduced number of qualified products. Therefore, there are still technical problems that need to be solved in this field. Utility Model Content

[0004] The purpose of this application is to at least partially solve one of the technical problems existing in the prior art.

[0005] Therefore, one objective of this application is to provide an internal electrode pattern for a multilayer ceramic chip capacitor, which can improve the utilization efficiency of the printed circuit board and increase the product qualification rate.

[0006] To achieve the above-mentioned technical objectives, the technical solution adopted in this application includes: an internal electrode pattern for a chip multilayer ceramic capacitor, comprising four sub-regions with the horizontal axis and vertical axis of the plane containing the center of the internal electrode pattern as dividing lines; each sub-region includes an effective electrode area and an edge electrode area; the edge electrode area is arranged around the effective electrode area; the edge electrode area includes a plurality of edge electrode patterns; the effective electrode area is a grid formed by a plurality of rectangular patterns of the same shape; the difference in horizontal length between the left and right edge electrode patterns of any two sub-regions that are centrally symmetrical about the center is the same; the horizontal length and vertical length of the upper and lower edge electrode patterns of any two sub-regions that are axially symmetrical about the horizontal axis are the same.

[0007] In addition, the internal electrode pattern of a chip multilayer ceramic capacitor according to the above embodiments of this utility model may also have the following additional technical features:

[0008] Furthermore, in this embodiment of the application, the inner electrode pattern further includes an inner identification site; the inner identification site is disposed on the vertical axis, and the inner identification site is disposed on the outer edge of the edge electrode area that is far from the center and parallel to the horizontal axis.

[0009] Furthermore, in this embodiment of the application, the number of internal identification sites is two.

[0010] Furthermore, in this embodiment of the application, the inner electrode pattern further includes two outer identification sites; the outer identification sites are located outside the sub-region; one of the outer identification sites is disposed outside the edge electrode area of ​​any one of the sub-regions, and the other outer identification site is disposed outside the edge electrode area of ​​the sub-region that is centrally symmetrical with respect to the center of any one of the sub-regions, and the two outer identification sites are centrally symmetrical with respect to the center.

[0011] Furthermore, in this embodiment of the application, each column of the rectangular patterns within the grid is arranged in parallel.

[0012] Furthermore, in this embodiment of the application, the rectangular patterns in each column of the grid are arranged in an alternating pattern.

[0013] Further, in this embodiment, the first region includes two sub-regions that are symmetrically arranged along a vertical axis and connected to each other; each of the first regions includes two first horizontal edge electrodes arranged parallel to the horizontal axis; each of the first horizontal edge electrodes includes two sub-horizontal edge electrodes; each of the sub-horizontal edge electrodes includes a left edge electrode, a first middle edge electrode of the same shape, and a right edge electrode arranged horizontally in sequence; wherein the difference in horizontal length between the right edge electrode and the left edge electrode of any one sub-horizontal edge electrode is equal to the difference in horizontal length between the left edge electrode and the right edge electrode of the other sub-horizontal edge electrode.

[0014] Further, in this embodiment, the second region includes two sub-regions that are symmetrically arranged along a horizontal axis and connected to each other; each of the second regions includes two first vertical edge electrodes arranged parallel to the vertical axis; each of the first vertical edge electrodes includes two sub-vertical edge electrodes; each of the sub-vertical edge electrodes includes a top edge electrode, a second middle edge electrode of the same shape, and a bottom edge electrode arranged vertically in sequence; wherein the shape of the bottom edge electrode and the top edge electrode of any one of the sub-vertical edge electrodes is the same as the shape of the bottom edge electrode and the top edge electrode of the other sub-vertical edge electrode.

[0015] Furthermore, in any two adjacent superimposed inner electrode patterns, the angle difference between the diagonal lines formed by the outer identification points of any one inner electrode pattern of the chip multilayer ceramic capacitor and the other inner electrode pattern of the chip multilayer ceramic capacitor is 180°.

[0016] The advantages and beneficial effects of this application are as follows:

[0017] Because the rectangular pattern of the effective electrode area and the edge pattern of the edge electrode area of ​​this application have equal length and width, the effective electrode area and the edge electrode area can still completely overlap with the pattern before rotation after rotating 180°, thereby improving the utilization rate of the screen printing sheet with the inner electrode pattern and increasing the effective number of qualified products obtained. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the internal electrode pattern of a chip multilayer ceramic capacitor in a specific embodiment of this utility model;

[0019] Figure 2 This is a schematic diagram showing the dimensions of a portion of the electrode pattern within a multilayer ceramic chip capacitor in a specific embodiment of this utility model.

[0020] Figure 3 This is a schematic diagram of the internal electrode stack pattern and stack cutting points of a chip multilayer ceramic capacitor in a specific embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the internal electrode stack pattern and stack cutting points of a multilayer ceramic chip capacitor in another specific embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the internal electrode stack pattern and stack cutting points of a multilayer ceramic chip capacitor in another specific embodiment of the present invention.

[0023] Figure 6This is a schematic diagram of the internal electrode stack pattern design and X-displacement stack in the prior art.

[0024] Figure 7 This is a schematic diagram of the internal electrode stack pattern design and Y-dislocation stack in the prior art. Detailed Implementation

[0025] The following detailed description, in conjunction with the accompanying drawings, illustrates the design principles and fabrication process of the internal electrode patterns in the multilayer ceramic chip capacitor of this utility model.

[0026] In existing lamination processes, ceramic film strips are first prepared by casting, and internal electrodes with internal electrode patterns are obtained by screen printing on the ceramic film strips. Then, the printed sheets with internal electrode patterns are misaligned by translation in the X or Y direction and laminated to obtain laminated blocks. However, the edges of the internal electrode patterns remain around the edges of the blocks obtained by lamination by misalignment and translation, resulting in a relatively loose lamination structure around the edges, poor uniformity of edge size and thickness, and poor overall lamination quality. This is especially unsuitable for the preparation of thin-layer, high-capacity products, and it is very easy to cause damage to the edges of the internal electrode pattern film strip, resulting in low utilization of the internal electrode pattern and a reduction in the number of qualified products.

[0027] This application provides an internal electrode pattern for a multilayer ceramic chip capacitor. (Refer to...) Figure 1 The internal electrode pattern of this chip-type multilayer ceramic capacitor may include at least four sub-regions with the horizontal axis and vertical axis of the plane where the center of the internal electrode pattern is located as the dividing lines; each sub-region includes an effective electrode area 11 and an edge electrode area 12; the edge electrode area 12 is arranged around the effective electrode area 11; the edge electrode area 12 includes a number of edge electrode patterns; the effective electrode area 11 is a grid formed by a number of rectangular patterns of the same shape; the difference in horizontal length between the left and right edge electrode patterns of any two sub-regions that are centrally symmetrical with the center as the symmetry point is the same; the difference in horizontal and vertical length between the upper and lower edge electrode patterns of any two sub-regions that are axially symmetrical with the horizontal axis is the same.

[0028] Furthermore, in some feasible embodiments of this application, the inner electrode pattern further includes an inner identification site; the inner identification site is disposed on the vertical axis, and the inner identification site is disposed on the outer edge of the edge electrode area away from the positive center and parallel to the horizontal axis.

[0029] Furthermore, in some feasible embodiments of this application, the number of internal identification sites is two.

[0030] Furthermore, in some feasible embodiments of this application, the inner electrode pattern may also include two outer identification sites; the outer identification sites are located outside the sub-region; one outer identification site is disposed outside the edge electrode area of ​​any sub-region, and the other outer identification site is disposed outside the edge electrode area of ​​a sub-region that is centrally symmetrical with respect to the center of any sub-region, and the two outer identification sites are centrally symmetrical with respect to the center.

[0031] like Figure 1 As shown, the area is divided into four regions: A, B, C, and D, with the horizontal and vertical axes at the center of the inner electrode pattern as boundaries. The effective electrode region is a rectangular pattern with the same horizontal and vertical length in the four regions. The edge electrode is a group of patterns surrounding the effective electrode. The inner identification points of the two inner electrode patterns are located at both ends of the vertical axis and are level with the upper and lower ends of the edge electrode. The outer identification points of the two inner electrode patterns are located outside the edge electrodes of regions A and B, respectively.

[0032] Furthermore, in some feasible embodiments of this application, each column of rectangular patterns within the grid is arranged in parallel.

[0033] Furthermore, in some feasible embodiments of this application, the rectangular patterns in each column of the grid are arranged in an alternating pattern.

[0034] Furthermore, in some feasible embodiments of this application, the first region may include two sub-regions that are symmetrically arranged along a vertical axis and connected to each other; any first region includes two first horizontal edge electrodes arranged parallel to the horizontal axis; wherein any first horizontal edge electrode includes two sub-horizontal edge electrodes; any sub-horizontal edge electrode includes a left edge electrode, a first middle edge electrode of the same shape, and a right edge electrode arranged horizontally in sequence; wherein the difference in horizontal length between the right edge electrode and the left edge electrode of any sub-horizontal edge electrode is equal to the difference in horizontal length between the left edge electrode and the right edge electrode of the other sub-horizontal edge electrode.

[0035] Furthermore, in some feasible embodiments of this application, the second region includes two sub-regions that are arranged symmetrically along a horizontal axis and connected to each other; any second region includes two first vertical edge electrodes arranged parallel to the vertical axis; wherein any first vertical edge electrode includes two sub-vertical edge electrodes; any sub-vertical edge electrode includes an upper edge electrode, a second middle edge electrode of the same shape, and a lower edge electrode arranged vertically in sequence; wherein the shape of the lower edge electrode and the upper edge electrode of any sub-vertical edge electrode is the same as the shape of the lower edge electrode and the upper edge electrode of the other sub-vertical edge electrode.

[0036] Furthermore, areas A and C both have the same layout design for their inner electrode printing patterns. Specifically, the shape and arrangement of each column of effective electrode areas are the same, the horizontal length of the edge electrode areas is the same, and each column is arranged in parallel. Areas B and D both have the same layout design for their inner electrode printing patterns, the horizontal length of the edge electrode areas is the same, and each column is arranged in parallel.

[0037] Furthermore, the dimensions of the edge electrode area of ​​the inner electrode pattern are referenced. Figure 2 .exist Figure 2 In the example, if the length of a single capacitor product is set to a, the horizontal length of the left edge of the sub-horizontal edge electrode of region A is b, the horizontal length of the right edge of region A is c, the horizontal length of the left edge of the sub-edge electrode of region B is d, and the horizontal length of the right edge of region B is e, then the screen design satisfies b>a, c>a, d=c+a and e=b+a.

[0038] Furthermore, the shapes of the upper and lower edge electrodes of regions A and C can be the same.

[0039] Furthermore, Figure 1 The inner electrode pattern is obtained by rotating it 180 degrees around the center. Figure 3 The internal electrode pattern structure is shown. At this point, the screen after rotating the internal electrode pattern 180 degrees around its center is sequentially divided into four regions: A', B', C', and D', and these regions are then compared with the unrotated internal electrode pattern. Figure 1 After being stacked, a stacked structure is obtained. The stacking sequence is: one layer of printed sheet with an unrotated inner electrode pattern, one layer of printed sheet with a rotated inner electrode pattern, ..., one layer of printed sheet with an unrotated inner electrode pattern, and one layer of printed sheet with a rotated inner electrode pattern. After stacking multiple layers of printed sheets, a stacked block is obtained. Then, it is cut according to the cutting points to obtain a single product.

[0040] Further, refer to Figure 4 Areas A, D, B, and C all have the same inner electrode printing pattern with the same layout design. Specifically, the shape and arrangement of each column of effective electrode areas are the same, the horizontal length of the edge electrode areas is the same, and the arrangement between each column is staggered.

[0041] Further, refer to Figure 5 In areas A and D, the shape and arrangement of each column of effective electrode areas are the same, and each column is arranged in parallel, but the horizontal length of the edge electrode areas is different. Areas B and C have the same inner electrode printing pattern with the same horizontal length of the edge electrode areas, and the columns are arranged in an alternating manner.

[0042] In summary, the printed sheet with the internal electrode screen pattern of this embodiment is rotated and then sequentially stacked to form a block. Compared with the traditional method of screen printing internal electrodes to form a printed sheet and then translating and stacking the structure, the block has a flush perimeter with no residual internal electrode pattern or film damage. The thickness is uniform and the stacked structure is tight, resulting in excellent stacking quality. Furthermore, it increases the number of products obtained from cutting and separation. The specific calculations are as follows:

[0043] Traditional internal electrode pattern design and X-direction translational misalignment stacking diagram are shown below Figure 6 As shown, with Figure 6 Based on a calculation of 7 columns × 13 rows × 4 zones, the effective number of product pieces obtained after cutting is 7 × 13 × 4 = 364 pieces. However, in this embodiment... Figure 1 The number of effective product particles is 8×13×4=416, which increases the output by 14.3% on the original basis.

[0044] Traditional internal electrode pattern design and Y-direction translational misalignment stacking diagram as shown in the figure. Figure 7 As shown, with Figure 7 Based on a calculation of 8 columns × 12 rows × 4 zones, the effective number of product pieces obtained after cutting is 8 × 12 × 4 = 384 pieces. However, in this embodiment... Figure 1 The number of effective product particles is 8×13×4=416, which increases the output by 8.3% on the original basis.

[0045] Furthermore, in the embodiments of this application, in any two adjacent superimposed inner electrode patterns, the angle difference between any inner electrode pattern of one chip multilayer ceramic capacitor and the inner electrode pattern of another chip multilayer ceramic capacitor is 180°.

[0046] It should be noted that the contents of any embodiment of the internal electrode pattern of the above-described multilayer ceramic chip capacitor are applicable to the field of electronic components. The specific functions implemented in any of the electronic components are the same as those of the above-described embodiment of the internal electrode pattern of the multilayer ceramic chip capacitor, and the beneficial effects achieved are also the same as those achieved by the above-described embodiment of the internal electrode pattern of the multilayer ceramic chip capacitor.

[0047] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the term "switching" should be interpreted broadly, for example, it can mean transformation or conversion; for those skilled in the art, the specific meaning of the above term in this utility model can be understood according to the specific circumstances.

[0048] In this specification, the description of referenced terms refers to a specific structure or feature described in connection with an embodiment or example that is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0049] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

[0050] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. An internal electrode pattern for a multilayer ceramic chip capacitor, characterized in that, It includes four sub-regions with the horizontal axis and the vertical axis of the plane containing the center of the inner electrode pattern as the dividing lines; Each sub-region includes an effective electrode area and an edge electrode area; the edge electrode area is arranged around the effective electrode area; the edge electrode area includes a plurality of edge electrode patterns; the effective electrode area is a grid formed by a plurality of rectangular patterns of the same shape; the horizontal length difference between the left and right edge electrode patterns of any two sub-regions that are centrally symmetrical about the center is the same; the horizontal and vertical lengths of the upper and lower edge electrode patterns of any two sub-regions that are axially symmetrical about the horizontal axis are the same.

2. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 1, characterized in that, The inner electrode pattern further includes an inner identification site; the inner identification site is disposed on the vertical axis, and the inner identification site is disposed on the outer edge of the edge electrode area that is away from the center and parallel to the horizontal axis.

3. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 2, characterized in that, The number of internal identification sites is 2.

4. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 1, characterized in that, The inner electrode pattern also includes two outer identification sites; the outer identification sites are located outside the sub-region; one of the outer identification sites is located outside the edge electrode area of ​​any one of the sub-regions, and the other outer identification site is located outside the edge electrode area of ​​the sub-region that is symmetrical to the center of any one of the sub-regions, and the two outer identification sites are centrally symmetrical about the center.

5. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 1, characterized in that, The rectangular patterns in each column of the grid are arranged in parallel.

6. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 1, characterized in that, The rectangular patterns in each column of the grid are arranged in an alternating pattern.

7. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 1, characterized in that, The first region includes two sub-regions that are symmetrically arranged along a vertical axis and connected to each other; each of the first regions includes two first horizontal edge electrodes arranged parallel to a horizontal axis; each of the first horizontal edge electrodes includes two sub-horizontal edge electrodes; each of the sub-horizontal edge electrodes includes a left edge electrode, a first middle edge electrode of the same shape, and a right edge electrode arranged horizontally in sequence; the difference in horizontal length between the right edge electrode and the left edge electrode of any one of the sub-horizontal edge electrodes is equal to the difference in horizontal length between the left edge electrode and the right edge electrode of the other sub-horizontal edge electrode.

8. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 1, characterized in that, The second region includes two sub-regions that are symmetrically arranged along a horizontal axis and connected to each other; each of the second regions includes two first vertical edge electrodes arranged parallel to the vertical axis; each of the first vertical edge electrodes includes two sub-vertical edge electrodes; each of the sub-vertical edge electrodes includes an upper edge electrode, a second middle edge electrode of the same shape, and a lower edge electrode arranged vertically in sequence; the shape of the lower edge electrode and the upper edge electrode of any one of the sub-vertical edge electrodes is the same as the shape of the lower edge electrode and the upper edge electrode of the other sub-vertical edge electrode.

9. The internal electrode pattern of the multilayer ceramic chip capacitor according to claim 1, characterized in that, In any two adjacent superimposed inner electrode patterns, the angle difference between the diagonal lines formed by the outer identification points of any one inner electrode pattern of the chip multilayer ceramic capacitor and the other inner electrode pattern of the chip multilayer ceramic capacitor is 180°.

Images