Bus-based address automatic allocation and heartbeat monitoring low-voltage energy storage battery

Abstract

The utility model relates to the technical field of bus address automatic distribution and heartbeat monitoring low-voltage energy storage batteries, in particular to a bus-based address automatic distribution and heartbeat monitoring low-voltage energy storage battery first control loop, which comprises a battery host and N battery slaves, and N is a positive integer smaller than or equal to 31. The positive electrode of the battery host is electrically connected with the positive electrode of the first battery slave, the positive electrodes of the N battery slaves are sequentially connected, the negative electrode of the battery host is electrically connected with the negative electrode of the first battery slave, and the negative electrodes of the N battery slaves are sequentially connected; in the parallel use process, after any battery is out of fault, the remaining battery packs can still operate efficiently, after the fault battery is repaired or replaced, the battery packs can still operate normally and efficiently after being incorporated into the system, the fault-free time of overall operation of the parallel battery packs is greatly prolonged, and the fault of any battery is out of fault, so that the service life of the battery packs is prolonged. And normal operation of other battery packs is not influenced.

Description

Technical Field

[0001] This utility model relates to the field of low-voltage energy storage battery technology with automatic address allocation and heartbeat monitoring based on a bus, and in particular to a low-voltage energy storage battery with automatic address allocation and heartbeat monitoring based on a bus. Background Technology

[0002] Currently, in low-voltage residential energy storage parallel systems, a master-slave operation mode needs to be set up. Each battery needs to be set up using a DIP switch or software. In the parallel battery pack, the operating status of each battery is collected by the master through communication and the data is uploaded to the inverter or EMS system.

[0003] In a parallel battery system, power output cables are typically connected in parallel for power output; signal cables are connected in series to automatically assign addresses and maintain heartbeat signals. During normal operation, battery A starts and outputs a DO signal to battery B; upon receiving the DI signal, battery B completes startup, automatically acquires its address, and outputs a signal to battery C, and so on, sequentially starting all batteries. If a battery fails, it cannot output a signal, causing all batteries downstream of it to lose the ability to receive the output signal from the previous battery, resulting in a large number of batteries failing to start and affecting the overall efficient operation of the parallel battery pack. Utility Model Content

[0004] In view of the existing technical problem that once a battery fails, it cannot output a signal, causing all the batteries behind it to be unable to receive the output signal from the previous battery, resulting in a large number of batteries being unable to start and affecting the efficient operation of the overall parallel battery pack, this utility model is proposed.

[0005] The purpose of this invention is to provide a low-voltage energy storage battery with automatic address allocation and heartbeat monitoring based on a bus. The aim is to solve the technical problem that once a battery fails, all batteries downstream of it cannot receive the output signal from the previous battery because the battery cannot output a signal, resulting in a large number of batteries being unable to start and affecting the efficient operation of the overall parallel battery pack.

[0006] To solve the above technical problems, this utility model provides the following technical solution: a low-voltage energy storage battery with automatic address allocation and heartbeat monitoring based on a bus, comprising a battery master and N battery slaves, where N is a positive integer less than or equal to. The positive terminal of the battery master is electrically connected to the positive terminal of the first battery slave, and the positive terminals of the N battery slaves are connected sequentially. The negative terminal of the battery master is electrically connected to the negative terminal of the first battery slave, and the negative terminals of the N battery slaves are connected sequentially.

[0007] The battery master unit and N battery slave units are all connected in parallel on the CAN parallel bus and bus.

[0008] As a preferred embodiment of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring of this utility model, the battery master and N battery slaves are all composed of BMS motherboard, front panel, communication interface and cell module.

[0009] As a preferred embodiment of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring of this utility model, the BMS motherboard includes an MCU electrically connected to the BMS motherboard, an input / output module electrically connected to the BMS motherboard, a front-end sampling device electrically connected to the BMS motherboard, a CAN-PCS electrically connected to the BMS motherboard, a CAN parallel bus electrically connected to the BMS motherboard, and an RS bus electrically connected to the BMS motherboard.

[0010] As a preferred embodiment of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring of this utility model, the MCU is electrically connected to the U isolation chip, the VOA pin of the U isolation chip is electrically connected to the MCU, and the VIB pin of the U isolation chip is electrically connected to the MCU.

[0011] As a preferred embodiment of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring of this utility model, wherein: the VIA pin of the U isolation chip is connected to the U chip, and the VOB pin of the U isolation chip is connected to the U chip.

[0012] As a preferred embodiment of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring of this utility model, wherein: the U isolation chip is electrically connected to the transistor, the transistor pin B is connected to the U chip, and the transistor pin C is connected to the U chip.

[0013] As a preferred embodiment of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring of this utility model, wherein: one end of the U chip pin is electrically connected to the first fuse, one end of the U chip pin is electrically connected to the second fuse, and the U chip pin is connected to the next group of N battery slaves.

[0014] As a preferred embodiment of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring of this utility model, the MCU is electrically connected to a DC chopper, the MCU is electrically connected to a watchdog timer, and the MCU is electrically connected to a clock.

[0015] The beneficial effects of this utility model of a low-voltage energy storage battery with automatic address allocation and heartbeat monitoring based on a bus are as follows: during parallel use, if any battery fails and exits, the remaining battery pack can still operate efficiently. After the faulty battery is repaired or replaced, it can still operate normally and efficiently after being put back into the system, which greatly improves the overall fault-free operation time of the parallel battery pack. The failure and exit of any battery does not affect the normal operation of other battery packs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Among them:

[0017] Figure 1 This is a schematic diagram of the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring as described in this utility model.

[0018] Figure 2 This is a schematic diagram of the control circuit for the low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring as described in this utility model.

[0019] Figure 3 This is a schematic diagram of the monitoring unit for a low-voltage energy storage battery with automatic address allocation and heartbeat monitoring based on a bus, as described in this utility model.

[0020] In the diagram: Battery master unit 101, Battery slave unit 102, BMS main board 103, Front panel 104, Communication interface 105, Cell module 106, MCU 103a, Input / output module 103b, Front-end sampling 103c, CAN-PCS 103d, CAN parallel bus 103e, RS485 bus 103f, U7 isolation chip 107, U8 chip 108, Transistor 109, First fuse 201, Second fuse 202, DC chopper 203, Watchdog timer 204, Clock 205 Detailed Implementation

[0021] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0022] Many specific details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0023] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments.

[0024] Example 1, referring to Figures 1 to 3 This is the first embodiment of the present invention. This embodiment provides a low-voltage energy storage battery with automatic address allocation and heartbeat monitoring based on a bus, including a battery master 101 and N battery slaves 102, where N is a positive integer less than or equal to 31. The positive terminal of the battery master 101 is electrically connected to the positive terminal of the first battery slave 102, and the positive terminals of the N battery slaves 102 are connected sequentially. The negative terminal of the battery master 101 is electrically connected to the negative terminal of the first battery slave 102, and the negative terminals of the N battery slaves 102 are connected sequentially.

[0025] The battery master unit 101 and N battery slave units 102 are all connected in parallel on the CAN parallel bus and bus.

[0026] Furthermore, the battery host 101 and the N battery slaves 102 are all composed of a BMS motherboard 103, a front panel 104, a communication interface 105, and a cell module 106.

[0027] Furthermore, the BMS motherboard 103 includes an MCU 103a electrically connected to the BMS motherboard 103, a DI / DO 103b electrically connected to the BMS motherboard 103, a front-end sampling 103c electrically connected to the BMS motherboard 103, a CAN-PCS 103d electrically connected to the BMS motherboard 103, a CAN parallel bus 103e electrically connected to the BMS motherboard 103, and an RS485 bus 103f electrically connected to the BMS motherboard 103.

[0028] Furthermore, the MCU103a is electrically connected to the U7 isolation chip 107, the VOA pin of the U7 isolation chip 107 is electrically connected to the MCU103a, and the VIB pin of the U7 isolation chip 107 is electrically connected to the MCU103a.

[0029] Furthermore, pin VIA of the U7 isolation chip 107 is connected to the U8 chip 108, and pin VOB of the U7 isolation chip 107 is connected to the U8 chip 108.

[0030] Furthermore, the U7 isolation chip 107 is electrically connected to the transistor 109, pin B of the transistor 109 is connected to the U8 chip 108, and pin C of the transistor 109 is connected to the U8 chip 108.

[0031] Furthermore, one end of pin 6 of the U8 chip 108 is electrically connected to the first fuse 201, and one end of pin 7 of the U8 chip 108 is electrically connected to the second fuse 202. Pin 6 of the U8 chip 108 is connected to the next group of N battery slaves 102, and pin 7 of the U8 chip 108 is connected to the next group of N battery slaves 102.

[0032] Preferably, the MCU103a is electrically connected to DC / DC203, the MCU103a is electrically connected to VDOG204, and the MCU103a is electrically connected to RTC205.

[0033] It should be noted that the CPU uses NXP's i.MX RT1064 chip as the main CPU, a Cortex M7 architecture processor, to collect real-time cell data and charging / discharging current; collect real-time external switching signals to control the on / off state of the charging / discharging MOSFETs; statistically analyze and periodically store charging / discharging data; provide various cell protection mechanisms; estimate the battery's SOC, SOH, and SOP; handle communication with the inverter; and receive data signals from other batteries in the parallel system.

[0034] Usage: For parallel connection of each battery, typically the first battery is used as the master, and the DIP switches are set to the remaining batteries as slaves. The DIP switches are then set to the parallel network cable connecting the master and slaves. The connection is made from the master to the slave's CAN / RS485 interface, and from the slave's CAN / RS485 interface to the next slave's CAN / RS485 interface, and so on. CAN / RS485 interfaces on the same device can be interchanged. When the master is powered on, the MCU powers on and enters standby mode, initializing the U8 chip to receive mode. After recognizing the parallel master mode according to the DIP switches, the master starts up. The MCU's GPIO sends periodic data 0 and 1 to the RS485 transmit pin at a frequency of 50Hz, generating a heartbeat signal to the slave devices. After the master completes its self-test, it closes the pre-discharge MOS, outputting voltage on the positive and negative ports. When the next slave is powered on, the MCU powers on and enters standby mode, initializing the U8 chip to receive mode. After recognizing the parallel slave mode based on the DIP switch, the voltage at the external port and the heartbeat signal of the U8 receiver pin are detected, and the startup is automatically completed. After the slave completes its self-test, it sends a registration login message through the CAN parallel bus. After the master receives the slave's registration message, it distributes the communication address to the corresponding slave and continues to turn on the next slave. The startup process of the slave is the same as the above steps. During the entire operation, the slave's heartbeat signal is generated by the master. Turning off the battery of any slave will not affect the operation of other slaves.

[0035] In summary, during parallel operation, even if any battery fails and exits the system, the remaining battery pack can still operate efficiently. After the faulty battery is repaired or replaced, it can still operate normally and efficiently after being put back into the system, significantly improving the overall fault-free operation time of the parallel battery pack. The failure of any battery does not affect the normal operation of other battery packs.

[0036] Example 2, refer to Figure 3This is the second embodiment of the present invention, which differs from the first embodiment in that: the U7 isolation chip 107 is electrically connected to the transistor 109, the pin B of the transistor 109 is connected to the U8 chip 108, and the pin C of the transistor 109 is connected to the U8 chip 108.

[0037] Furthermore, one end of pin 6 of the U8 chip 108 is electrically connected to the first fuse 201, and one end of pin 7 of the U8 chip 108 is electrically connected to the second fuse 202. Pin 6 of the U8 chip 108 is connected to the next group of N battery slaves 102, and pin 7 of the U8 chip 108 is connected to the next group of N battery slaves 102.

[0038] Preferably, the MCU103a is electrically connected to the DC chopper 203, the MCU103a is electrically connected to the watchdog timer 204, and the MCU103a is electrically connected to the clock 205.

[0039] Usage: When transistor 109 is turned on, U8 chip 108 is in receive mode; when transistor 109 is not turned on, U8 chip 108 is in transmit mode. During initialization, U8 chip 108 is in receive mode. In master mode, U8 chip 108 is placed in transmit mode; in slave mode, U8 chip 108 is placed in receive mode.

[0040] In summary, during parallel operation, even if any battery fails and exits the system, the remaining battery pack can still operate efficiently. After the faulty battery is repaired or replaced, it can still operate normally and efficiently after being put back into the system, significantly improving the overall fault-free operation time of the parallel battery pack. The failure of any battery does not affect the normal operation of other battery packs.

[0041] It is important to note that the constructions and arrangements of this application shown in several different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who consult this disclosure will readily understand that many modifications are possible (e.g., changes in the size, dimensions, structure, shape and proportion of various elements, as well as parameter values ​​(e.g., temperature, pressure, etc.), mounting arrangements, use of materials, color, orientation, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in this application). For example, an element shown as integrally formed may be composed of multiple parts or elements, the position of elements may be inverted or otherwise altered, and the nature or number or position of discrete elements may be changed or altered. Therefore, all such modifications are intended to be included within the scope of this utility model. The order or sequence of any process or method steps may be changed or rearranged according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure described herein that performs the function, and not only structural equivalents but also equivalent structures. Without departing from the scope of this invention, other substitutions, modifications, alterations, and omissions may be made in the design, operation, and arrangement of the exemplary embodiments. Therefore, this invention is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

[0042] Furthermore, in order to provide a concise description of exemplary embodiments, not all features of actual embodiments (i.e., those features that are not relevant to the best mode of carrying out the present invention as currently considered, or those features that are not relevant to implementing the present invention) may be omitted.

[0043] It should be understood that numerous specific implementation decisions can be made during the development of any practical implementation, such as in any engineering or design project. Such development efforts may be complex and time-consuming, but for those skilled in the art who benefit from this disclosure, the development effort will be a routine work of design, manufacturing, and production without requiring much experimentation.

[0044] It should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and are not intended to limit it. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solution of this utility model without departing from the spirit and scope of the technical solution of this utility model, and all such modifications or substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A low-voltage energy storage battery based on bus-based automatic address allocation and heartbeat monitoring, characterized in that: It includes a battery master unit (101) and N battery slave units (102), where N is a positive integer less than or equal to 31. The positive terminal of the battery master unit (101) is electrically connected to the positive terminal of the first battery slave unit (102), and the positive terminals of the N battery slave units (102) are connected sequentially. The negative terminal of the battery master unit (101) is electrically connected to the negative terminal of the first battery slave unit (102), and the negative terminals of the N battery slave units (102) are connected sequentially. The battery master unit (101) and N battery slave units (102) are all connected in parallel on the CAN parallel bus and bus.

2. The low-voltage energy storage battery with bus-based automatic address allocation and heartbeat monitoring as described in claim 1, characterized in that: The battery host (101) and N battery slaves (102) are all composed of a BMS motherboard (103), a front panel (104), a communication interface (105), and a cell module (106).

3. The low-voltage energy storage battery with bus-based automatic address allocation and heartbeat monitoring as described in claim 2, characterized in that: The BMS motherboard (103) includes an MCU (103a) electrically connected to the BMS motherboard (103), an input / output module (103b) electrically connected to the BMS motherboard (103), a front-end sampling (103c) electrically connected to the BMS motherboard (103), a CAN-PCS (103d) electrically connected to the BMS motherboard (103), a CAN parallel bus (103e) electrically connected to the BMS motherboard (103), and an RS485 bus (103f) electrically connected to the BMS motherboard (103).

4. The low-voltage energy storage battery with bus-based automatic address allocation and heartbeat monitoring as described in claim 3, characterized in that: The MCU (103a) is electrically connected to the U7 isolation chip (107), the VOA pin of the U7 isolation chip (107) is electrically connected to the MCU (103a), and the VIB pin of the U7 isolation chip (107) is electrically connected to the MCU (103a).

5. The low-voltage energy storage battery with bus-based automatic address allocation and heartbeat monitoring as described in claim 4, characterized in that: The VIA pin of the U7 isolation chip (107) is connected to the U8 chip (108), and the VOB pin of the U7 isolation chip (107) is connected to the U8 chip (108).

6. The low-voltage energy storage battery with bus-based automatic address allocation and heartbeat monitoring as described in claim 5, characterized in that: The U7 isolation chip (107) is electrically connected to the transistor (109), and pin B of the transistor (109) is connected to the U8 chip (108), and pin C of the transistor (109) is connected to the U8 chip (108).

7. The low-voltage energy storage battery with bus-based automatic address allocation and heartbeat monitoring as described in claim 6, characterized in that: One end of pin 6 of the U8 chip (108) is electrically connected to the first fuse (201), and one end of pin 7 of the U8 chip (108) is electrically connected to the second fuse (202). Pin 6 of the U8 chip (108) is connected to the next group of N battery slaves (102), and pin 7 of the U8 chip (108) is connected to the next group of N battery slaves (102).

8. The low-voltage energy storage battery with bus-based automatic address allocation and heartbeat monitoring as described in claim 7, characterized in that: The MCU (103a) is electrically connected to a DC chopper (203), the MCU (103a) is electrically connected to a watchdog timer (204), and the MCU (103a) is electrically connected to a clock (205).

Images