Protection circuit of charging and discharging chip, charging and discharging chip and electronic equipment

Abstract

The utility model discloses a protection circuit of a charging and discharging chip, the charging and discharging chip and electronic equipment, and belongs to the technical field of electronics. The protection circuit comprises a detection module and a state controller, the detection module is connected with the state controller; the detection module is respectively connected with a first switch node and a second switch node of the buck-boost circuit; the state controller is connected with the switch tube driving pin; when the voltage of the first switch node is greater than a first target voltage and / or the voltage of the second switch node is greater than a second target voltage, the detection module outputs a signal to the state controller in a first state; the state controller closes the drive of the switching tube in the buck-boost circuit under the condition that the signal of the first state is input. According to the protection circuit of the charging and discharging chip, the charging and discharging chip and the electronic equipment disclosed by the invention, a device which is short-circuited can be timely and automatically identified, so that external charging / discharging equipment and other devices at the periphery of the charging and discharging chip can be protected, and higher safety is achieved.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, and in particular relates to a protection circuit for a charge / discharge chip, a charge / discharge chip, and an electronic device. Background Technology

[0002] For charge / discharge chips with a 4-transistor BUCK-BOOST architecture, a single-point failure, if not handled promptly and effectively, may cause further damage to other components or external charging / discharging equipment. A single-point failure refers to a short circuit in one of the following components on the power path during power conversion: the VBUS current sensing resistor, the battery current sensing resistor, or the high-side switching transistor between VBUS and VBAT.

[0003] Most existing BUCK-BOOST architecture charging and discharging chips rely on the protection functions built into external charging / discharging devices to deal with single-point failures. However, the above methods cannot protect peripheral devices and equipment (such as other power devices besides charging / discharging devices), and may even cause damage to the chip itself. Utility Model Content

[0004] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a protection circuit for a charge / discharge chip, a charge / discharge chip, and an electronic device, which can protect the peripheral devices and equipment of the charge / discharge chip.

[0005] In a first aspect, this application provides a protection circuit for a charging and discharging chip, the charging and discharging chip including a buck-boost circuit based on four switching transistors; the circuit includes: a detection module and a status controller;

[0006] The detection module is connected to the state controller; the detection module is also connected to the first and second switching nodes of the buck-boost circuit.

[0007] The state controller is connected to the high-side switch driver pin on the buck side, the high-side switch driver pin on the boost side, the low-side switch driver pin on the buck side, and the low-side switch driver pin on the boost side of the buck-boost circuit, respectively.

[0008] When the voltage of the first switching node is greater than the first target voltage and / or the voltage of the second switching node is greater than the second target voltage, the detection module outputs a first state signal to the state controller.

[0009] When the state controller receives a signal indicating the first state, it shuts down the drive of the switching transistor in the buck-boost circuit.

[0010] According to the protection circuit of the charging / discharging chip of this application, the detection module detects the short-circuit failure of either the VBUS high-side switch transistor or the VBAT high-side switch transistor. It can automatically identify the short-circuited device in a timely manner and shut down the driving of the switch transistor in the buck-boost circuit, thereby protecting the external charging / discharging equipment and other devices around the charging / discharging chip, and has stronger safety.

[0011] According to one embodiment of this application, the detection module includes a first detection unit and a second detection unit;

[0012] The input terminal of the first detection unit is connected to the first switch node; the output terminal of the first detection unit is connected to the first input terminal of the state controller; when the voltage of the first switch node is greater than the first target voltage, the output signal of the output terminal of the first detection unit is the first state; when the voltage of the first switch node is less than or equal to the first target voltage, the output signal of the output terminal of the first detection unit is the second state.

[0013] The input terminal of the second detection unit is connected to the second switch node; the output terminal of the second detection unit is connected to the second input terminal of the state controller; when the voltage of the second switch node is greater than the second target voltage, the output signal of the output terminal of the second detection unit is the first state; when the voltage of the second switch node is less than or equal to the second target voltage, the output signal of the output terminal of the second detection unit is the second state.

[0014] According to one embodiment of this application, the protection circuit of the charging and discharging chip further includes: a current sampling module and an arithmetic unit;

[0015] The current sampling module is connected to the arithmetic unit; the arithmetic unit is connected to the state controller;

[0016] The current sampling module is connected to both ends of the VBUS current sensing resistor and the battery current sensing resistor of the buck-boost circuit, respectively, to obtain the voltage across the VBUS current sensing resistor and the voltage across the battery current sensing resistor.

[0017] When the voltage across the current sensing resistor at the VBUS terminal is abnormal or the voltage across the current sensing resistor at the battery terminal is abnormal, the signal output by the arithmetic unit to the state controller is the first state.

[0018] According to the protection circuit of the charging / discharging chip of this application, the short-circuit failure of either the VBUS current sensing resistor or the VBAT current sensing resistor can be detected by the current sampling module and the arithmetic unit. The short-circuited device can be identified in a timely and automatic manner and the driving of the switching transistor in the buck-boost circuit can be turned off, thereby protecting the external charging / discharging equipment and other devices around the charging / discharging chip, and providing stronger safety.

[0019] According to one embodiment of this application, the current sampling module includes a first switching unit, a second switching unit, and a current sampling unit;

[0020] The first switching unit connects the current sampling unit to both ends of the VBUS terminal current sensing resistor;

[0021] The second switching unit connects the current sampling unit to both ends of the current sensing resistor at the battery terminal;

[0022] The output terminal of the first detection unit is connected to the control terminal of the first switch unit and the control terminal of the second switch unit; the output terminal of the second detection unit is connected to the control terminal of the first switch unit and the control terminal of the second switch unit.

[0023] When the output signal at the output terminal of the first detection unit is in the first state, the first switch unit and the second switch unit are in the open state; when the output signal at the output terminal of the second detection unit is in the first state, the first switch unit and the second switch unit are in the open state; when the output signal at the output terminal of the first detection unit and the output signal at the output terminal of the second detection unit are in the second state, the first switch unit and the second switch unit are in the closed state.

[0024] According to one embodiment of this application, the current sampling module further includes a NOR gate;

[0025] The output terminals of the first detection unit and the second detection unit are respectively connected to one input terminal of the NOR gate; the output terminal of the NOR gate is respectively connected to the control terminal of the first switching unit and the control terminal of the second switching unit.

[0026] According to one embodiment of this application, the first output terminal of the arithmetic unit is connected to the third input terminal of the state controller; the second output terminal of the arithmetic unit is connected to the fourth input terminal of the state controller.

[0027] When the voltage across the current sensing resistor at the VBUS terminal is abnormal, the output signal at the first output terminal of the arithmetic unit is in the first state.

[0028] When the voltage across the current sensing resistor at the battery terminal is abnormal, the output signal at the second output terminal of the arithmetic unit is in the first state.

[0029] According to one embodiment of this application, when the target parameter is greater than a first threshold, the output signal of the first output terminal of the arithmetic unit is the first state;

[0030] When the target parameter is less than the second threshold, the output signal of the second output terminal of the arithmetic unit is in the first state; the second threshold is less than the first threshold.

[0031] The target parameter is the ratio of the first product to the second product; the first product is the product of the voltage at the positive input terminal of the VBUS current sensing resistor and the current of the VBUS current sensing resistor; the second product is the product of the voltage at the positive input terminal of the battery current sensing resistor and the current of the battery current sensing resistor.

[0032] According to one embodiment of this application, the state controller includes a first OR gate, a second OR gate, a third OR gate, and a driver;

[0033] The input terminals of the first OR gate are respectively connected to the output terminals of the first detection unit and the second detection unit;

[0034] The input terminals of the second OR gate are respectively connected to the first output terminal and the second output terminal of the arithmetic unit;

[0035] The input terminal of the third OR gate is connected to the output terminal of the first OR gate and the output terminal of the second OR gate, respectively.

[0036] The output of the third OR gate is connected to the driver; the driver is connected to the buck-side high-side switch driver pin, the boost-side high-side switch driver pin, the buck-side low-side switch driver pin, and the boost-side low-side switch driver pin of the buck-boost circuit, respectively.

[0037] When the output signal at the output terminal of the third OR gate is in the first state, the driver pulls down the high-side switch driver pin on the buck side, the high-side switch driver pin on the boost side, the low-side switch driver pin on the buck side, and the low-side switch driver pin on the boost side.

[0038] Secondly, this application provides a charge / discharge chip, which includes a protection circuit for the charge / discharge chip as described in the first aspect above.

[0039] According to the charging and discharging chip of this application, when a single-point failure occurs, the internal circuit can identify the current failure point and perform abnormal protection to protect the chip, other external devices and equipment.

[0040] Thirdly, this application provides an electronic device including a charge / discharge chip as described in the second aspect.

[0041] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0042] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0043] Figure 1 This is one of the structural schematic diagrams of the protection circuit of the charging and discharging chip provided in the embodiments of this application;

[0044] Figure 2 This is a schematic diagram of the buck-boost circuit provided in the embodiments of this application;

[0045] Figure 3 This is a second schematic diagram of the protection circuit of the charging and discharging chip provided in the embodiments of this application;

[0046] Figure 4 This is a schematic diagram of the detection module provided in an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the current sampling module provided in an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of the structure of the state controller provided in an embodiment of this application;

[0049] Figure 7 This is a schematic diagram of the chip structure provided in the embodiments of this application;

[0050] Figure 8 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application.

[0051] Reference numerals: 110, detection module; 120, state controller; 130, current sampling module; 140, arithmetic unit; 111, first detection unit; 112, second detection unit; 131, current sampling unit; 132, NOR gate; 610, first OR gate; 620, second OR gate; 630, third OR gate; 640, driver; 650, state machine and core. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0053] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0054] The protection circuit, charging / discharging chip, and electronic device provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0055] like Figure 1 As shown, the protection circuit of the charge / discharge chip includes a detection module 110 and a status controller 120. The charge / discharge chip includes a buck-boost circuit based on four switching transistors.

[0056] In actual implementation, such as Figure 2 As shown, a typical buck-boost circuit may include four switching transistors: Q1, Q2, Q3, and Q4. Q1, Q2, Q3, and Q4 can be any type of switching transistor, and the specific types of Q1, Q2, Q3, and Q4 are not limited in this embodiment. In some embodiments, Q1, Q2, Q3, and Q4 can be N-channel switching transistors. Q1 and Q2 are located on the high side (HS, also known as the "high-side") and low side (LS, also known as the "low-side") of the buck side, respectively, while Q3 and Q4 are located on the high side and low side of the boost side. Q1 is the high-side switch on the buck side, also known as the VBUS high-side switch; Q2 is the low-side switch on the buck side, also known as the VBUS low-side switch; Q3 is the high-side switch on the boost side, also known as the battery high-side switch; and Q4 is the low-side switch on the boost side, also known as the battery low-side switch.

[0057] The buck side also includes the VBUS terminal (V represents voltage, BUS represents bus) and the VBUS current sensing resistor R7, as well as the buck-side high-side switch drive pin HD1, the positive input terminal CSP_VBUS of the VBUS current sensing resistor R7, the negative input terminal CSN_VBUS of the VBUS current sensing resistor R7, and the first switching node SW1. The first switching node SW1 is a buck switching node.

[0058] The boost side also includes the VBAT terminal (i.e., the battery terminal, where V represents voltage and BAT represents battery) and the battery terminal current sensing resistor R8, as well as the boost side high-side switch driver pin HD2, the boost side low-side switch driver pin LD2, the positive input terminal CSP_VBAT of the battery terminal current sensing resistor R8, the negative input terminal CSN_VBUS of the battery terminal current sensing resistor R8, and the second switching node SW2. The second switching node SW2 is the boost switching node.

[0059] The buck side and the boost side can be connected through a path consisting of the first switching node SW1, the inductor L1, and the second switching node SW2.

[0060] The detection module 110 is connected to the status controller 120; the detection module 110 is connected to the first switch node SW1 and the second switch node SW2 of the buck-boost circuit respectively.

[0061] In actual operation, the detection module 110 can be connected to the state controller 120 and output signals to the state controller 120. The pins of the buck-boost circuit to which the detection module 110 is connected may include the first switching node SW1 and the second switching node SW2.

[0062] The state controller 120 is connected to the buck-side high-side switch drive pin HD1, the boost-side high-side switch drive pin HD2, the buck-side low-side switch drive pin LD1, and the boost-side low-side switch drive pin LD2 of the buck-boost circuit, respectively.

[0063] In actual implementation, the pins of the buck-boost circuit connected to the state controller 120 may include the buck-side high-side switch driver pin HD1, the boost-side high-side switch driver pin HD2, the buck-side low-side switch driver pin LD1, and the boost-side low-side switch driver pin LD2.

[0064] When the voltage of the first switch node SW1 is greater than the first target voltage and / or the voltage of the second switch node SW2 is greater than the second target voltage, the detection module 110 outputs a signal to the state controller 120 as the first state.

[0065] In actual operation, the detection module 110 can detect whether the high-side switching transistors on the buck side and boost side have single-point failures by detecting the voltage of the first switching node SW1 and the voltage of the second switching node SW2.

[0066] The detection module 110 can detect whether the voltage of the first switch node SW1 is greater than the first target voltage, and whether the voltage of the second switch node SW2 is greater than the second target voltage.

[0067] If the voltage at the first switching node SW1 is greater than the first target voltage, it indicates that the high-side switch on the buck converter side has a short circuit, resulting in a single-point failure. Conversely, if the voltage at the first switching node SW1 is less than or equal to the first target voltage, it indicates that the high-side switch on the buck converter side has not a short circuit, and the high-side switch on the buck converter side has not experienced a single-point failure.

[0068] If the voltage at the second switching node SW2 is greater than the second target voltage, it indicates that the high-side switch on the boost side has short-circuited, resulting in a single-point failure. Conversely, if the voltage at the second switching node SW2 is less than or equal to the second target voltage, it indicates that the high-side switch on the boost side has not short-circuited, and the high-side switch on the boost side has not failed at a single point.

[0069] The first target voltage and the second target voltage can be set according to the actual situation. The specific values ​​of the first target voltage and the second target voltage are not limited in the embodiments of this application.

[0070] In some embodiments, the detection module 110 may employ any voltage detection circuit or voltage comparison circuit.

[0071] In actual execution, when the voltage of the first switch node SW1 is greater than the first target voltage and / or the voltage of the second switch node SW2 is greater than the second target voltage, the output signal of the detection module 110 is in the first state.

[0072] The first state is a level state of the output signal. In some embodiments, the first state can be a high level state.

[0073] When the first state signal is input, the state controller 120 turns off the drive of the switching transistor in the buck-boost circuit.

[0074] In actual execution, when the signal from the input state controller 120 to the detection module 110 is in the first state, it indicates a single-point failure of the high-side switch transistor. The detection module 110 detects the abnormality, and the state controller 120 pulls down the high-side switch transistor drive pin HD1 on the buck side, the high-side switch transistor drive pin HD2 on the boost side, the low-side switch transistor drive pin LD1 on the buck side, and the low-side switch transistor drive pin LD2 on the boost side of the buck-boost circuit, thereby turning off the drive of the switch transistor in the buck-boost circuit, thus shutting down the buck-boost circuit and preventing the charging and discharging chip from charging and discharging.

[0075] According to the protection circuit of the charging / discharging chip provided in the embodiments of this application, the detection module detects the short-circuit failure of any device among the VBUS high-side switch and VBAT high-side switch, and can automatically identify the short-circuited device in a timely manner and shut down the drive of the switch in the buck-boost circuit, thereby protecting the external charging / discharging equipment and other devices around the charging / discharging chip, and has stronger safety.

[0076] In some embodiments, such as Figure 4 As shown, the detection module 110 includes a first detection unit 111 and a second detection unit 112.

[0077] In actual implementation, the detection module 110 may include a first detection unit 111 and a second detection unit 112. The first detection unit 111 can be used to detect the voltage of the first switching node SW1. The second detection unit 112 can be used to detect the voltage of the second switching node SW1.

[0078] The input terminal of the first detection unit 111 is connected to the first switch node SW1; the output terminal of the first detection unit 111 is connected to the first input terminal of the state controller 120; when the voltage of the first switch node SW1 is greater than the first target voltage, the output signal of the output terminal of the first detection unit 111 is in the first state; when the voltage of the first switch node SW1 is less than or equal to the first target voltage, the output signal of the output terminal of the first detection unit 111 is in the second state.

[0079] In actual operation, the input terminal of the first detection unit 111 is connected to the first switch node SW1. The first input terminal of the state controller 120 is connected to the output terminal of the first detection unit 111, and the detection result of the first detection unit 111 can be input into the state controller 120.

[0080] The first detection unit 111 can detect whether the voltage of the first switch node SW1 is greater than the first target voltage. If it is greater, the output terminal of the first detection unit 111 can output a signal in the first state, so that the signal output by the detection module 110 to the state controller 120 includes the signal in the first state; if it is less than or equal to, the output terminal of the first detection unit 111 can output a signal in the second state, so that the signal output by the detection module 110 to the state controller 120 includes the signal in the second state.

[0081] In some embodiments, the first state and the second state are different level states of the signal. When the first state is a high level state, the second state can be a low level state; and vice versa.

[0082] The input terminal of the second detection unit 112 is connected to the second switch node SW2; the output terminal of the second detection unit 112 is connected to the second input terminal of the state controller 120; when the voltage of the second switch node SW2 is greater than the second target voltage, the output signal of the output terminal of the second detection unit 112 is in the first state; when the voltage of the second switch node SW2 is less than or equal to the second target voltage, the output signal of the output terminal of the second detection unit 112 is in the second state.

[0083] In actual operation, the input terminal of the second detection unit 112 is connected to the second switch node SW2. The second input terminal of the state controller 120 is connected to the output terminal of the second detection unit 112, and the detection result of the second detection unit 112 can be input into the state controller 120.

[0084] The second detection unit 112 can detect whether the voltage of the second switch node SW2 is greater than the second target voltage. If it is greater, the output terminal of the second detection unit 112 can output a signal in the first state, so that the signal output by the detection module 110 to the state controller 120 includes the signal in the first state; if it is less than or equal to, the output terminal of the second detection unit 112 can output a signal in the second state, so that the signal output by the detection module 110 to the state controller 120 includes the signal in the second state.

[0085] In some embodiments, the first detection unit 111 may include a first comparator, a third switching unit S3, a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1. The first switching node SW1 can be connected to the positive input terminal of the first comparator via the third switching unit S3. A third resistor R3 and a first capacitor C1 are connected in parallel between the positive input terminal of the first comparator and ground. The first capacitor C1 performs filtering. The third resistor R3 pulls down the signal input to the positive input terminal of the first comparator. The resistance value of the third resistor R3 is not limited in this embodiment; for example, the resistance value of the third resistor R3 can be 5.1 kΩ. The third switching unit S3 can be controlled by the signal SW1 control output by the state controller 120.

[0086] The third switching unit S3 can be any type of switching element, such as an analog switch.

[0087] The negative input of the first comparator can be connected to a voltage divider circuit. This voltage divider circuit can consist of a reference voltage VREF provided by the state controller 120, a first resistor R1, and a second resistor R2. The reference voltage VREF can be connected to the positive input of the first comparator via the first resistor R1 and the second resistor R2. The connection point of the first resistor R1 and the second resistor R2 is connected to the negative input of the first comparator.

[0088] The first target voltage is the input voltage at the negative input terminal of the first comparator, which can be obtained by dividing the reference voltage VREF using a first resistor R1 and a second resistor R2, etc. In some embodiments, the first target voltage can be 0.5V.

[0089] The output signal of the first comparator is SW1 DET. The output of the first comparator can be connected to the state controller 120 and the current sampling module 130.

[0090] The second detection unit 112 may include a second comparator, a fourth switching unit S4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a second capacitor C2. The signal output by the second comparator is SW2 DET, and the output terminal of the second comparator can be connected to the state controller 120 and the current sampling module 130. The structure and internal and external connections of the second detection unit 112 are the same as those of the first detection unit 111, and will not be described again here.

[0091] In actual implementation, the detection module 110 can realize the single-point failure protection function of the high-side switch tube through the first detection unit 111 and the second detection unit 112. Whenever the charging / discharging chip receives an external power-on signal, that is, when the charging / discharging signal arrives, the state machine and core in the state controller 120 can provide a reference voltage VREF to the detection module 110 and pull up the SW1 and SW2 control signals (that is, SW1 control and SW2 control, which can be combined into SW control), so that the third switch unit S3 and the fourth switch unit S4 are both closed.

[0092] Both the third switch unit S3 and the fourth switch unit S4 are closed. Pins SW1 and SW2 are connected to their respective comparators and filtered by their respective capacitors C1 and C2. They are also discharged to GND through R3 and R6.

[0093] The positive input of the first comparator is the voltage at pin SW1, and the negative input is the 0.5V voltage obtained from the voltage divider circuit of VREF. The first comparator compares these two voltages. If the high-side switch at the VBUS terminal is short-circuited, VBUS and SW1 are directly connected, and the voltage at SW1 is the same as the external VBUS voltage, which cannot be pulled low by R3. The input voltage at the positive input of the first comparator is the VBUS voltage.

[0094] The positive input of the second comparator is the voltage at pin SW2, and the negative input is the voltage of 0.5V obtained from the voltage divider circuit of VREF (an example of a second target voltage). The second comparator compares these two voltages. If the high-side switch at the VBAT terminal is short-circuited, VBAT is directly connected to SW2, and the voltage at SW2 is the same as the external VBAT voltage, which cannot be pulled low by R6. The positive voltage of the second comparator is then the VBUS voltage.

[0095] With neither the high-side switching transistors at the VBUS nor VBAT terminals short-circuited, the floating current on SW1 and SW2 is discharged by their respective pull-down resistors since neither high-side switching transistor is turned on, and the voltages of SW1 and SW2 are both 0V.

[0096] Therefore, in the absence of a short circuit, the corresponding comparator can output a low level, and the charging / discharging chip can charge and discharge normally. When the VBUS high-side switch is short-circuited, SW1 DET outputs high; when the VBAT high-side switch is short-circuited, SW2 DET outputs high. When the state controller 120 receives either SW1 DET or SW2 DET as high, the drivers pull HD1, HD2, LD1, and LD2 low, thereby shutting down the charging / discharging chip and prohibiting charging and discharging.

[0097] According to the protection circuit of the charging / discharging chip provided in the embodiments of this application, the short-circuit failure of the VBUS high-side switch is detected by the first detection unit, and the short-circuit failure of the VBAT high-side switch is detected by the first detection unit. The device that has short-circuited can be identified in a timely and automatic manner, thereby turning off the drive of the switch in the buck-boost circuit in a timely manner. This can protect the external charging / discharging equipment and other devices around the charging / discharging chip, and has stronger safety.

[0098] In some embodiments, such as Figure 3 As shown, the protection circuit of the charging and discharging chip also includes a current sampling module 130 and an arithmetic unit 140. The current sampling module 130 is connected to the arithmetic unit 140; the arithmetic unit 140 is connected to the state controller 120.

[0099] In actual implementation, the protection circuit of the charging and discharging chip may also include a current sampling module 130 and an arithmetic unit 140.

[0100] In some embodiments, the current sampling module 130 may employ a current sampling module included in a charging and discharging chip in the related art to obtain the current at the VBUS terminal of the buck-boost circuit and the current at the battery terminal.

[0101] In actual operation, the current sampling module 130 can be connected to the arithmetic unit 140, so that the data obtained by the current sampling module 130 through current sampling can be transmitted to the arithmetic unit 140.

[0102] The arithmetic unit 140 can process the current data obtained by the current sampling module 130 and detect whether the current sensing resistor at the VBUS terminal and the current sensing resistor at the battery terminal have single-point failure.

[0103] The arithmetic unit 140 is connected to the state controller 120, so that the detection results obtained by the arithmetic unit 140 can be input into the state controller 120.

[0104] The state controller 120 can be connected to the current sampling module 130 to provide the current sampling module 130 with a clock signal CLK (as the clock for current sampling) and a reference voltage VREF.

[0105] The current sampling module 130 is connected to both ends of the VBUS current sensing resistor R7 and the battery current sensing resistor R8 of the buck-boost circuit, respectively, to obtain the voltage across the VBUS current sensing resistor R7 and the voltage across the battery current sensing resistor R8.

[0106] In actual implementation, the pins of the buck-boost circuit connected to the current sampling module 130 may include the positive input terminal CSP_VBUS of the VBUS current sensing resistor R7, the negative input terminal CSN_VBUS of the VBUS current sensing resistor R7, the positive input terminal CSP_VBAT of the battery current sensing resistor R8, and the negative input terminal CSN_VBUS of the battery current sensing resistor R8.

[0107] It is understandable that the current in resistors R7 and R8 can be obtained by dividing the difference in voltage across them by their resistance values. Therefore, obtaining the voltage across resistors R7 and R8 can achieve current sampling.

[0108] When the voltage across the current sensing resistor R7 at the VBUS terminal or the voltage across the current sensing resistor R8 at the battery terminal is abnormal, the arithmetic unit 120 outputs a signal to the state controller 120 in the first state.

[0109] In actual operation, the arithmetic unit 120 can determine whether the voltage across the current sensing resistor R7 at the VBUS terminal is normal. An abnormal voltage across the current sensing resistor R7 indicates a short circuit, a single-point failure. Conversely, a normal voltage across the current sensing resistor R7 indicates no short circuit and no single-point failure.

[0110] The arithmetic unit 120 can determine whether the voltage across the current sensing resistor R8 at the battery terminal is normal. An abnormal voltage across R8 indicates a short circuit and single-point failure. Conversely, a normal voltage across R8 indicates no short circuit and no single-point failure.

[0111] In some embodiments, the arithmetic unit 120 may be a digital arithmetic unit, etc.

[0112] In the event of an abnormal voltage across the current sensing resistor R7 at the VBUS terminal and / or an abnormal voltage across the current sensing resistor R8 at the battery terminal, the output signal of the arithmetic unit 120 is in the first state.

[0113] When the state of the signal from the input state controller 120 to the arithmetic unit 120 is in the first state, it indicates that there is a single-point failure of the current sensing resistor. The arithmetic unit 120 detects the abnormality and the state controller 120 pulls HD1, HD2, LD1, and LD2 low, thereby turning off the driving of the switching transistor in the buck-boost circuit, thus shutting down the buck-boost circuit and preventing the charging and discharging chip from charging and discharging.

[0114] According to the protection circuit of the charging / discharging chip provided in the embodiments of this application, the short-circuit failure of either the VBUS current sensing resistor or the VBAT current sensing resistor is detected by the current sampling module and the arithmetic unit. The short-circuited device can be identified in a timely and automatic manner, and the driving of the switching transistor in the buck-boost circuit can be turned off. This can protect the external charging / discharging equipment and other devices around the charging / discharging chip, and has stronger safety.

[0115] In some embodiments, reference Figure 5 The current sampling module 130 includes a first switching unit S1, a second switching unit S2, and a current sampling unit 131. The first switching unit S1 connects the current sampling unit 131 to both ends of the current sensing resistor R7 at the VBUS terminal; the second switching unit S2 connects the current sampling unit 131 to both ends of the current sensing resistor R8 at the battery terminal.

[0116] In actual operation, the CSP_VBUS and CSN_VBUS pins are both connected to the first switching unit S1, and the CSP_VBAT and CSN_VBAT pins are both connected to the second switching unit S2. Both the first switching unit S1 and the second switching unit S2 are connected to the current sampling unit 131.

[0117] In some embodiments, the current sampling unit 131 may include a mixer (MUX), a buffer, an analog-to-digital converter (ADC), and a data register. The MUX may be connected to the buffer and to a reference voltage VREF provided by the state controller 120. The buffer is connected to the ADC. The ADC is connected to the data register and to a clock signal CLK provided by the state controller 120. The data register may be connected to the arithmetic unit 140. In some embodiments, the data register may be a 12-bit data register.

[0118] The output terminal of the first detection unit 111 is connected to the control terminal of the first switch unit S1 and the control terminal of the second switch unit S2; the output terminal of the second detection unit 112 is connected to the control terminal of the first switch unit S1 and the control terminal of the second switch unit S2.

[0119] In actual operation, the control terminals of the first switching unit S1 and the second switching unit S2 are both connected to the output terminals of the first detection unit 111 and the second detection unit 112. Therefore, the states of the first switching unit S1 and the second switching unit S2 are both controlled by the outputs of the first detection unit 111 and the second detection unit 112.

[0120] When the output signal at the output terminal of the first detection unit 111 is in the first state, the first switch unit S1 and the second switch unit S2 are in the open state; when the output signal at the output terminal of the second detection unit 112 is in the first state, the first switch unit S1 and the second switch unit S2 are in the open state; when the output signal at the output terminal of the first detection unit 111 and the output signal at the output terminal of the second detection unit 112 are in the second state, the first switch unit S1 and the second switch unit S2 are in the closed state.

[0121] In actual operation, when at least one of the output signals of the control terminal of the first switching unit S1 and the output terminal of the second detection unit 112 is in the first state, both the first switching unit S1 and the second switching unit S2 are in the open state, and the current sampling module 130 does not work; when neither of the output signals of the control terminal of the first switching unit S1 and the output terminal of the second detection unit 112 is in the first state (i.e. both are in the second state), both the first switching unit S1 and the second switching unit S2 are in the closed state, and the current sampling module 130 works.

[0122] According to the protection circuit of the charging / discharging chip provided in the embodiments of this application, the detection module detects the short-circuit failure of the VBUS high-side switch and the VBAT high-side switch. When both the VBUS high-side switch and the VBAT high-side switch fail short-circuit, the current sampling module is controlled to work. Furthermore, through the current sampling module and the arithmetic unit, the short-circuit failure of any one of the VBUS current sensing resistor and the VBAT current sensing resistor can be detected in a timely and automatic manner. This allows for timely shutdown of the driving of the switching transistor in the buck-boost circuit, protecting external charging / discharging equipment and other peripheral devices of the charging / discharging chip, thus providing stronger safety.

[0123] In some embodiments, the current sampling module 130 further includes a NOR gate 132; the output terminal of the first detection unit 111 and the output terminal of the second detection unit 112 are respectively connected to one input terminal of the NOR gate 132; the output terminal of the NOR gate 132 is respectively connected to the control terminal of the first switching unit S1 and the control terminal of the second switching unit S2.

[0124] In actual execution, the control terminals of the first switching unit S1 and the second switching unit S2 are connected to the results of SW1 DET and SW2 DET output by the detection module 110 after integration by the NOR gate 132.

[0125] When the NOR gate 132 in the current sampling module 130 receives either the abnormal signal SW1 DET or SW2 DET as high, the output of the NOR gate 132 is always low, preventing the opening of switches S1 and S2 for current sampling. Only when both SW1 DET and SW2 DET are low will the NOR gate 132 output a high-level signal to open switches S1 and S2, allowing the current sampling module 130 to operate. The output signal of the NOR gate 132 can be denoted as HMOSDET RESULT.

[0126] According to the protection circuit of the charging and discharging chip provided in the embodiments of this application, by integrating the outputs of the first detection unit and the second detection unit with NOR gates, the first switching unit and the second switching unit can be controlled. This enables the current sampling module to work when both the VBUS high-side switch and the VBAT high-side switch fail due to short circuit, while the current sampling module does not work when either the VBUS high-side switch or the VBAT high-side switch fails due to short circuit. This saves energy and improves safety.

[0127] In some embodiments, the first output terminal of the arithmetic unit 140 is connected to the third input terminal of the state controller 120; the second output terminal of the arithmetic unit 140 is connected to the fourth input terminal of the state controller 120.

[0128] In actual operation, the first output terminal of the arithmetic unit 140 is connected to the third input terminal of the state controller 120, outputting a VBUS RCSDET detection signal. The VBUS RCSDET detection signal can be used to indicate whether the voltage across the current sensing resistor R7 at the VBUS terminal is normal.

[0129] The second output terminal of the arithmetic unit 140 is connected to the fourth input terminal of the state controller 120, and outputs a VBAT RCSDET detection signal. The VBAT RCSDET detection signal can be used to indicate whether the voltage across the current sensing resistor R8 at the battery terminal is normal.

[0130] When the voltage across the current sensing resistor R7 at the VBUS terminal is abnormal, the output signal at the first output terminal of the arithmetic unit 140 is in the first state.

[0131] In actual execution, the arithmetic unit 140 detects that the voltage across the current sensing resistor R7 at the VBUS terminal is abnormal, and the output signal VBUS RCSDET at the first output terminal of the arithmetic unit 140 is in the first state.

[0132] When the voltage across the current sensing resistor R8 at the battery terminal is abnormal, the output signal at the second output terminal of the arithmetic unit 140 is in the first state.

[0133] In actual execution, the arithmetic unit 140 detects that the voltage across the current sensing resistor R8 at the battery terminal is abnormal, and the output signal VBUS RCSDET at the second output terminal of the arithmetic unit 140 is in the first state.

[0134] According to the protection circuit of the charging / discharging chip provided in the embodiments of this application, the arithmetic unit detects the short-circuit failure of either the VBUS current sensing resistor or the VBAT current sensing resistor, and can automatically identify the short-circuited device in a timely manner. This allows for timely shutdown of the driving of the switching transistor in the buck-boost circuit, protecting external charging / discharging devices and other peripheral devices of the charging / discharging chip, thus providing enhanced safety.

[0135] In some embodiments, when the target parameter is greater than a first threshold, the output signal of the first output terminal of the arithmetic unit 140 is in a first state; when the target parameter is less than a second threshold, the output signal of the second output terminal of the arithmetic unit 140 is in a first state; the second threshold is less than the first threshold; the target parameter is the ratio of the first product to the second product; the first product is the product of the voltage at the positive input terminal of the VBUS current sensing resistor R7 and the current of the VBUS current sensing resistor R7; the second product is the product of the voltage at the positive input terminal of the battery current sensing resistor R8 and the current of the battery current sensing resistor R8.

[0136] In actual implementation, the arithmetic unit 140 may include a multiplication calculator and a comparator. The multiplication calculator is used to perform multiplication calculations, and the comparator is used to compare the calculator results. The specific structure of the arithmetic unit 140 is not limited in this embodiment.

[0137] In actual implementation, the single-point failure protection function of the current sensing resistor can be realized through the current sampling module 130 and the arithmetic unit.

[0138] In some embodiments, the CSP_VBUS and CSN_VBUS pins are connected to the positive and negative terminals of the current sensing resistor R7 at the VBUS terminal, respectively, and the CSP_VBAT and CSN_VBAT pins are connected to the positive and negative terminals of the current sensing resistor R8 at the VBAT terminal, respectively. Whenever a single-point failure detection of the high-side switch is completed, if no abnormality is detected, its output will control the closing of S1 and S2 of the current sampling module 130, and the state gate and core of the state controller 120 will synchronously provide a reference voltage VREF and a clock signal CLK to the current sampling module 130, causing the current sampling module 130 to enter a ready state.

[0139] After the buck-boost circuit starts working, the charging / discharging current flows through the current sensing resistors at the VBUS and VBAT terminals. According to Ohm's law V = R * I, a voltage difference is generated between the positive and negative terminals when current flows through the current sensing resistor. Therefore, the voltage difference obtained by subtracting CSN_VBUS from CSP_VBUS, divided by the resistance of current sensing resistor R7, is the charging / discharging current at the VBUS terminal. Similarly, the voltage difference obtained by subtracting CSN_VBAT from CSP_VBAT, divided by the resistance of current sensing resistor R8, is the charging / discharging current at the VBAT terminal. When the MUX receives the voltages from the CSP_VBUS, CSN_VBUS, CSP_VBAT, and CSN_VBAT pins, it performs time-division multiplexing and division on each, and outputs their respective currents to the buffer. The voltages from the CSP_VBUS and CSP_VBAT pins are also output to the buffer. After the analog signal is filtered by the buffer, the analog-to-digital converter will receive: the current IBU from the current sensing resistor R7 at the VBUS terminal, the current IBU from the current sensing resistor R8 at the VBAT terminal, the voltage at the CSP_VBUS pin, and the voltage at the CSN_VBUS pin. The analog-to-digital converter can then convert these analog signals into approximate digital values ​​and store them in a 12-bit data register.

[0140] The arithmetic logic unit 140 can continuously read data from the data register and continuously multiply the obtained CSP_VBUS and IBUS, and multiply CSP_VBAT and IBAT. Then, it divides the result of the multiplication at the VBUS end by the result of the multiplication at the VBAT end. The formula is: DET = (CSP_VBUS * IBUS) / (CSP_VBAT * IBAT).

[0141] When the current sensing resistor at the VBAT terminal is short-circuited, IBAT will be close to 0, and the final DET result will be greater than 1. Therefore, when the DET result is greater than 1, the digital arithmetic unit pulls the VBAT RCSDET signal high and outputs it to the state controller 120. When the current sensing resistor at the VBUS terminal is short-circuited, IBUS will be close to 0, and the final DET result will be close to 0. Therefore, when the DET result is < 0.2, the arithmetic unit 140 pulls the VBUS RCSDET signal high and outputs it to the state controller.

[0142] When the status controller detects that any of the abnormal signals VBUS RCSDET and VBAT RCSDET is high, the driver pulls HD1, HD2, LD1, and LD2 low to shut down the charging and discharging chip and prevent charging and discharging.

[0143] It should be noted that DET is the target parameter. 1 and 0.2 are exemplary descriptions of the first threshold and the second threshold, respectively. This application does not limit the specific values ​​of the first threshold and the second threshold.

[0144] According to the protection circuit of the charging / discharging chip provided in the embodiments of this application, the target parameters are obtained by the arithmetic unit. Based on the relationship between the target parameters and the first threshold and the second threshold, the short-circuit failure of any device among the VBUS current sensing resistor and the VBAT current sensing resistor is detected. This can more accurately identify the device that has short-circuited, thereby enabling timely shutdown of the driving of the switching transistor in the buck-boost circuit. This can protect the external charging / discharging equipment and other devices around the charging / discharging chip, thus providing stronger safety.

[0145] In some embodiments, reference Figure 6 The state controller 120 includes a first OR gate 610, a second OR gate 620, a third OR gate 630, and a driver 640. The input terminal of the first OR gate 610 is connected to the output terminal of the first detection unit 111 and the output terminal of the second detection unit 112, respectively. The input terminal of the second OR gate 620 is connected to the first output terminal and the second output terminal of the arithmetic unit 140, respectively. The input terminal of the third OR gate 630 is connected to the output terminal of the first OR gate 610 and the output terminal of the second OR gate 620, respectively. The output terminal of the third OR gate 630 is connected to the driver 640. The driver 640 is connected to the buck-side high-side switch driver pin HD1, the boost-side high-side switch driver pin HD2, the buck-side low-side switch driver pin LD1, and the boost-side low-side switch driver pin LD2 of the buck-boost circuit, respectively.

[0146] In actual execution, the state controller 120 can be connected to external VBUS RCS detection signals (VBUS RCS DET), VBAT RCS detection signals (VBAT RCSDET), SW1 detection signals (SW1 DET), and SW2 detection signals (SW2 DET). The VBUS RCS and VBAT RCS detection signals are connected to an OR gate (specifically, a second OR gate 620), and the SW1 and SW2 detection signals are connected to another OR gate (specifically, a first OR gate 610). The results of these two OR gates are then connected to another OR gate (specifically, a third OR gate 630). The output of the third OR gate 630 (which can be represented as SPOTDET) is connected to the driver 640, the state machine, and the core 650. The driver 640 can be connected to external HD2, HD1, LD2, and LD1 pins, and is also connected to the state machine and the core 650.

[0147] When the output signal at the output terminal of the third OR gate 630 is in the first state, the driver 640 pulls low the buck-side high-side switch driver pin HD1, the boost-side high-side switch driver pin HD2, the buck-side low-side switch driver pin LD1, and the boost-side low-side switch driver pin LD2.

[0148] In actual execution, when any one of the VBUS RCS detection signal (VBUS RCSDET), VBAT RCS detection signal (VBATRCSDET), SW1 detection signal (SW1 DET), and SW2 detection signal (SW2 DET) is in the first state, SPOT DET is in the first state, and the driver 640 pulls HD1, HD2, LD1, and LD2 low, thereby shutting down the charging and discharging chip and prohibiting charging and discharging.

[0149] According to the protection circuit of the charging / discharging chip provided in the embodiments of this application, the VBUS RCS detection signal, VBAT RCS detection signal, SW1 detection signal and SW2 detection signal are integrated by three OR gates. The device that has short-circuited can be identified in a timely and automatic manner, thereby turning off the drive of the switching transistor in the buck-boost circuit in a timely manner. This can protect the external charging / discharging equipment and other devices around the charging / discharging chip, and has stronger safety.

[0150] This application also provides a charge / discharge chip 700.

[0151] like Figure 7 As shown, the charge / discharge chip 700 includes the protection circuit 710 of the charge / discharge chip in the above embodiment, and can achieve the same effect. To avoid repetition, it will not be described again.

[0152] It is understandable that the charge / discharge chip 700 may also include, for example: Figure 2 The step-up / step-down circuit 720 is shown.

[0153] According to the charging and discharging chip provided in the embodiments of this application, when a single-point failure occurs, the internal circuit can identify the current failure point and perform abnormal protection, so as to protect the chip, other external devices and equipment.

[0154] This application also provides an electronic device.

[0155] like Figure 8 As shown, the electronic device 800 includes the charging and discharging chip 700 described above.

[0156] The electronic device 30 can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. The embodiments of this application do not specifically limit it.

[0157] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0158] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0159] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A protection circuit for a charging and discharging chip, characterized in that, The charging and discharging chip includes a buck-boost circuit based on four switching transistors; the protection circuit includes a detection module and a status controller. The detection module is connected to the state controller; the detection module is also connected to the first and second switching nodes of the buck-boost circuit. The state controller is connected to the high-side switch driver pin on the buck side, the high-side switch driver pin on the boost side, the low-side switch driver pin on the buck side, and the low-side switch driver pin on the boost side of the buck-boost circuit, respectively. When the voltage of the first switching node is greater than the first target voltage and / or the voltage of the second switching node is greater than the second target voltage, the detection module outputs a first state signal to the state controller. When the state controller receives a signal indicating the first state, it shuts down the drive of the switching transistor in the buck-boost circuit.

2. The protection circuit for the charge / discharge chip according to claim 1, characterized in that, The detection module includes a first detection unit and a second detection unit; The input terminal of the first detection unit is connected to the first switch node; the output terminal of the first detection unit is connected to the first input terminal of the state controller; when the voltage of the first switch node is greater than the first target voltage, the output signal of the output terminal of the first detection unit is the first state; when the voltage of the first switch node is less than or equal to the first target voltage, the output signal of the output terminal of the first detection unit is the second state. The input terminal of the second detection unit is connected to the second switch node; the output terminal of the second detection unit is connected to the second input terminal of the state controller. When the voltage of the second switching node is greater than the second target voltage, the output signal of the output terminal of the second detection unit is the first state; When the voltage of the second switching node is less than or equal to the second target voltage, the output signal of the output terminal of the second detection unit is the second state.

3. The protection circuit for the charge / discharge chip according to claim 2, characterized in that, Also includes: Current sampling module and arithmetic unit; The current sampling module is connected to the arithmetic unit; The arithmetic unit is connected to the state controller; The current sampling module is connected to both ends of the VBUS current sensing resistor and the battery current sensing resistor of the buck-boost circuit, respectively, to obtain the voltage across the VBUS current sensing resistor and the voltage across the battery current sensing resistor. When the voltage across the current sensing resistor at the VBUS terminal is abnormal or the voltage across the current sensing resistor at the battery terminal is abnormal, the signal output by the arithmetic unit to the state controller is the first state.

4. The protection circuit for the charge / discharge chip according to claim 3, characterized in that, The current sampling module includes a first switching unit, a second switching unit, and a current sampling unit; The first switching unit connects the current sampling unit to both ends of the VBUS terminal current sensing resistor; The second switching unit connects the current sampling unit to both ends of the current sensing resistor at the battery terminal; The output terminal of the first detection unit is connected to the control terminal of the first switch unit and the control terminal of the second switch unit; the output terminal of the second detection unit is connected to the control terminal of the first switch unit and the control terminal of the second switch unit. When the output signal at the output terminal of the first detection unit is in the first state, the first switching unit and the second switching unit are in the off state. When the output signal at the output terminal of the second detection unit is in the first state, the first switch unit and the second switch unit are in the open state; when the output signal at the output terminal of the first detection unit and the output signal at the output terminal of the second detection unit are in the second state, the first switch unit and the second switch unit are in the closed state.

5. The protection circuit for the charge / discharge chip according to claim 4, characterized in that, The current sampling module also includes an OR gate; The output terminals of the first detection unit and the second detection unit are respectively connected to one input terminal of the NOR gate; the output terminal of the NOR gate is respectively connected to the control terminal of the first switching unit and the control terminal of the second switching unit.

6. The protection circuit for the charge / discharge chip according to any one of claims 3 to 5, characterized in that, The first output terminal of the arithmetic unit is connected to the third input terminal of the state controller; the second output terminal of the arithmetic unit is connected to the fourth input terminal of the state controller. When the voltage across the current sensing resistor at the VBUS terminal is abnormal, the output signal at the first output terminal of the arithmetic unit is in the first state. When the voltage across the current sensing resistor at the battery terminal is abnormal, the output signal at the second output terminal of the arithmetic unit is in the first state.

7. The protection circuit of the charging and discharging chip according to claim 6, wherein when the target parameter is greater than the first threshold, the output signal of the first output terminal of the arithmetic unit is the first state; When the target parameter is less than the second threshold, the output signal of the second output terminal of the arithmetic unit is in the first state; The second threshold is less than the first threshold; The target parameter is the ratio of the first product to the second product; The first product is the product of the voltage at the positive input terminal of the VBUS current sensing resistor and the current of the VBUS current sensing resistor; the second product is the product of the voltage at the positive input terminal of the battery current sensing resistor and the current of the battery current sensing resistor.

8. The protection circuit for the charge / discharge chip according to claim 6, characterized in that, The state controller includes a first OR gate, a second OR gate, a third OR gate, and a driver; The input terminals of the first OR gate are respectively connected to the output terminals of the first detection unit and the second detection unit; The input terminals of the second OR gate are respectively connected to the first output terminal and the second output terminal of the arithmetic unit; The input terminal of the third OR gate is connected to the output terminal of the first OR gate and the output terminal of the second OR gate, respectively. The output of the third OR gate is connected to the driver; the driver is connected to the buck-side high-side switch driver pin, the boost-side high-side switch driver pin, the buck-side low-side switch driver pin, and the boost-side low-side switch driver pin of the buck-boost circuit, respectively. When the output signal at the output terminal of the third OR gate is in the first state, the driver pulls down the high-side switch driver pin on the buck side, the high-side switch driver pin on the boost side, the low-side switch driver pin on the buck side, and the low-side switch driver pin on the boost side.

9. A charge / discharge chip, characterized in that, The protection circuit for the charge / discharge chip as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the charge / discharge chip as described in claim 9.

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