Photomask and semiconductor packaging structure
By setting chip and pad patterns on both sides of the dicing area of the photomask, repeating units are formed and empty space is left, which solves the problem of insufficient usable space in semiconductor device packaging and realizes larger space for auxiliary pattern setting and cost-effectiveness.
Patent Information
- Application Number
- CN202422727550.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-11-08
AI Technical Summary
In the packaging process of semiconductor devices, as device size shrinks, the available space for setting auxiliary patterns on the dicing area gradually decreases, leading to increased production costs or limited applicability.
Design a photomask structure by setting chip patterns and pad patterns on both sides of the dicing area to form repeating units, leaving empty space between adjacent units to increase the usable space, and setting auxiliary function patterns such as test keys and feature marks.
Without reducing chip density, the available space in the dicing area is significantly increased, the space for setting auxiliary patterns is improved, and production costs are reduced.
Smart Images
Figure CN223501292U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and in particular to a photomask and a semiconductor packaging structure. Background Technology
[0002] In semiconductor device manufacturing, a common process involves packaging multiple dies using lead frames. Currently, some products require conductive trim pads for testing the electrical properties of the chips. During the packaging process, a photomask is typically used, and auxiliary patterns such as test keys, marks, and critical dimension bars (CD bars) need to be set on the dicing area of the photomask. The presence of conductive trim pads also occupies some space in the dicing area, reducing the space available for setting auxiliary patterns. As device sizes continue to shrink, the usable space in the dicing area for setting auxiliary patterns is gradually decreasing. Utility Model Content
[0003] Based on this, and in view of the problems mentioned above, it is necessary to provide a photomask that can increase the usable space on the cutting channel area.
[0004] According to some embodiments of the present disclosure, a photomask is provided, comprising: a frame region, a first chip pattern, and a first pad pattern, wherein the frame region includes a first dicing region extending along a first direction and a second dicing region extending along a second direction intersecting the first direction;
[0005] The photomask further includes a second chip pattern and a second pad pattern, wherein the first chip pattern and the second chip pattern are respectively disposed on both sides of the first dicing area in the second direction, and the first pad pattern and the second pad pattern are disposed on the first dicing area; and / or,
[0006] The photomask also includes a third chip pattern and a third pad pattern. The first chip pattern and the third chip pattern are respectively disposed on both sides of the second dicing area in the first direction. The first pad pattern is disposed on the first dicing area, and the third pad pattern is disposed on the second dicing area.
[0007] In some embodiments of this disclosure, the first chip pattern, the second chip pattern, the first pad pattern, and the second pad pattern constitute a first repeating unit. The photomask is provided with a plurality of the first repeating units arranged side by side along the second direction, and adjacent first repeating units are separated by the first dicing zone.
[0008] In some embodiments of this disclosure, the first chip pattern, the third chip pattern, the first pad pattern, and the third pad pattern constitute a second repeating unit. The photomask is provided with a plurality of second repeating units arranged side by side along the first direction, and adjacent second repeating units are separated by a second dicing zone.
[0009] In some embodiments of this disclosure, the photomask further includes an auxiliary functional pattern selected from at least one of test keys, feature identifiers, and critical dimension bars, the auxiliary functional pattern being disposed between two adjacent first pad patterns in the first direction.
[0010] In some embodiments of this disclosure, the first pad pattern is adjacent to the first chip pattern, the second pad pattern is adjacent to the second chip pattern, and the third pad pattern is adjacent to the third chip pattern.
[0011] In some embodiments of this disclosure, the shape of the overall region formed by the first chip pattern and the first pad pattern is identical to the shape of the overall region formed by the second chip pattern and the second pad pattern; and / or,
[0012] The shape of the overall area formed by the first chip pattern and the first pad pattern is identical to the shape of the overall area formed by the third chip pattern and the third pad pattern, and both the first chip pattern and the third chip pattern are square.
[0013] Secondly, this disclosure also provides a semiconductor packaging structure, including a lead frame, a first chip, and a first conductive pad, wherein the first conductive pad is electrically connected to the first chip, and the lead frame has a first dicing channel extending along a first direction and a second dicing channel extending along a second direction intersecting the first direction, wherein...
[0014] The semiconductor package structure further includes a second chip and a second conductive pad disposed on the lead frame, the second conductive pad being electrically connected to the second chip, the second chip being disposed on the side of the first dicing track away from the first chip, and both the first conductive pad and the second conductive pad being disposed on the first dicing track; and / or,
[0015] The semiconductor package structure further includes a third chip and a third conductive pad. The third conductive pad is electrically connected to the third chip. The third chip is disposed on the side of the second dicing track away from the first chip, and the first conductive pad is disposed on the first dicing track, while the third conductive pad is disposed on the second dicing track.
[0016] In some embodiments of this disclosure, the overall structure formed by the first chip and the first conductive pad is the same as the overall structure formed by the second chip and the second conductive pad; and / or,
[0017] The overall structure formed by the first chip and the first conductive pad is the same as the overall structure formed by the third chip and the third conductive pad, and both the first chip and the third chip are square.
[0018] In some embodiments of this disclosure, the first conductive pad is close to the first chip, the second conductive pad is close to the second chip, and the third conductive pad is close to the third chip.
[0019] In at least some of the above embodiments, a second chip pattern and a second pad pattern are disposed in the photomask. Both the first pad pattern and the second pad pattern are located in a first dicing channel between the first chip pattern and the second chip pattern. Therefore, the areas of the first chip pattern far from the second chip pattern and the areas of the second chip pattern far from the first chip pattern are vacant, serving as usable space, and this usable space is significantly larger than the usable space in conventional technologies. In these at least some of the above embodiments, the first pad pattern is located on a first dicing channel area adjacent to the first chip pattern, and the third pad pattern is located on a second dicing channel area adjacent to the third chip pattern. This reduces the number of pad areas required on the first dicing channel area, and correspondingly, the usable space on the first dicing channel area is also significantly larger than the usable space in conventional technologies. Therefore, the photomask provided by this disclosure can increase the usable space on the dicing channel area. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of a traditional photomask pattern structure;
[0021] Figure 2 This is a schematic diagram of the structure of a photomask according to an embodiment of the present disclosure;
[0022] Figure 3 This is a schematic diagram of the structure of a photomask according to another embodiment of the present disclosure;
[0023] Figure 4 This is a schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure;
[0024] Figure 5 This is a schematic diagram of a semiconductor packaging structure according to another embodiment of the present disclosure.
[0025] The meanings of the reference numerals in the attached figures are as follows:
[0026] 11. Chip area; 12. Pad area; 100. Frame area; 101. First dicing area; 102. Second dicing area; 111. First chip pattern; 112. First pad pattern; 121. Second chip pattern; 122. Second pad pattern; 131. Third chip pattern; 132. Third pad pattern; 200. Lead frame; 201. First dicing; 202. Second dicing; 211. First chip; 212. First conductive pad; 221. Second chip; 222. Second conductive pad; 231. Third chip; 232. Third conductive pad. Detailed Implementation
[0027] To facilitate understanding of this utility model, a more comprehensive description of it will be provided below in conjunction with embodiments and effect diagrams. The embodiments provide preferred embodiments of this utility model. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this utility model.
[0028] It should be noted that when one component is referred to as being "fixed" to another component, it can be directly fixed to the other component or fixed to the other component through an intermediate component. When one component is referred to as being "connected" to another component, it can be directly connected to the other component, or there can be an intermediate component between the two components. Furthermore, in the description of this utility model, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "attached" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integrated connection. For example, it can be a mechanical connection or an electrical connection. For example, it can be a direct connection or an indirect connection through an intermediate component, or it can be a connection within two components. It should be understood that those skilled in the art can interpret the specific meaning of the above terms according to the specific circumstances without causing ambiguity.
[0029] Unless otherwise specified, in the description of this utility model, terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," which indicate orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings of the utility model. They are only for the convenience and simplification of the description of the utility model and to help the reader understand it in conjunction with the accompanying drawings, and are not intended to limit or imply a specific orientation that the device or element referred to must have. Therefore, they should not be construed as limitations on this utility model.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the implementation of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. "More" herein includes combinations of two or more items.
[0031] Figure 1 This is a schematic diagram of a traditional photomask pattern structure. (Refer to...) Figure 1 As shown, the photomask includes multiple chip regions 11 and multiple pad regions 12. The multiple chip regions 11 are arranged in an array in the photomask, with dicing channels between the chip regions 11, and the pad regions 12 are located on the dicing channels. Furthermore, the multiple pad regions 12 correspond one-to-one with the multiple chip regions 11, with each pad region 12 adjacent to its corresponding chip region 11. The space between adjacent pad regions 12 is the usable space for auxiliary patterns, and this usable space gradually decreases as the device size gradually shrinks.
[0032] In this context, to set auxiliary patterns, some conventional techniques reduce the number of chips to maintain a larger dicing area size, but this leads to increased production costs. Other conventional techniques reduce the size of feature markers and adjust the orientation of test structures and critical dimension bars to ensure that the aforementioned patterns can be set in a smaller available space, but their applicability is relatively limited. Therefore, it is necessary to provide a photomask that can increase the usable space on the dicing area without reducing chip density.
[0033] Figure 2 This is a schematic diagram of the structure of a photomask disclosed herein. (Refer to...) Figure 2 As shown, the photomask includes a frame region 100, a first chip pattern 111, and a first pad pattern 112. The frame region 100 includes a first dicing region 101 extending along a first direction and a second dicing region 102 extending along a second direction intersecting the first direction. In this embodiment, the photomask also includes a second chip pattern 121 and a second pad pattern 122. The first chip pattern 111 and the second chip pattern 121 are respectively disposed on both sides of the first dicing region 101 in the second direction, and the first pad pattern 112 and the second pad pattern 122 are disposed on the first dicing region 101.
[0034] It is understood that in the structural design of this photomask, the first chip pattern 111 and the second chip pattern 121 correspond to the positions of the chips in the corresponding devices to be fabricated, and the first dicing region 101 and the second dicing region 102 correspond to the positions of the dicing channels in the corresponding devices to be fabricated. The first dicing region 101 and the second dicing region 102 can be areas outside the first chip pattern 111 and the second chip pattern 121.
[0035] Reference Figure 2 As shown, for ease of understanding, Figure 2 The direction indicated by the x-axis marked in the figure is the first direction. Figure 2 The direction indicated by the y-axis is the second direction. In this embodiment, the first direction and the second direction are perpendicular to each other.
[0036] In this embodiment, the first pad pattern 112 and the second pad pattern 122 are both located in the first dicing zone 101 between the first chip pattern 111 and the second chip pattern 121. The area of the first chip pattern 111 away from the second chip pattern 121 and the area of the second chip pattern 121 away from the first chip pattern 111 are vacant and can be used as usable space. This usable space is significantly larger than the usable space in conventional technology.
[0037] Reference Figure 2 As shown, as some examples of this embodiment, the first pad pattern 112 may be set close to the first chip pattern 111, and the second pad pattern 122 may be set close to the second chip pattern 121.
[0038] Reference Figure 2 As shown, as examples of this embodiment, the first chip pattern 111, the second chip pattern 121, the first pad pattern 112, and the second pad pattern 122 constitute a first repeating unit. The photomask has multiple first repeating units arranged side-by-side along a second direction, with adjacent first repeating units separated by a first dicing zone 101. By arranging multiple first repeating units in the second direction, multiple vacant first dicing zones 101 are correspondingly formed, further expanding the usable space on the photomask.
[0039] It is understood that the first cleaving area 101 located between two adjacent first repeating units does not have a first pad pattern 112 and a second pad pattern 122, thus having a large empty space. As some examples of this embodiment, the photomask also includes an auxiliary function pattern, which is selected from at least one of test keys, feature identifiers, and key dimension bars, and the auxiliary function pattern is disposed on the first cleaving area 101 located between adjacent first repeating units.
[0040] Reference Figure 2As shown, as some examples of this embodiment, a plurality of first repeating units arranged side by side along the second direction constitute a column of first repeating units, and the photomask includes a plurality of columns of first repeating units arranged side by side along the first direction. Further, adjacent columns of first repeating units are spaced apart by a second cutting channel region 102. It can be understood that the plurality of first repeating units can be arranged in an array.
[0041] Furthermore, as some examples of this embodiment, a plurality of first chip patterns 111 and a plurality of second chip patterns 121 are alternately arranged sequentially along a second direction. For example, in Figure 2 In the embodiment shown, a first chip pattern 111, a second chip pattern 121, and a second chip pattern 121 are arranged sequentially from top to bottom.
[0042] As examples of this embodiment, the shape of the overall region formed by the first chip pattern 111 and the first pad pattern 112 can be congruent to the shape of the overall region formed by the second chip pattern 121 and the second pad pattern 122. It is understood that the orientation of the overall region formed by the first chip pattern 111 and the first pad pattern 112 can be different from the orientation of the overall region formed by the second chip pattern 121 and the second pad pattern 122. In this case, the overall region formed by the first chip pattern 111 and the first pad pattern 112 can be rotated to form the same shape as the overall region formed by the second chip pattern 121 and the second pad pattern 122. Figure 2 As shown, the shape of the overall area composed of the first chip pattern 111 and the first pad pattern 112 can be rotated 180° to form the same shape as the overall area composed of the second chip pattern 121 and the second pad pattern 122.
[0043] Typically, the relative position between conductive pads and the chip is fixed. Figure 2 In the embodiment, the overall area formed by the first chip pattern 111 and the first pad pattern 112 is identical to the overall area formed by the second chip pattern 121 and the second pad pattern 122. In the actual manufacturing process, the first chip pattern 111 and the second chip pattern 121 can correspond to chips with the same structure, and the relative positional relationship between each chip and the connected conductive pad is also the same.
[0044] Reference Figure 2 As shown, as some examples of this embodiment, the first chip pattern 111 and the second chip pattern 121 have the same shape. For example, the shapes of the first chip pattern 111 and the second chip pattern 121 can be square or rectangular. As some examples of this embodiment, the first pad pattern 112 and the second pad pattern 122 also have the same shape. It can be understood that, in the case of... Figure 2In the illustrated embodiment, the main difference between the first pad pattern 112 and the second pad pattern 122 lies in their specific placement positions.
[0045] Figure 3 This is a schematic diagram of the structure of a photomask disclosed herein. (Refer to...) Figure 3 As shown, the photomask includes a frame region 100, a first chip pattern 111, and a first pad pattern 112. The frame region 100 includes a first dicing region 101 extending along a first direction and a second dicing region 102 extending along a second direction intersecting the first direction. In this embodiment, the photomask also includes a third chip pattern 131 and a third pad pattern 132. The first chip pattern 111 and the third chip pattern 131 are respectively disposed on both sides of the second dicing region 102 in the first direction. The first pad pattern 112 is disposed on the first dicing region 101, and the third pad pattern 132 is disposed on the second dicing region 102.
[0046] Reference Figure 3 As shown, in this embodiment, the first chip pattern 111 is provided with first dicing zones 101 on both sides in the second direction, and the first pad pattern 112 can be provided in either of the two first dicing zones 101.
[0047] Reference Figure 3 As shown, in this embodiment, the third chip pattern 131 also has second dicing regions 102 on both sides in the first direction, and the third pad pattern 132 can be disposed in either of these two second dicing regions 102. For example... Figure 3 In this embodiment, the third pad pattern 132 is disposed in the second dicing region 102 on the side of the third chip pattern 131 away from the first chip pattern 111. However, in other embodiments, the third pad pattern 132 may also be disposed in the second dicing region 102 on the side of the third chip pattern 131 closer to the first chip pattern 111.
[0048] Reference Figure 3 As shown, for ease of understanding, Figure 3 The direction indicated by the x-axis marked in the figure is the first direction. Figure 3 The direction indicated by the y-axis is the second direction. In this embodiment, the first direction and the second direction are perpendicular to each other.
[0049] In this embodiment, the first pad pattern 112 is located on the first dicing area 101 adjacent to the first chip pattern 111, and the third pad pattern 132 is located on the second dicing area 102 adjacent to the third chip pattern 131. Therefore, the number of pad areas required on the first dicing area 101 is reduced, and correspondingly, the usable space is increased.
[0050] Reference Figure 3 As shown, as some examples of this embodiment, the first pad pattern 112 may be set close to the first chip pattern 111, and the third pad pattern 132 may be set close to the third chip pattern 131.
[0051] Reference Figure 3 As shown, as examples of this embodiment, the first chip pattern 111, the third chip pattern 131, the first pad pattern 112, and the third pad pattern 132 constitute a second repeating unit. The photomask has multiple second repeating units arranged side-by-side along a first direction, with adjacent second repeating units separated by a second dicing zone 102. Arranging multiple second repeating units in the first direction further expands the usable space on the photomask.
[0052] As some examples of this embodiment, the photomask also includes an auxiliary function pattern selected from at least one of test keys, feature identifiers, and critical dimension bars, and the auxiliary function pattern is disposed between two adjacent first pad patterns 112 in the first direction.
[0053] Reference Figure 3 As shown, as some examples of this embodiment, a plurality of second repeating units arranged side by side along a first direction constitute a row of second repeating units, and the photomask includes multiple rows of second repeating units arranged side by side along the first direction. Further, adjacent rows of second repeating units are spaced apart by a first cutting channel region 101. It can be understood that the plurality of second repeating units can be arranged in an array.
[0054] Furthermore, as some examples of this embodiment, a plurality of first chip patterns 111 and a plurality of third chip patterns 131 are alternately arranged sequentially along a first direction. For example, in Figure 3 In the embodiment shown, a first chip pattern 111, a third chip pattern 131, and a third chip pattern 131 are arranged sequentially from left to right.
[0055] As examples of this embodiment, the shape of the overall region formed by the first chip pattern 111 and the first pad pattern 112 can be identical to the shape of the overall region formed by the third chip pattern 131 and the third pad pattern 132. It is understood that the orientation of the overall region formed by the first chip pattern 111 and the first pad pattern 112 can be different from the orientation of the overall region formed by the third chip pattern 131 and the third pad pattern 132. In this case, the overall region formed by the first chip pattern 111 and the first pad pattern 112 can be rotated to form the same shape as the overall region formed by the third chip pattern 131 and the third pad pattern 132. Figure 3As shown, the shape of the overall area composed of the first chip pattern 111 and the first pad pattern 112 can be rotated by 90° to form the same shape as the overall area composed of the second chip pattern 121 and the second pad pattern 122.
[0056] Typically, the relative position between conductive pads and the chip is fixed. Figure 3 In the embodiment, the overall area formed by the first chip pattern 111 and the first pad pattern 112 is identical to the overall area formed by the third chip pattern 131 and the third pad pattern 132. In the actual process, the first chip pattern 111 and the third chip pattern 131 can correspond to chips with the same structure, and the relative positional relationship between each chip and the connected conductive pad is also the same.
[0057] Reference Figure 3 As shown, as some examples of this embodiment, the first chip pattern 111 and the third chip pattern 131 have the same shape, and both the first chip pattern 111 and the third chip pattern 131 are square. As some examples of this embodiment, the first pad pattern 112 and the third pad pattern 132 also have the same shape. It can be understood that, in the case of... Figure 3 In the illustrated embodiment, the main difference between the first pad pattern 112 and the third pad pattern 132 lies in their specific placement positions.
[0058] Understandable, in such cases Figure 2 and Figure 3 In the illustrated embodiment, the arrangement of the second pad pattern 122 and the third pad pattern 132 is shown respectively. In other embodiments of this disclosure, the second chip pattern 121, the second pad pattern 122, the third chip pattern 131, and the third pad pattern 132 can also be simultaneously arranged in the photomask. In this case, the second chip pattern 121 and the second pad pattern 122 are located on one side of the first chip pattern 111 in the first direction, and the third chip pattern 131 and the third pad pattern 132 are located on one side of the first chip pattern 111 in the second direction.
[0059] Furthermore, this disclosure also provides a semiconductor packaging structure that corresponds to the pattern on the photomask in the embodiments of this disclosure and can be fabricated based on the photomask in the embodiments of this disclosure.
[0060] Figure 4This is an embodiment of a semiconductor packaging structure disclosed herein. The semiconductor packaging structure includes a lead frame 200, a first chip 211, and a first conductive pad 212. The first conductive pad 212 is electrically connected to the first chip 211. The lead frame 200 has a first cleaving channel 201 extending along a first direction and a second cleaving channel 202 extending along a second direction intersecting the first direction. Further, referring to… Figure 4 As shown, the semiconductor packaging structure further includes a second chip 221 and a second conductive pad 222 disposed on the lead frame 200. The second conductive pad 222 is electrically connected to the second chip 221. The second chip 221 is disposed on the side of the first dicing channel 201 away from the first chip 211, and both the first conductive pad 212 and the second conductive pad 222 are disposed on the first dicing channel 201.
[0061] Reference Figure 4 As shown, as some examples of this embodiment, the first chip 211, the second chip 221, the first conductive pad 212 and the second conductive pad 222 constitute a first repeating component. The semiconductor package structure may include a plurality of the first repeating components arranged side by side along the second direction, with adjacent first repeating components spaced apart by the first dicing channel 201.
[0062] Reference Figure 4 As shown, as some examples of this embodiment, a plurality of first repeating components arranged side by side along the second direction constitute a column of first repeating components, and the semiconductor package structure includes a plurality of columns of first repeating components arranged side by side along the first direction.
[0063] Reference Figure 4 As shown, as examples of this embodiment, the overall structure composed of the first chip 211 and the first conductive pad 212 is the same as the overall structure composed of the second chip 221 and the second conductive pad 222. It is understood that the structures of the first chip 211 and the second chip 221 should be identical, the structures of the first conductive pad 212 and the second conductive pad 222 should also be identical, and the connection position between the first chip 211 and the first conductive pad 212 should correspond to the connection position between the second chip 221 and the second conductive pad 222. However, their specific orientations can be different, and this orientation can be set according to the placement positions of the first conductive pad 212 and the second conductive pad 222.
[0064] For example, Figure 4 A dashed triangle is used to distinguish the first chip 211 and the second chip 221. Figure 4 A hollow triangle is used to distinguish the first conductive pad 212 and the second conductive pad 222. In such a way... Figure 4In the diagram, the first chip 211 is represented by a dashed triangle pointing upwards, and the second chip 221 is represented by a dashed triangle pointing downwards. Correspondingly, the first conductive pad 212 is represented by a hollow triangle pointing upwards, and the second conductive pad 222 is represented by a hollow triangle pointing downwards. It can be understood that the first chip 211 and the second chip 221 have opposite orientations; that is, the first chip 211, after being rotated 180°, can have the orientation of the second chip 221. Similarly, the first conductive pad 212 and the second conductive pad 222 also have opposite orientations. In this case, the overall structure formed by the first chip 211 and the first conductive pad 212 is the same as the overall structure formed by the second chip 221 and the second conductive pad 222.
[0065] Reference Figure 4 As shown, the first conductive pad 212 can be set close to the first chip 211, and the second conductive pad 222 can be set close to the second chip 221.
[0066] Figure 5 This is an embodiment of a semiconductor packaging structure disclosed herein. The semiconductor packaging structure includes a lead frame 200, a first chip 211, and a first conductive pad 212. The first conductive pad 212 is electrically connected to the first chip 211. The lead frame 200 has a first cleaving channel 201 extending along a first direction and a second cleaving channel 202 extending along a second direction intersecting the first direction. Further, referring to… Figure 4 As shown, the semiconductor structure also includes a third chip 231 and a third conductive pad 232. The third conductive pad 232 is electrically connected to the third chip 231. The third chip 231 is disposed on the side of the second dicing channel 202 away from the first chip 211, and the first conductive pad 212 is disposed on the first dicing channel 201, while the third conductive pad 232 is disposed on the second dicing channel 202.
[0067] Reference Figure 5 As shown, as some examples of this embodiment, the first chip 211, the third chip 231, the first conductive pad 212 and the third conductive pad 232 constitute a second repeating component. The semiconductor package structure includes a plurality of second repeating components arranged side by side along the first direction, with adjacent second repeating components spaced apart by the second dicing 202.
[0068] Reference Figure 5 As shown, as some examples of this embodiment, a plurality of second repeating components arranged side by side along the first direction constitute a row of second repeating components, and the semiconductor package structure includes a plurality of rows of second repeating components arranged side by side along the second direction.
[0069] Reference Figure 5 As shown, as examples of this embodiment, the overall structure composed of the first chip 211 and the first conductive pad 212 is the same as the overall structure composed of the third chip 231 and the third conductive pad 232. It is understood that the structures of the first chip 211 and the third chip 231 should be identical, the structures of the first conductive pad 212 and the third conductive pad 232 should also be identical, and the connection positions between the first chip 211 and the first conductive pad 212 should correspond to the connection positions between the third chip 231 and the third conductive pad 232. However, their specific orientations can be different, and these orientations can be set according to the corresponding positions of the first conductive pad 212 and the second conductive pad 222.
[0070] For example, Figure 5 A dashed triangle is used to distinguish the first chip 211 from the third chip 231. Figure 5 A hollow triangle is used to distinguish the first conductive pad 212 and the third conductive pad 232. In such a way... Figure 5 In the diagram, the first chip 211 is represented by a dashed triangle pointing upwards, and the third chip 231 is represented by a dashed triangle pointing to the left. Correspondingly, the third conductive pad 232 is represented by a hollow triangle pointing upwards and a hollow triangle pointing to the left. It can be understood that the first chip 211 and the third chip 231 are perpendicular, meaning that the first chip 211 can have the same orientation as the third chip 231 after being rotated 90° or 270°. The first conductive pad 212 and the third conductive pad 232 are also perpendicular. In this case, the overall structure formed by the first chip 211 and the first conductive pad 212 is the same as the overall structure formed by the third chip 231 and the third conductive pad 232.
[0071] Understandable, in such cases Figure 4 and Figure 5 In the illustrated embodiment, the arrangement of the second conductive pad 222 and the third conductive pad 232 is shown respectively. In other embodiments of this disclosure, the semiconductor package structure may also simultaneously include a second chip 221, a second conductive pad 222, a third chip 231, and a third conductive pad 232. In this case, the second chip 221 and the second conductive pad 222 are located on one side of the first chip 211 in a first direction, and the third chip 231 and the third conductive pad 232 are located on one side of the first chip 211 in a second direction.
[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0073] The above embodiments only illustrate several implementation methods of this utility model, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.
Claims
1. A photomask, characterized in that, include: The system comprises a frame region, a first chip pattern, and a first pad pattern. The frame region includes a first dicing region extending along a first direction and a second dicing region extending along a second direction intersecting the first direction. The photomask further includes a second chip pattern and a second pad pattern, wherein the first chip pattern and the second chip pattern are respectively disposed on both sides of the first dicing area in the second direction, and the first pad pattern and the second pad pattern are disposed on the first dicing area; and / or, The photomask also includes a third chip pattern and a third pad pattern. The first chip pattern and the third chip pattern are respectively disposed on both sides of the second dicing area in the first direction. The first pad pattern is disposed on the first dicing area, and the third pad pattern is disposed on the second dicing area.
2. The photomask according to claim 1, characterized in that, The first chip pattern, the second chip pattern, the first pad pattern, and the second pad pattern constitute a first repeating unit. The photomask is provided with a plurality of the first repeating units arranged side by side along the second direction, and adjacent first repeating units are separated by the first dicing zone.
3. The photomask according to claim 2, characterized in that, The photomask also includes an auxiliary function pattern selected from at least one of test keys, feature identifiers, and key dimension bars, and the auxiliary function pattern is disposed on the first cutting path located between adjacent first repeating units.
4. The photomask according to claim 1, characterized in that, The first chip pattern, the third chip pattern, the first pad pattern, and the third pad pattern constitute a second repeating unit. The photomask is provided with a plurality of second repeating units arranged side by side along the first direction, and adjacent second repeating units are separated by the second dicing zone.
5. The photomask according to claim 4, characterized in that, The photomask also includes an auxiliary function pattern, which is selected from at least one of test keys, feature identifiers, and critical dimension bars, and is disposed between two adjacent first pad patterns in the first direction.
6. The photomask according to any one of claims 1 to 5, characterized in that, The first pad pattern is adjacent to the first chip pattern, the second pad pattern is adjacent to the second chip pattern, and the third pad pattern is adjacent to the third chip pattern.
7. The photomask according to any one of claims 1 to 5, characterized in that, The shape of the entire region formed by the first chip pattern and the first pad pattern is identical to the shape of the entire region formed by the second chip pattern and the second pad pattern; and / or, The shape of the overall area formed by the first chip pattern and the first pad pattern is identical to the shape of the overall area formed by the third chip pattern and the third pad pattern, and both the first chip pattern and the third chip pattern are square.
8. A semiconductor packaging structure, characterized in that, include: The system comprises a lead frame, a first chip, and a first conductive pad, the first conductive pad being electrically connected to the first chip. The lead frame has a first cleaving extending along a first direction and a second cleaving extending along a second direction intersecting the first direction. The semiconductor package structure further includes a second chip and a second conductive pad disposed on the lead frame, the second conductive pad being electrically connected to the second chip, the second chip being disposed on the side of the first dicing track away from the first chip, and both the first conductive pad and the second conductive pad being disposed on the first dicing track; and / or, The semiconductor package structure further includes a third chip and a third conductive pad. The third conductive pad is electrically connected to the third chip. The third chip is disposed on the side of the second dicing track away from the first chip, and the first conductive pad is disposed on the first dicing track, while the third conductive pad is disposed on the second dicing track.
9. The semiconductor packaging structure according to claim 8, characterized in that, The overall structure formed by the first chip and the first conductive pad is the same as the overall structure formed by the second chip and the second conductive pad; and / or, The overall structure formed by the first chip and the first conductive pad is the same as the overall structure formed by the third chip and the third conductive pad, and both the first chip and the third chip are square.
10. The semiconductor packaging structure according to claim 8, characterized in that, The first conductive pad is close to the first chip, the second conductive pad is close to the second chip, and the third conductive pad is close to the third chip.