Hard reset control system and battery management system

Abstract

The utility model relates to a hard reset control system and a battery management system, the hard reset control system comprises at least one analog front-end chip and at least one hard reset control circuit, and the analog front-end chips and the hard reset control circuits are in one-to-one correspondence; a first end of the hard reset control circuit is used for receiving a control signal, a second end of the hard reset control circuit is connected with a power supply end of a corresponding analog front-end chip, and a third end of the hard reset control circuit is used for being connected with a battery pack; and the hard reset control circuit is used for disconnecting the connection between the power supply end of the analog front-end chip and the battery pack according to the control signal, so that the analog front-end chip is powered off and reset. By adopting the method and the device, the recovery efficiency of the AFE chip in the abnormal fault state can be improved.

Description

Technical Field

[0001] This application relates to the field of battery technology, specifically to a hard reset control system and a battery management system. Background Technology

[0002] In the battery management system of new energy vehicles, the Analog Front End (AFE) chip is the only integrated chip directly connected to the power battery, responsible for real-time monitoring of various electrical parameters of the battery. The battery pack voltage is maintained within a specific range to ensure that its voltage does not fall below the self-reset voltage threshold of the AFE chip, thereby ensuring that the AFE chip is always in an uninterrupted power supply state.

[0003] Normally, when the AFE chip malfunctions (such as a fault, register error, or state machine anomaly), the main controller sends a software reset command via a daisy-chain communication harness, prompting the AFE chip to perform a reset operation. However, if the AFE chip is in a "frozen" or "stuck" state, its communication will be abnormal, and conventional software reset methods will not be able to restore the AFE chip to a normal state. This leads to a malfunction of the battery management system, preventing it from functioning properly.

[0004] Currently, the solution to this type of malfunction is to disassemble the battery system and manually disconnect the battery pack from the AFE chip to reset the AFE chip. However, this method is inefficient, significantly impacts user experience, and is extremely costly to maintain. Utility Model Content

[0005] To address the aforementioned issues, this application provides a hard reset control system and a battery management system that can autonomously reset the AFE chip upon power failure via software. This reduces the frequency of manual after-sales maintenance, enhances the battery management system's ability to handle abnormal faults, thereby improving the robustness of the battery management system and enhancing the user experience.

[0006] In a first aspect, this application provides a hard reset control system, which includes at least one analog front-end chip and at least one hard reset control circuit, with each analog front-end chip corresponding to a hard reset control circuit. A first terminal of the hard reset control circuit is used to receive a control signal, a second terminal of the hard reset control circuit is connected to the power supply terminal of the corresponding analog front-end chip, and a third terminal of the hard reset control circuit is used to connect to a battery pack. The hard reset control circuit is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack according to the control signal, so that the analog front-end chip is powered off and reset.

[0007] In the technical solution of this application embodiment, when the AFE chip malfunctions, the hard reset control circuit can disconnect the power supply terminal of the analog front-end chip from the battery pack according to the control signal, thereby powering down and resetting the analog front-end chip. This improves the efficiency of fault handling. Compared with traditional physical intervention methods, this hard reset control system can restore normal operation in a shorter time, reducing the downtime of the battery management system. Furthermore, it eliminates the need for cumbersome disassembly; reset can be completed simply through control signals, reducing the complexity of manual intervention and the possibility of operational errors. This not only improves work efficiency but also enhances maintenance safety.

[0008] In some embodiments, the hard reset control circuit includes an isolation module and a switching module; a first terminal of the isolation module is used to receive a control signal, and a second terminal of the isolation module is connected to the first terminal of the switching module; the second terminal of the switching module is connected to the power supply terminal of the analog front-end chip, and a third terminal of the switching module is used to connect to the battery pack; the isolation module is used to drive the switching module according to the control signal; the switching module is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack under the drive of the isolation module, so as to power-off reset the analog front-end chip. In the technical solution of this application embodiment, the isolation module can electrically isolate the main controller and the AFE chip, which can not only reduce signal interference between the main controller and the AFE chip, but also protect the sensitive analog front-end chip from the effects of high voltage or instantaneous current, thereby extending the service life of the AFE chip. In addition, by disconnecting the connection between the power supply terminal of the analog front-end chip and the battery pack, the hard reset control circuit can perform a complete power-off reset when an AFE fault occurs, which can handle more types of AFE abnormal faults and improve the BMS fault recovery capability.

[0009] In some embodiments, the switching module includes a first switching circuit and a second switching circuit; a first terminal of the first switching circuit is connected to an isolation module, a second terminal of the first switching circuit is connected to the battery pack and the first terminal of the second switching circuit respectively, and a third terminal of the first switching circuit is connected to the second terminal of the second switching circuit; a first terminal of the second switching circuit is connected to the battery pack and the second terminal of the first switching circuit respectively, and a third terminal of the second switching circuit is connected to the power supply terminal of the analog front-end chip; the first switching circuit is used to control the second switching circuit under the drive of the isolation module; the second switching circuit is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack under the control of the first switching circuit, so as to power off and reset the analog front-end chip. In the technical solution of this application embodiment, after receiving the control signal, the first switching circuit can effectively manage the working state of the second switching circuit. This hierarchical control mechanism can improve the response speed of the circuit and quickly disconnect the connection between the power supply terminal of the AFE and the battery pack in the event of a fault, implementing a hard reset operation.

[0010] In some embodiments, the first switching circuit includes a first pull-up resistor and a first switching transistor; the first end of the first pull-up resistor is connected to the first end of the battery pack and the second switching circuit respectively; the second end of the first pull-up resistor is connected to the control electrode of the first switching transistor and the output terminal of the isolation module respectively; the first electrode of the first switching transistor is connected to the second end of the second switching circuit, and the second electrode of the first switching transistor is grounded. In the technical solution of this application embodiment, the first pull-up resistor provides a stable voltage reference point by connecting the battery pack to the first end of the second switching circuit, which can effectively reduce false triggering caused by signal fluctuations. The second end of the first pull-up resistor is connected to the control electrode of the first switching transistor, enabling the first switching transistor to respond quickly under the action of the control signal. The first electrode of the first switching transistor is connected to the second end of the second switching circuit, which can effectively control the power flow. By controlling the conduction and cutoff of the first switching transistor, effective power management can be achieved.

[0011] In some embodiments, the first switching circuit further includes a protective resistor; a first end of the protective resistor is connected to the control electrode of the first switching transistor, and a second end of the protective resistor is connected to the second end of the first pull-up resistor and the output terminal of the isolation module, respectively. In the technical solution of this application embodiment, the protective resistor is connected to the control electrode of the first switching transistor, which can effectively limit the current passing through the first switching transistor.

[0012] In some embodiments, the second switching circuit includes a second pull-up resistor and a second switching transistor; the first end of the second pull-up resistor is connected to the battery pack, the second end of the first switching circuit, and the first terminal of the second switching transistor; the second end of the second pull-up resistor is connected to the control terminal of the second switching transistor and the third end of the first switching circuit; the second terminal of the second switching transistor is connected to the power supply terminal of the analog front-end chip. In the technical solution of this application embodiment, the second pull-up resistor can effectively assist the second switching transistor in reliably switching under the action of the control signal, ensuring that the analog front-end chip always receives a stable power supply. With the assistance of the pull-up resistor, the control signal can switch the state of the second switching transistor more quickly and accurately, improving the response speed and accuracy of the hard reset control system to control commands.

[0013] In some embodiments, the isolation module includes an optical isolator, which includes a light-emitting diode (LED) and a receiving diode. A first end of the LED receives a control signal, and a second end of the LED is grounded. A first end of the receiving diode is connected to a switching module, and a second end of the receiving diode is grounded. In this embodiment, the first end of the LED receives the control signal, which allows the control signal to be effectively transmitted to the receiving diode without directly affecting the switching circuit. This configuration provides electrical isolation, avoiding interference from high voltage or noise on the control signal. Grounding the second end of the LED helps stabilize its operating state. Simultaneously, the connection between the receiving diode and the switching module allows the control signal to effectively drive the switching module.

[0014] In some embodiments, the isolation module further includes a pull-down resistor; the first end of the pull-down resistor is connected to the first end of the LED, and the second end of the pull-down resistor is grounded. In the technical solution of this application embodiment, the connection between the first end of the pull-down resistor and the first end of the LED allows the LED to remain in a low-level state when no control signal is received. This reduces the possibility of the LED being falsely triggered in the event of missing or interference of the control signal, thereby improving the stability of the battery management system.

[0015] In some embodiments, the switching module is housed within the corresponding analog front-end chip. In the technical solution of this application embodiment, by embedding the switching module within the analog front-end chip, the number of external components is reduced, thereby simplifying circuit design, reducing the complexity of the battery management system, and contributing to improved compactness and integrability of the battery management system. Furthermore, since the control signal is transmitted within the same AFE chip, delays and signal attenuation introduced by external connections are reduced. This direct connection enhances the response speed of the switching module, thereby achieving faster and more accurate power switching. In addition, internal integration improves the anti-interference capability of the battery management system. Because the switching module and the analog front-end chip operate in the same environment, the impact of external electromagnetic interference and noise is reduced.

[0016] In some embodiments, the hard reset multi-control system includes multiple hard reset control circuits and analog front-end chips corresponding to each hard reset control circuit. For the first-level hard reset control circuit, its first terminal is connected to the external main controller, its second terminal is connected to the power supply terminal of the corresponding analog front-end chip, and its third terminal is connected to the battery pack. For the i-th-level hard reset control circuit, its first terminal is connected to the previous-level analog front-end chip, its second terminal is connected to the power supply terminal of the corresponding analog front-end chip, and its third terminal is connected to the battery pack; where i is a positive integer greater than 1. In the technical solution of this application embodiment, the hierarchical hard reset multi-control system not only improves the efficiency of the reset operation but also enables the entire battery management system to quickly and safely recover to normal working condition when encountering an anomaly.

[0017] Secondly, this application provides a battery management system, which includes a main controller and the hard reset control system described in the first aspect.

[0018] In the technical solution of this application embodiment, when the AFE chip malfunctions, the hard reset control circuit can disconnect the power supply terminal of the analog front-end chip from the battery pack according to the control signal, thereby powering down and resetting the analog front-end chip. This improves the efficiency of fault handling. Compared with traditional physical intervention methods, this hard reset control system can restore normal operation in a shorter time, reducing the downtime of the battery management system. Furthermore, it eliminates the need for cumbersome disassembly; reset can be completed simply through control signals, reducing the complexity of manual intervention and the possibility of operational errors. This not only improves work efficiency but also enhances maintenance safety. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the alternative embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0020] Figure 1 This is a schematic diagram of the hard reset control system according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the hard reset control system according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the structure of a switch module according to an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the structure of a first switching circuit according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the structure of a first switching circuit according to an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of a second switching circuit according to an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the structure of an isolation module according to an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of an isolation module according to an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the hard reset control system according to an embodiment of this application;

[0029] Figure 10 This is a schematic diagram of the hard reset control system according to an embodiment of this application;

[0030] Figure 11 This is a schematic diagram of the hard reset control system according to an embodiment of this application;

[0031] Explanation of reference numerals in the attached figures:

[0032] Hard reset control system 10, battery pack 20, main controller 30;

[0033] Analog front-end chip 11, hard reset control circuit 12;

[0034] Isolation module 121, switch module 122;

[0035] First switching circuit 1221; Second switching circuit 1222;

[0036] First pull-up resistor R1; First switching transistor S1; Protection resistor R2;

[0037] Second pull-up resistor R3; Second switch S2;

[0038] Optical isolator 1211;

[0039] LED D1; receiver D2; pull-down resistor R4. Detailed Implementation

[0040] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0042] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0043] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0044] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0045] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0046] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0047] In the Battery Management System (BMS) of new energy vehicles, the AFE chip plays a crucial role. As the only integrated chip directly connected to the power battery, the AFE chip is responsible for real-time monitoring of various electrical parameters of the battery, including voltage, current, and temperature. Monitoring these electrical parameters is essential for the safety and performance of the battery. To ensure the normal operation of the AFE chip, the voltage of the battery pack must be maintained within a specific range, not lower than the AFE chip's self-reset voltage threshold. This measure aims to ensure that the AFE chip is always under uninterrupted power supply, enabling continuous monitoring and data acquisition.

[0048] However, in practical applications, the AFE chip may encounter various abnormal situations, such as malfunctions, register errors, or state machine anomalies. When these problems occur, the main controller sends a software reset command via a daisy chain to attempt to force the AFE chip to perform a reset operation. This software reset method can usually resolve some minor faults and restore the normal operation of the battery management system.

[0049] However, if the AFE chip malfunctions or freezes, its communication functions will be severely affected. In this situation, conventional software reset methods will not be effective in restoring it to normal operation, which may lead to a complete failure of the battery management system. This could result in limited or lost battery management system power, vehicle breakdown, and negatively impact user experience. In extreme cases, it could even compromise user safety.

[0050] Currently, the common way to resolve this abnormal fault is through physical intervention, which involves disassembling the battery system and directly disconnecting the battery pack from the AFE chip to achieve a power-off reset of the AFE chip. While this method can effectively reset the chip and restore the battery management system function in some cases, it is inefficient and cumbersome, leading to extended downtime for new energy vehicles and increased maintenance costs.

[0051] Based on this, this application provides a hard reset control system. The hard reset control circuit is a circuit component used to manage the power state of the AFE chip. The first terminal of the hard reset control circuit receives a control signal to trigger a hard reset operation. The second terminal of the hard reset control circuit is connected to the power supply terminal of the corresponding AFE chip, and the third terminal is connected to the battery pack to control the connection between the power supply terminal of the AFE chip and the battery pack. In the technical solution of this application, when the AFE chip malfunctions, the hard reset control circuit can disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack according to the control signal, causing the analog front-end chip to power down and reset, which improves the efficiency of fault handling. Compared with traditional physical intervention methods, this hard reset control system can restore normal operation in a shorter time, reducing the downtime of the battery management system. Furthermore, no cumbersome disassembly work is required; reset can be completed simply through a control signal, reducing the complexity of manual intervention and the possibility of operational errors. This not only improves work efficiency but also enhances maintenance safety.

[0052] According to some embodiments of this application, refer to Figure 1A hard reset control system is provided. The hard reset control system 10 includes at least one analog front-end chip 11 and at least one hard reset control circuit 12, with each analog front-end chip 11 corresponding to a hard reset control circuit 12. A first terminal of the hard reset control circuit 12 is used to receive a control signal, a second terminal of the hard reset control circuit 12 is connected to the power supply terminal of the corresponding analog front-end chip 11, and a third terminal of the hard reset control circuit 12 is used to connect to a battery pack 20. The hard reset control circuit 12 is used to disconnect the connection between the power supply terminal of the analog front-end chip 11 and the battery pack 20 according to the control signal, so that the analog front-end chip 11 is powered off and reset.

[0053] In this embodiment, the hard reset control circuit 12 is a circuit component used to manage the power state of the AFE chip 11. The first terminal of the hard reset control circuit 12 receives a control signal to trigger a hard reset operation. The second terminal of the hard reset control circuit 12 is connected to the power supply terminal of the corresponding AFE chip 11, and the third terminal of the hard reset control circuit 12 is connected to the battery pack 20 to control the connection and disconnection between the power supply terminal of the AFE chip 11 and the battery pack 20.

[0054] When the main controller 30 detects that the AFE chip 11 is in an abnormal state, such as "crash" or "stuck", the main controller 30 will send a control signal to the first terminal of the hard reset control circuit 12. The sending of this control signal marks the start of the reset process of the hard reset control system 10.

[0055] Next, the hard reset control circuit 12 responds to the control signal and can disconnect the connection between the second terminal and the power supply terminal of the AFE chip 11 through its internal switching mechanism, thereby disconnecting the connection between the power supply terminal of the AFE chip 11 and the battery pack 20, causing the AFE chip 11 to enter a power-off state. During this stage, all functions of the AFE chip 11 are disabled, its internal state machine and registers are reset, and all parameters and states of the AFE chip 11 are cleared, preparing for a subsequent reset.

[0056] In some embodiments, to ensure the effectiveness of the reset, the hard reset control circuit 12 sets a short delay time, typically a few milliseconds to a few seconds, depending on the characteristics of the AFE chip 11 and the system design. During this process, the AFE chip 11 completes an internal reset in a power-off state, clearing any residual states that may cause malfunctions.

[0057] After the delay ends, the hard reset control circuit 12 reconnects the battery pack 20 to the power supply terminal of the AFE chip 11, powering the AFE chip 11 back on. At this time, the AFE chip 11 begins self-testing and initialization, checking whether the status and function of its internal modules are normal.

[0058] Finally, the hard reset control system 10 confirms the operating status of the AFE chip 11 through the corresponding communication protocol to determine whether the reset was successful. If the reset is successful, the AFE chip 11 will resume normal monitoring and control functions, and the battery management system will re-enter normal operating mode. If the reset fails to resolve the issue, the hard reset control system 10 will record the fault status and may require further troubleshooting or physical intervention to improve the reliability and safety of the battery management system.

[0059] Under normal operating conditions, the AFE chip 11 begins operation when powered by the battery pack 20, continuously collecting key electrical parameter data such as battery voltage, current, and temperature. This electrical parameter data is transmitted to the main controller 30 through the communication interface of the AFE chip 11. The main controller 30 analyzes and processes the received information to assess the status and health of the battery pack 20.

[0060] During normal operation, the main controller 30 can also periodically send query signals to the AFE chip 11 to ensure smooth data communication. If the AFE chip 11 detects that the state of the battery pack 20 is within a safe range, the hard reset control system 10 will continue to perform routine monitoring and control tasks.

[0061] In addition, the main controller 30 will periodically perform self-tests to check the AFE chip 11 and its connection status with the battery pack 20. Under normal operating conditions, the communication between the AFE chip 11 and the main controller 30 is continuous and stable, and the data transmission is timely and accurate. The battery management system can effectively maintain the safety and performance of the battery pack 20.

[0062] In the above embodiments, the hard reset control system includes at least one analog front-end chip and at least one hard reset control circuit, with one analog front-end chip and one hard reset control circuit corresponding to each other; the first terminal of the hard reset control circuit is used to receive control signals, the second terminal of the hard reset control circuit is connected to the power supply terminal of the corresponding analog front-end chip, and the third terminal of the hard reset control circuit is used to connect to the battery pack; the hard reset control circuit is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack according to the control signal, so as to power off and reset the analog front-end chip.

[0063] In the technical solution of this application embodiment, when the AFE chip malfunctions, the hard reset control circuit can disconnect the power supply terminal of the analog front-end chip from the battery pack according to the control signal, thereby powering down and resetting the analog front-end chip. This improves the efficiency of fault handling. Compared with traditional physical intervention methods, this hard reset control system can restore normal operation in a shorter time, reducing the downtime of the battery management system. Furthermore, it eliminates the need for cumbersome disassembly; reset can be completed simply through control signals, reducing the complexity of manual intervention and the possibility of operational errors. This not only improves work efficiency but also enhances maintenance safety.

[0064] According to some embodiments of this application, refer to Figure 2 The aforementioned hard reset control circuit 12 includes an isolation module 121 and a switch module 122. The first end of the isolation module 121 is used to receive control signals, and the second end of the isolation module 121 is connected to the first end of the switch module 122. The second end of the switch module 122 is connected to the power supply terminal of the analog front-end chip 11, and the third end of the switch module 122 is used to connect to the battery pack 20. The isolation module 121 is used to drive the switch module 122 according to the control signals. The switch module 122 is used to disconnect the connection between the power supply terminal of the analog front-end chip 11 and the battery pack 20 under the drive of the isolation module 121, so that the analog front-end chip 11 is powered off and reset.

[0065] In this embodiment, the main function of the isolation module 121 is to receive control signals. The first end of the isolation module 121 can receive control signals from the main controller 30, and the second end is connected to the first end of the switch module 122.

[0066] The switch module 122 is the execution part that controls the power connection. Its second terminal is connected to the power supply terminal of the AFE chip 11, and its third terminal is connected to the battery pack 20. The switch module 122 performs switching operations under the action of the isolation module 121. When it receives a drive signal generated by the isolation module 121 based on control information, the switch module 122 will disconnect the connection between the power supply terminal of the AFE chip 11 and the battery pack 20, thereby putting the AFE chip 11 into a power-off state.

[0067] When the AFE chip 11 experiences an abnormal state, the main controller 30 first sends a control signal to the first terminal of the isolation module 121 to initiate a power-off reset process. Upon receiving the control signal, the isolation module 121 converts it into a drive signal and transmits it to the first terminal of the switch module 122, preparing to perform a power-off operation. Subsequently, driven by the isolation module 121, the switch module 122 disconnects its second terminal from the power supply terminal of the AFE chip 11, causing the AFE chip 11 to enter a power-off state.

[0068] At this time, the internal state machine and registers of AFE chip 11 are reset, and all functions are turned off to clear any residual states that may have caused a fault. To improve the effectiveness of the reset, the switch module 122 can be set with a short delay time to allow AFE chip 11 to complete its internal reset. After the delay, the switch module 122 reconnects the power supply terminal of AFE chip 11 to battery pack 20, thus powering AFE chip 11 back on.

[0069] After power is restored, the AFE chip 11 begins self-testing and initialization, checking the status and function of its internal modules. Finally, the main controller 30 confirms the operating status of the AFE chip 11 through the corresponding communication protocol to determine whether the reset was successful. If the reset is successful, the main controller 30 will resume normal monitoring and control functions; if abnormalities still exist, further troubleshooting or physical intervention is required to improve the reliability and safety of the battery management system.

[0070] Under normal operating conditions, the AFE chip 11 starts operating under the power supply of the battery pack 20, collecting electrical data in real time. This electrical data is periodically transmitted to the main controller 30 through its communication interface. The main controller 30 analyzes the received electrical data to evaluate the health status and performance of the battery pack 20.

[0071] During normal operation, the main controller 30 periodically sends query signals to the AFE chip 11. If the AFE chip 11 detects that the battery state is within a safe range, it continues to manage the charging and discharging process. Simultaneously, the main controller 30 periodically checks the AFE chip 11 and its connection status with the battery pack 20.

[0072] In the above embodiments, the hard reset control circuit includes an isolation module and a switching module. The first terminal of the isolation module receives a control signal, and the second terminal of the isolation module is connected to the first terminal of the switching module. The second terminal of the switching module is connected to the power supply terminal of the analog front-end chip, and the third terminal of the switching module is connected to the battery pack. The isolation module drives the switching module according to the control signal. The switching module, driven by the isolation module, disconnects the connection between the power supply terminal of the analog front-end chip and the battery pack, thereby powering down and resetting the analog front-end chip. In the technical solution of this application embodiment, the isolation module can electrically isolate the main controller from the AFE chip. This not only reduces signal interference between the main controller and the AFE chip but also protects the sensitive analog front-end chip from high voltage or instantaneous current, thus extending the lifespan of the AFE chip. Furthermore, by disconnecting the connection between the power supply terminal of the analog front-end chip and the battery pack, the hard reset control circuit can perform a complete power-down reset when an AFE fault occurs. This can handle more types of AFE abnormal faults and improve the BMS fault recovery capability.

[0073] According to some embodiments of this application, refer to Figure 3 The aforementioned switch module 122 includes a first switch circuit 1221 and a second switch circuit 1222. The first terminal of the first switch circuit 1221 is connected to the isolation module 121, the second terminal of the first switch circuit 1221 is connected to the battery pack 20 and the first terminal of the second switch circuit 1222, and the third terminal of the first switch circuit 1221 is connected to the second terminal of the second switch circuit 1222. The first terminal of the second switch circuit 1222 is connected to the battery pack 20 and the second terminal of the first switch circuit 1221, and the third terminal of the second switch circuit 1222 is connected to the power supply terminal of the analog front-end chip 11. The first switch circuit 1221 is used to control the second switch circuit 1222 under the drive of the isolation module 121. The second switch circuit 1222 is used to disconnect the connection between the power supply terminal of the analog front-end chip 11 and the battery pack 20 under the control of the first switch circuit 1221, so that the analog front-end chip 11 is powered off and reset.

[0074] In this embodiment, the first terminal of the first switching circuit 1221 is connected to the isolation module 121 to receive a drive signal generated by the isolation module 121 based on a control signal. Its second terminal is connected to both the battery pack 20 and the first terminal of the second switching circuit 1222, enabling power management between the battery pack 20 and the second switching circuit 1222. The third terminal is connected to the second terminal of the second switching circuit 1222 to facilitate power switching. The main function of the first switching circuit 1221 is to control the operation of the second switching circuit 1222 under the drive of the isolation module 121.

[0075] The first terminal of the second switching circuit 1222 is connected to the battery pack 20 and the second terminal of the first switching circuit 1221, enabling it to switch power supplies when powered by the battery pack 20. The third terminal of the second switching circuit 1222 is connected to the power supply terminal of the analog front-end chip 11, forming a power supply path.

[0076] The second switching circuit 1222 operates under the control of the first switching circuit 1221, and is mainly responsible for disconnecting the power supply terminal of the AFE chip 11 from the battery pack 20. By disconnecting this connection, the second switching circuit 1222 achieves the power-off reset of the AFE chip 11.

[0077] When the AFE chip 11 malfunctions, the main controller 30 first sends a control signal to the first terminal of the isolation module 121 to initiate a power-off reset process. After receiving the control signal, the isolation module 121 converts it into a drive signal and transmits it to the first terminal of the first switching circuit 1221.

[0078] Next, the first switching circuit 1221 controls the second switching circuit 1222 according to the drive signal to disconnect the connection between the power supply terminal of the AFE chip 11 and the battery pack 20, causing the AFE chip 11 to enter a power-off state. In this state, the internal state machine and registers of the AFE chip 11 are reset, clearing any residual states that may cause malfunctions and preparing for normal operation.

[0079] After a set delay, the first switching circuit 1221 and the second switching circuit 1222 reconnect to the power supply, restoring power to the AFE chip 11. Upon power-up, the AFE chip 11 begins a self-test and initialization process to verify the functionality of its modules. Finally, the operating status of the AFE chip 11 is confirmed via the corresponding communication protocol to determine if the reset was successful. If the reset is successful, normal monitoring and control functions are restored; if the reset fails to resolve the issue, further troubleshooting or physical intervention is required to ensure the reliability and safety of the battery management system.

[0080] Under normal operating conditions, the AFE chip 11 starts operating under the power supply of the battery pack 20, collecting electrical data in real time. This electrical data is periodically transmitted to the main controller 30 through its communication interface. The main controller 30 analyzes the received electrical data to assess the health status and performance of the battery pack 20.

[0081] During normal operation, the main controller 30 periodically sends query signals to the AFE chip 11. The AFE chip 11 responds to these query signals, providing the latest battery status information. If the battery status is detected to be within a safe range, the management of the charging and discharging process continues.

[0082] In the above embodiments, the switching module includes a first switching circuit and a second switching circuit. The first terminal of the first switching circuit is connected to the isolation module, the second terminal of the first switching circuit is connected to the battery pack and the first terminal of the second switching circuit, and the third terminal of the first switching circuit is connected to the second terminal of the second switching circuit. The first terminal of the second switching circuit is connected to the battery pack and the second terminal of the first switching circuit, and the third terminal of the second switching circuit is connected to the power supply terminal of the analog front-end chip. The first switching circuit controls the second switching circuit under the drive of the isolation module. The second switching circuit, under the control of the first switching circuit, disconnects the connection between the power supply terminal of the analog front-end chip and the battery pack, thereby powering down and resetting the analog front-end chip. In the technical solution of this application embodiment, after receiving a control signal, the first switching circuit can effectively manage the working state of the second switching circuit. This hierarchical control mechanism can improve the circuit's response speed and quickly disconnect the connection between the power supply terminal of the AFE and the battery pack in case of a fault, implementing a hard reset operation.

[0083] According to some embodiments of this application, refer to Figure 4 The first switching circuit 1221 includes a first pull-up resistor R1 and a first switching transistor S1; the first end of the first pull-up resistor R1 is connected to the first end of the battery pack 20 and the second switching circuit 1222 respectively; the second end of the first pull-up resistor R1 is connected to the control electrode of the first switching transistor S1 and the output end of the isolation module 121 respectively; the first electrode of the first switching transistor S1 is connected to the second end of the second switching circuit 1222, and the second electrode of the first switching transistor S1 is grounded.

[0084] In this embodiment, the first terminal of the first pull-up resistor R1 is connected to the first terminal of the battery pack 20 and the second switch circuit 1222, respectively, to provide a voltage reference point. Its second terminal is connected to the control electrode of the first switch transistor S1 and the output terminal of the isolation module 121, respectively. By introducing a control signal into the first pull-up resistor R1, the control electrode of the first switch transistor S1 can obtain an appropriate drive voltage, thereby achieving effective management of the power supply connection.

[0085] The first terminal of the first switching transistor S1 is connected to the second terminal of the second switching circuit 1222, allowing power to flow from the battery pack 20 to the AFE chip 11; while the second terminal is grounded, enabling the first switching transistor S1 to operate normally. Upon receiving a control signal from the isolation module 121, the first switching transistor S1 can quickly switch its state, thereby controlling the power supply of the AFE chip 11.

[0086] Under normal operating conditions, the first pull-up resistor R1 ensures that the control electrode of the first switching transistor S1 receives an appropriate voltage signal, causing the first switching transistor S1 to be in a conducting state. In this way, the AFE chip 11 can stably obtain power from the battery pack 20.

[0087] When the AFE chip 11 malfunctions, the main controller 30 detects the malfunction and sends a control signal to the first terminal of the isolation module 121 to enable the hard reset process. Upon receiving the control signal, the isolation module 121 generates a corresponding drive signal and transmits it to the first terminal of the first switching circuit 1221.

[0088] Upon receiving the drive signal, the second switch circuit 1222, under the control of the first switch circuit 1221, disconnects the connection between the power supply terminal of the AFE chip 11 and the battery pack 20, causing the AFE chip to enter a power-off state.

[0089] In the power-off state, the internal state machine and registers of the AFE chip 11 are reset, clearing any residual states that may have caused a fault. After a set delay time, the first switching circuit 1221 and the second switching circuit 1222 reconnect to the power supply, restoring power to the AFE chip 11.

[0090] After power is restored, the AFE chip 11 will perform a self-test and initialization process to confirm whether the functions of its internal modules are normal. The main controller 30 confirms the operating status of the AFE chip 11 through the corresponding communication protocol to determine whether the reset was successful. If the reset is successful, normal monitoring and control functions will be restored.

[0091] In the above embodiments, the first switching circuit includes a first pull-up resistor and a first switching transistor; the first end of the first pull-up resistor is connected to the first end of the battery pack and the second switching circuit respectively; the second end of the first pull-up resistor is connected to the control electrode of the first switching transistor and the output terminal of the isolation module respectively; the first electrode of the first switching transistor is connected to the second end of the second switching circuit, and the second electrode of the first switching transistor is grounded. In the technical solution of this application embodiment, the first pull-up resistor provides a stable voltage reference point by connecting the battery pack to the first end of the second switching circuit, which can effectively reduce false triggering caused by signal fluctuations. The second end of the first pull-up resistor is connected to the control electrode of the first switching transistor, enabling the first switching transistor to respond quickly under the action of the control signal. The first electrode of the first switching transistor is connected to the second end of the second switching circuit, which can effectively control the power flow. By controlling the conduction and cutoff of the first switching transistor, effective power management can be achieved.

[0092] According to some embodiments of this application, refer to Figure 5 The first switching circuit 1221 mentioned above also includes a protection resistor R2; the first end of the protection resistor R2 is connected to the control electrode of the first switching transistor S1, and the second end of the protection resistor R2 is connected to the second end of the first pull-up resistor R1 and the output end of the isolation module 121 respectively.

[0093] In this embodiment, the first end of the protection resistor R2 is connected to the control electrode of the first switching transistor S1, and its second end is connected to the second end of the first pull-up resistor R1 and the output terminal of the isolation module 121. The main function of the protection resistor R2 is to provide overcurrent protection in the circuit, limiting the current through the control electrode to reduce device damage caused by excessive current. Under normal operating conditions, the protection resistor R2 and the first pull-up resistor R1 work together to ensure that the control electrode of the first switching transistor S1 receives a stable voltage signal, thereby allowing the AFE chip 11 to stably receive power.

[0094] In some embodiments, the protection resistor R2 can also be integrated into the first switching transistor S1.

[0095] In the above embodiments, the first switching circuit further includes a protective resistor; the first end of the protective resistor is connected to the control electrode of the first switching transistor, and the second end of the protective resistor is connected to the second end of the first pull-up resistor and the output terminal of the isolation module, respectively. In the technical solution of this application embodiment, the protective resistor is connected to the control electrode of the first switching transistor, which can effectively limit the current passing through the first switching transistor.

[0096] According to some embodiments of this application, refer to Figure 6 The second switching circuit 1222 includes a second pull-up resistor R3 and a second switching transistor S2; the first end of the second pull-up resistor R3 is connected to the battery pack 20, the second end of the first switching circuit 1221, and the first terminal of the second switching transistor S2; the second end of the second pull-up resistor R3 is connected to the control terminal of the second switching transistor S2 and the third end of the first switching circuit 1221; the second terminal of the second switching transistor S2 is connected to the power supply terminal of the analog front-end chip 11.

[0097] In this embodiment, the first terminal of the second pull-up resistor R3 is connected to the battery pack 20, the second terminal of the first switching circuit 1221, and the first terminal of the second switching transistor S2, respectively, providing a voltage reference point so that the second switching transistor S2 can operate at a suitable voltage. Its second terminal is connected to the control terminal of the second switching transistor S2 and the third terminal of the first switching circuit 1221, allowing for effective transmission of control signals.

[0098] The second switch S2 is responsible for switching control in the circuit. Its first terminal is connected to the first end of the second pull-up resistor R3, receiving power from the battery pack 20; its second terminal is connected to the power supply terminal of the analog front-end chip 11, allowing power to flow to the AFE chip 11. After receiving a control signal from the first switching circuit 1221, the second switch S2 can switch its state, thereby controlling the power supply to the AFE chip 11.

[0099] Under normal operating conditions, the second pull-up resistor R3 enables the control electrode of the second switch S2 to receive an appropriate voltage signal, putting it in a conducting state, thereby allowing the AFE chip 11 to continuously and stably receive power.

[0100] When the AFE chip 11 malfunctions, the main controller 30 detects the malfunction and sends a control signal to the first terminal of the isolation module 121 to enable the hard reset process. After receiving the control signal, the isolation module 121 generates a corresponding drive signal and transmits it to the first terminal of the first switching circuit 1221.

[0101] Upon receiving the drive signal, the second switch circuit 1222, under the control of the first switch circuit 1221, disconnects the connection between the power supply terminal of the AFE chip 11 and the battery pack 20, causing the AFE chip 11 to enter a power-off state.

[0102] In this power-off state, the internal state machine and registers of the AFE chip 11 are reset, clearing any residual states that could cause a fault. After a set delay time, the first switching circuit 1221 and the second switching circuit 1222 reconnect to the power supply, restoring power to the AFE chip 11.

[0103] In the above embodiments, the second switching circuit includes a second pull-up resistor and a second switching transistor; the first end of the second pull-up resistor is connected to the battery pack, the second end of the first switching circuit, and the first terminal of the second switching transistor, respectively; the second end of the second pull-up resistor is connected to the control terminal of the second switching transistor and the third end of the first switching circuit, respectively; the second terminal of the second switching transistor is connected to the power supply terminal of the analog front-end chip. In the technical solution of this application embodiment, the second pull-up resistor can effectively assist the second switching transistor in reliably switching under the action of the control signal, so that the analog front-end chip always obtains a stable power supply. With the assistance of the pull-up resistor, the control signal can switch the state of the second switching transistor more quickly and accurately, improving the response speed and accuracy of the hard reset control system to control commands.

[0104] According to some embodiments of this application, refer to Figure 7 The aforementioned isolation module 121 includes an optical isolator 1211, which includes a light-emitting diode D1 and a receiving diode D2. The first end of the light-emitting diode D1 is used to receive control signals, and the second end of the light-emitting diode D1 is grounded. The first end of the receiving diode D2 is connected to the switch module 122, and the second end of the receiving diode D2 is grounded.

[0105] In this embodiment, the isolation module 121 is composed of an optical isolator 1211, which is mainly used to achieve the isolation and transmission of control signals. The optical isolator 1211 includes a light-emitting diode D1 and a receiving diode D2, which is responsible for transmitting the control signal from the main controller to the switching module 122.

[0106] The first terminal of LED D1 is used to receive control signals. When the main controller 30 sends a control signal, LED D1 will generate a corresponding light signal according to the received control signal. The second terminal of LED D1 is grounded to ensure its normal operation and stable signal transmission.

[0107] The first terminal of receiver D2 is connected to switch module 122, responsible for receiving the optical signal from LED D1 and converting it into an electrical signal. The second terminal of receiver D2 is also grounded to ensure its proper functioning. (Continue referring to...) Figure 7 The main controller 30 is connected to GND2, and the AFE chip 11 is connected to GND1.

[0108] Under normal operating conditions, after receiving a control signal, the light-emitting diode D1 generates a light signal, which is captured by the receiving diode D2 and converted into an electrical signal. This electrical signal drives the corresponding operation of the switching module 122, thereby controlling the power supply state of the AFE chip 11. During the power-off reset process, the isolation module 121 ensures effective isolation between the control signal and the main power supply circuit, avoiding current interference caused by the transmission of the control signal, thereby enhancing the safety and reliability of the BMS.

[0109] In the above embodiments, the isolation module includes an optical isolator, which includes a light-emitting diode (LED) and a receiving diode. The first end of the LED receives a control signal, and the second end is grounded. The first end of the receiving diode is connected to the switching module, and the second end is grounded. In the technical solution of this application embodiment, the first end of the LED receives the control signal, which allows the control signal to be effectively transmitted to the receiving diode without directly affecting the switching circuit. This configuration provides electrical isolation, avoiding interference from high voltage or noise on the control signal. Grounding the second end of the LED helps stabilize its operating state. Simultaneously, the connection between the receiving diode and the switching module allows the control signal to effectively drive the switching module.

[0110] According to some embodiments of this application, refer to Figure 8 The aforementioned isolation module 121 also includes a pull-down resistor R4; the first end of the pull-down resistor R4 is connected to the first end of the LED D1, and the second end of the pull-down resistor R4 is grounded.

[0111] In this embodiment of the application, the isolation module 121 includes not only the optical isolation device 1211, namely the light-emitting diode D1 and the receiving diode D2, but also the pull-down resistor R4.

[0112] The first terminal of pull-down resistor R4 is connected to the first terminal of LED D1 to provide a stable reference voltage. When LED D1 does not receive a control signal, pull-down resistor R4 pulls the control terminal voltage of LED D1 to ground level to prevent false triggering. The second terminal of pull-down resistor R4 is grounded to ensure its normal operation. (Continue referring to...) Figure 8 The main controller 30 is connected to GND2, and the AFE chip 11 is connected to GND1.

[0113] Under normal operating conditions, LED D1 receives a control signal and generates a corresponding light signal. Receiver D2 receives this light signal and converts it into an electrical signal. Pull-down resistor R4 keeps LED D1 at a low level when there is no control signal, thus preventing malfunctions caused by noise or interference. Combining the functions of LED D1 and receiver D2, pull-down resistor R4 works together to ensure effective transmission and electrical isolation of the control signal.

[0114] In the above embodiments, the isolation module further includes a pull-down resistor; the first end of the pull-down resistor is connected to the first end of the LED, and the second end of the pull-down resistor is grounded. In the technical solution of this application embodiment, the connection between the first end of the pull-down resistor and the first end of the LED allows the LED to remain in a low-level state when no control signal is received. This reduces the possibility of the LED being falsely triggered in the event of missing or interference of the control signal, thereby improving the stability of the battery management system.

[0115] According to some embodiments of this application, refer to Figure 9 The aforementioned switch module 122 is located inside the corresponding analog front-end chip 11.

[0116] In this embodiment, the switch module 122 is an important component located inside the corresponding analog front-end chip 11. Its main function is to manage the connection and disconnection between the power supply terminal of the analog front-end chip 11 and the battery pack 20, so as to ensure the normal operation of the AFE chip 11 under different working states. (Continuing to refer to...) Figure 9 The main controller 30 is connected to GND2, and the AFE chip 11 is connected to GND1.

[0117] The internal integrated design of the switch module 122 enables it to work closely with the analog front-end chip 11. The switch module 122 consists of multiple switch circuits and is responsible for receiving control signals and adjusting the connection between the power supply terminal of the analog front-end chip 11 and the battery pack 20 according to the control signals.

[0118] Under normal operating conditions, the switch module 122 can quickly respond to control signals, ensuring that the AFE chip 11 always receives a stable power supply. When an abnormality is detected in the AFE chip 11, the connection between the power supply terminal of the analog front-end chip 11 and the battery pack 20 is promptly disconnected.

[0119] In the above embodiments, the switching module is housed within the corresponding analog front-end chip. In the technical solution of this application, by embedding the switching module within the analog front-end chip, the number of external components is reduced, thereby simplifying circuit design, reducing the complexity of the battery management system, and contributing to improved compactness and integrability. Furthermore, since the control signal is transmitted within the same AFE chip, delays and signal attenuation introduced by external connections are reduced. This direct connection enhances the response speed of the switching module, enabling faster and more accurate power switching. In addition, internal integration improves the battery management system's anti-interference capability. Because the switching module and the analog front-end chip operate in the same environment, the impact of external electromagnetic interference and noise is reduced.

[0120] In some embodiments, refer to Figure 10Alternatively, the first switching transistor S1 and the second switching circuit 1222 can be housed inside the corresponding analog front-end chip 11. The main controller 30 is connected to GND2, and the AFE chip 11 is connected to GND1.

[0121] In the above embodiments, the hard reset control circuit is housed within the corresponding analog front-end chip. In the technical solution of this application, integrating the hard reset control circuit with the analog front-end chip helps reduce the physical space requirements of the circuit, thereby improving the compactness of the overall hard reset control system. Since the hard reset control circuit is directly embedded within the analog front-end chip, the signal transmission distance is shortened, reducing latency caused by external connections.

[0122] According to some embodiments of this application, refer to Figure 11 The aforementioned hard reset multi-control system includes multiple hard reset control circuits 12 and analog front-end chips 11 corresponding to each hard reset control circuit 12. For the first-level hard reset control circuit 12, the first terminal of the first-level hard reset control circuit 12 is used to connect to the main controller 30 outside the hard reset multi-control system 10, the second terminal of the first-level hard reset control circuit 12 is connected to the power supply terminal of the corresponding analog front-end chip 11, and the third terminal of the first-level hard reset control circuit 12 is used to connect to the battery pack 20. For the i-th level hard reset control circuit 12, the first terminal of the i-th level hard reset control circuit 12 is connected to the previous level analog front-end chip 11, the second terminal of the i-th level hard reset control circuit 12 is connected to the power supply terminal of the corresponding analog front-end chip 11, and the third terminal of the i-th level hard reset control circuit 12 is used to connect to the battery pack 20. Here, i is a positive integer greater than 1.

[0123] In this embodiment, the primary hard reset control circuit 12 is located at the outermost layer of the hard reset control system 10, and its main function is to receive instructions from the external main controller 30. The first terminal of the primary hard reset control circuit 12 is connected to the main controller 30 and is responsible for receiving control information. Its second terminal is connected to the power supply terminal of the corresponding analog front-end chip 11, so that when a reset signal is received, the connection between the power supply terminal of the analog front-end chip 11 and the battery pack 20 is cut off. Its third terminal is connected to the battery pack 20, enabling it to effectively manage the power supply to the battery pack 20.

[0124] The i-th stage hard reset control circuit 12 is connected to the analog front-end chip 11 of the previous stage hard reset control circuit 12, forming a hierarchical structure. The first terminal of the i-th stage hard reset control circuit 12 is connected to the analog front-end chip 11 of the previous stage, and the second terminal is connected to the power supply terminal of its corresponding analog front-end chip 11, which can disconnect the power supply when a reset signal is received. The third terminal is also connected to the battery pack 20 to maintain the power supply to the battery pack 20.

[0125] Continue to refer to Figure 11As shown, when the main controller 30 sends a control signal, it first triggers the first-stage hard reset control circuit 12, disconnecting the power supply terminal of AFE1 chip 11 from the battery pack 20, thus performing a hard reset. After the hard reset of AFE1 chip 11 is completed, the main controller 30 sends control signals to the already functioning AFE1 chip 11 via a daisy chain, using its general purpose input / output (GPIO) pins to control the next-stage hard reset control circuit 12, thereby achieving a hard reset of AFE2 chip 11. Through this step-by-step reset mechanism, the main controller 30 can effectively manage the state of all AFE chips 11, enabling each AFE chip 11 to quickly and reliably return to its normal working state when needed. The main controller 30 is connected to GND2, AFE1 chip 11 is connected to GND1, and AFE2 chip 11 is connected to GND3.

[0126] In the above embodiments, the hard reset multi-control system includes multiple hard reset control circuits and analog front-end chips corresponding to each hard reset control circuit. For the first-level hard reset control circuit, its first terminal is connected to the external main controller, its second terminal is connected to the power supply terminal of the corresponding analog front-end chip, and its third terminal is connected to the battery pack. For the i-th-level hard reset control circuit, its first terminal is connected to the previous-level analog front-end chip, its second terminal is connected to the power supply terminal of the corresponding analog front-end chip, and its third terminal is connected to the battery pack. Here, i is a positive integer greater than 1. In the technical solution of this application embodiment, the hierarchical hard reset multi-control system not only improves the efficiency of the reset operation but also enables the entire battery management system to quickly and safely recover to normal working condition when encountering an anomaly.

[0127] According to some embodiments of this application, a battery management system is provided. The battery management system includes a main controller 30 and the aforementioned hard reset control system 10.

[0128] The hard reset control system 10 includes at least one analog front-end chip 11 and at least one hard reset control circuit 12, with each analog front-end chip 11 corresponding to a hard reset control circuit 12. The first terminal of the hard reset control circuit 12 is used to receive control signals, the second terminal of the hard reset control circuit 12 is connected to the power supply terminal of the corresponding analog front-end chip 11, and the third terminal of the hard reset control circuit 12 is used to connect to the battery pack 20. The hard reset control circuit 12 is used to disconnect the connection between the power supply terminal of the analog front-end chip 11 and the battery pack 20 according to the control signal, so that the analog front-end chip 11 is powered off and reset.

[0129] In this embodiment, the hard reset control circuit 12 is a circuit component used to manage the power state of the AFE chip 11. The first terminal of the hard reset control circuit 12 receives a control signal to trigger a hard reset operation. The second terminal of the hard reset control circuit 12 is connected to the power supply terminal of the corresponding AFE chip 11, and the third terminal of the hard reset control circuit 12 is connected to the battery pack 20 to control the connection and disconnection between the power supply terminal of the AFE chip 11 and the battery pack 20.

[0130] When the main controller 30 detects that the AFE chip 11 is in an abnormal state, such as "crash" or "stuck", the main controller 30 will send a control signal to the first terminal of the hard reset control circuit 12. The sending of this control signal marks the start of the reset process of the hard reset control system 10.

[0131] Next, the hard reset control circuit 12 responds to the control signal and can disconnect the connection between the second terminal and the power supply terminal of the AFE chip 11 through its internal switching mechanism, thereby disconnecting the connection between the power supply terminal of the AFE chip 11 and the battery pack 20, causing the AFE chip 11 to enter a power-off state. During this stage, all functions of the AFE chip 11 are disabled, its internal state machine and registers are reset, and all parameters and states of the AFE chip 11 are cleared, preparing for a subsequent reset.

[0132] In some embodiments, to ensure the effectiveness of the reset, the hard reset control circuit 12 sets a short delay time, typically a few milliseconds to a few seconds, depending on the characteristics of the AFE chip 11 and the system design. During this process, the AFE chip 11 completes an internal reset in a power-off state, clearing any residual states that may cause malfunctions.

[0133] After the delay ends, the hard reset control circuit 12 reconnects the battery pack 20 to the power supply terminal of the AFE chip 11, powering the AFE chip 11 back on. At this time, the AFE chip 11 begins self-testing and initialization, checking whether the status and function of its internal modules are normal.

[0134] Finally, the hard reset control system 10 confirms the operating status of the AFE chip 11 through the corresponding communication protocol to determine whether the reset was successful. If the reset is successful, the AFE chip 11 will resume normal monitoring and control functions, and the battery management system will re-enter normal operating mode. If the reset fails to resolve the issue, the hard reset control system 10 will record the fault status and may require further troubleshooting or physical intervention to improve the reliability and safety of the battery management system.

[0135] Under normal operating conditions, the AFE chip 11 begins operation when powered by the battery pack 20, continuously collecting key electrical parameter data such as battery voltage, current, and temperature. This electrical parameter data is transmitted to the main controller 30 through the communication interface of the AFE chip 11. The main controller 30 analyzes and processes the received information to assess the status and health of the battery pack 20.

[0136] During normal operation, the main controller 30 can also periodically send query signals to the AFE chip 11 to ensure smooth data communication. If the AFE chip 11 detects that the state of the battery pack 20 is within a safe range, the hard reset control system 10 will continue to perform routine monitoring and control tasks.

[0137] In addition, the main controller 30 will periodically perform self-tests to check the AFE chip 11 and its connection status with the battery pack 20. Under normal operating conditions, the communication between the AFE chip 11 and the main controller 30 is continuous and stable, and the data transmission is timely and accurate. The battery management system can effectively maintain the safety and performance of the battery pack 20.

[0138] In the above embodiments, the hard reset control system includes at least one analog front-end chip and at least one hard reset control circuit, with one analog front-end chip and one hard reset control circuit corresponding to each other; the first terminal of the hard reset control circuit is used to receive control signals, the second terminal of the hard reset control circuit is connected to the power supply terminal of the corresponding analog front-end chip, and the third terminal of the hard reset control circuit is used to connect to the battery pack; the hard reset control circuit is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack according to the control signal, so as to power off and reset the analog front-end chip.

[0139] In the technical solution of this application embodiment, when the AFE chip malfunctions, the hard reset control circuit can disconnect the power supply terminal of the analog front-end chip from the battery pack according to the control signal, thereby powering down and resetting the analog front-end chip. This improves the efficiency of fault handling. Compared with traditional physical intervention methods, this hard reset control system can restore normal operation in a shorter time, reducing the downtime of the battery management system. Furthermore, it eliminates the need for cumbersome disassembly; reset can be completed simply through control signals, reducing the complexity of manual intervention and the possibility of operational errors. This not only improves work efficiency but also enhances maintenance safety.

[0140] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The embodiments described above are merely illustrative of several implementation methods of this application, intended to facilitate a detailed understanding of the technical solutions of this application, but should not be construed as limiting the scope of protection of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. It should be understood that technical solutions obtained by those skilled in the art based on the technical solutions provided in this application through logical analysis, reasoning, or limited experimentation are all within the scope of protection of the appended claims. Therefore, the scope of protection of this patent application should be determined by the content of the appended claims, and the specification and drawings can be used to interpret the content of the claims.

Claims

1. A hard reset control system, characterized in that, The hard reset control system includes at least one analog front-end chip and at least one hard reset control circuit, with the analog front-end chip and the hard reset control circuit corresponding one-to-one. The first terminal of the hard reset control circuit is used to receive control signals, the second terminal of the hard reset control circuit is connected to the power supply terminal of the corresponding analog front-end chip, and the third terminal of the hard reset control circuit is used to connect to the battery pack. The hard reset control circuit is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack according to the control signal, so as to power off and reset the analog front-end chip.

2. The hard reset control system according to claim 1, characterized in that, The hard reset control circuit includes an isolation module and a switching module; the first terminal of the isolation module is used to receive the control signal, the second terminal of the isolation module is connected to the first terminal of the switching module; the second terminal of the switching module is connected to the power supply terminal of the analog front-end chip, and the third terminal of the switching module is used to connect to the battery pack. The isolation module is used to drive the switching module according to the control signal; The switching module is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack under the drive of the isolation module, so as to power off and reset the analog front-end chip.

3. The hard reset control system according to claim 2, characterized in that, The switching module includes a first switching circuit and a second switching circuit; The first terminal of the first switching circuit is connected to the isolation module, the second terminal of the first switching circuit is connected to the battery pack and the first terminal of the second switching circuit, and the third terminal of the first switching circuit is connected to the second terminal of the second switching circuit; the first terminal of the second switching circuit is connected to the battery pack and the second terminal of the first switching circuit, and the third terminal of the second switching circuit is connected to the power supply terminal of the analog front-end chip. The first switching circuit is used to control the second switching circuit under the drive of the isolation module; The second switching circuit is used to disconnect the connection between the power supply terminal of the analog front-end chip and the battery pack under the control of the first switching circuit, so as to power off and reset the analog front-end chip.

4. The hard reset control system according to claim 3, characterized in that, The first switching circuit includes a first pull-up resistor and a first switching transistor; The first end of the first pull-up resistor is connected to the battery pack and the first end of the second switching circuit, respectively; the second end of the first pull-up resistor is connected to the control electrode of the first switching transistor and the output end of the isolation module, respectively. The first terminal of the first switching transistor is connected to the second terminal of the second switching circuit, and the second terminal of the first switching transistor is grounded.

5. The hard reset control system according to claim 4, characterized in that, The first switching circuit also includes a protective resistor; The first end of the protection resistor is connected to the control electrode of the first switching transistor, and the second end of the protection resistor is connected to the second end of the first pull-up resistor and the output end of the isolation module.

6. The hard reset control system according to claim 3, characterized in that, The second switching circuit includes a second pull-up resistor and a second switching transistor; The first end of the second pull-up resistor is connected to the battery pack, the second end of the first switching circuit, and the first terminal of the second switching transistor, respectively; the second end of the second pull-up resistor is connected to the control terminal of the second switching transistor and the third end of the first switching circuit, respectively. The second terminal of the second switching transistor is connected to the power supply terminal of the analog front-end chip.

7. The hard reset control system according to claim 2, characterized in that, The isolation module includes an optical isolator, which includes a light-emitting diode and a receiving diode. The first end of the light-emitting diode is used to receive the control signal, and the second end of the light-emitting diode is grounded; The first end of the receiving tube is connected to the switch module, and the second end of the receiving tube is grounded.

8. The hard reset control system according to claim 7, characterized in that, The isolation module also includes a pull-down resistor; The first end of the pull-down resistor is connected to the first end of the LED, and the second end of the pull-down resistor is grounded.

9. The hard reset control system according to claim 2, characterized in that, The switch module is located inside the corresponding analog front-end chip.

10. The hard reset control system according to any one of claims 1-9, characterized in that, The hard reset control system includes multiple hard reset control circuits and analog front-end chips corresponding to each hard reset control circuit. For the primary hard reset control circuit, the first terminal of the primary hard reset control circuit is used to connect to the main controller outside the system, the second terminal of the primary hard reset control circuit is connected to the power supply terminal of the corresponding analog front-end chip, and the third terminal of the primary hard reset control circuit is used to connect to the battery pack. For the i-th stage hard reset control circuit, the first terminal of the i-th stage hard reset control circuit is connected to the previous stage analog front-end chip, the second terminal of the i-th stage hard reset control circuit is connected to the power supply terminal of the corresponding analog front-end chip, and the third terminal of the i-th stage hard reset control circuit is used to connect to the battery pack; where i is a positive integer greater than 1.

11. A battery management system, characterized in that, The battery management system includes a main controller and a hard reset control circuit as described in any one of claims 1-10.

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