Embedded memory chip testing device

Abstract

The utility model discloses an embedded memory chip testing device, which comprises a chip strip, a testing seat and a pressing block, and is characterized in that the chip strip is a splicing body of a plurality of chips subjected to patch and wire bonding, and the plurality of chips are distributed in an array; a plurality of connecting pieces are arranged on the upper end surface of the test seat, and the connecting pieces are in one-to-one correspondence with pin bonding pads on the back surface of a to-be-tested chip strip; the chip strip is pressed and attached to the test seat through the pressing block, a hollow window is formed in the pressing block, and the position of the hollow window is matched with that of the chip. By testing part of the chip after wire bonding, whether each process is abnormal or not before packaging can be quickly confirmed, so that the test verification of the chip is greatly accelerated, the function verification period is shortened, and the product development risk, the later invalid production investment and the application risk in a terminal are reduced.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to an embedded memory chip testing device. Background Technology

[0002] Testing of embedded memory chips is a crucial step in ensuring stable yield and reliable performance during the packaging process. Currently, most testing is performed after packaging, resulting in significant delays. Based on the production cycles of most packaging and testing companies, chip performance and yield can only be known 7-15 days later. Furthermore, multiple processes during chip manufacturing can lead to product quality issues, which are often difficult to detect using methods like X-ray and SAT, hindering effective defect interception and increasing manufacturing risks.

[0003] In order to test the basic electrical functions of the chip as early as possible and ensure the process yield, some manufacturers use probes to press onto the gold fingers for testing after wire bonding. However, this method can only perform simple open and short circuit tests, and the probes need to be carefully placed manually by the operator, which is inefficient and easy to touch the gold wires, causing short circuits and other problems.

[0004] Based on the above-mentioned technical problems, this application proposes an embedded memory chip testing device. Utility Model Content

[0005] The purpose of this utility model is to provide an embedded memory chip testing device to solve the technical problems mentioned in the background art. This purpose is achieved through the following technical solution:

[0006] An embedded memory chip testing device includes a chip strip, a test socket, and a pressure block. The chip strip is a splice of several chips after being surface-mounted and wire-bonded, and the chips are arranged in an array. The upper surface of the test socket is provided with several connectors, and the connectors correspond one-to-one with the pin pads on the back of the chip strip. The pressure block presses the chip strip onto the test socket, and the pressure block has a cutout window that matches the position of the chip.

[0007] Furthermore, a first positioning hole is provided on the chip strip, a second positioning hole is provided on the pressure block, and a positioning pin is provided on the test seat. The positions of the second positioning hole and the positioning pin match the positions of the first positioning hole.

[0008] Furthermore, the pressure block is a rectangular plate made of carbonitic stainless steel or martensitic stainless steel, and magnets are provided around the upper surface of the test seat.

[0009] Furthermore, the test socket has an opening on its side, in which a card opener is detachably installed. One end of the card opener is electrically connected to the connector, and the other end of the card opener is electrically connected to the test host via a data cable.

[0010] Furthermore, the connector is a flexible pin, and the position and number of the flexible pins match the position and number of the pin pads of the packaged chip.

[0011] The technical solutions provided in this application have at least the following technical effects or advantages:

[0012] By packaging and testing chips after partial wire bonding, it is possible to quickly confirm whether there are any abnormalities in each process before packaging, which greatly accelerates chip testing and verification, shortens the functional verification cycle, and reduces product development risks, as well as ineffective production investment and application risks in the end. Attached Figure Description

[0013] The accompanying drawings, which form part of this application, are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0014] Figure 1 This is a schematic diagram of the structure of an embodiment of this application;

[0015] Figure 2 This is a schematic diagram of the chip strip structure according to an embodiment of this application;

[0016] Figure 3 This is a schematic diagram of the test socket structure in an embodiment of this application;

[0017] Figure 4 This is a schematic diagram of the pressing block structure in an embodiment of this application.

[0018] The following are labeled in the attached diagram: 1. Chip strip; 11. Substrate; 12. Chip; 12a. Packaged chip; 13. First positioning hole; 2. Test socket; 21. Connector; 22. Positioning pin; 23. Insert; 24. Opening plate; 3. Pressing block; 31. Hollow window; 32. Second positioning hole. Detailed Implementation

[0019] To better understand the above technical solutions, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, will illustrate the technical solutions. Obviously, the described embodiments are merely some embodiments of this utility model, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this utility model or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0020] like Figure 1-4An embedded memory chip testing device is shown, including a chip strip 1, a test socket 2, and a pressure block 3. The pressure block 3 presses the chip strip 1 onto the test socket 2 for testing the chip strip 1.

[0021] like Figure 1 , Figure 2 As shown, the chip strip 1 includes a substrate 11 and chips 12. Several chips 12 are arranged in an array on the substrate 11 after being surface-mounted and wire-bonded. Some chips 11 are packaged to become packaged chips 11a.

[0022] Preferably, 100 chips 11 are arranged on each substrate 11, and the 100 chips 11 are distributed in a 5*20 array. Six chips 11 are selected from the four corners and the middle position of the chip strip 1 for encapsulation, resulting in six encapsulated chips 11a. Six first positioning holes 13 are formed on the substrate 11, two of which are located on the upper edge of the substrate 11, and the other four are located on the lower edge of the substrate 11.

[0023] like Figures 1-3 As shown, the test socket 2 is a rectangular shell. Six connectors 21 are mounted on the upper surface of the test socket 2, and the positions of the connectors 21 correspond one-to-one with the positions of the packaged chips 11a. Six positioning pins 22 are vertically mounted on the upper surface of the test socket 2. The positions of the positioning pins 22 match the positions of the first positioning holes 13, and the size of the positioning pins 22 is slightly smaller than the size of the first positioning holes 13, preferably 0.1 mm smaller than the first positioning holes 13.

[0024] like Figure 1 , Figure 3 As shown, the test socket 2 has six ports 23 on its side, each containing a detachable card opener 24. One end of the card opener 24 has pins; when inserted into a port 23, the pins are electrically connected to the connector 21. The other end of the card opener 24 is electrically connected to the test host via a data cable, thus connecting the test host to the connector 21. The card opener 24 is a standard design from the chip manufacturer and can be purchased directly from the market. The data cable connects the card opener to the test host and can use a standard USB 3.0 cable. The test host can be a Windows computer with the test software installed.

[0025] The connector 21 consists of a set of elastic pins. The position and number of the elastic pins are matched with the position and number of the pin pads of the packaged chip 12a. The diameter of the elastic pins needs to be smaller than the pin pad size of the packaged chip 12a. Preferably, the diameter of the elastic pins is 0.2mm.

[0026] like Figure 1 , Figure 4As shown, the pressure block 3 is a rectangular plate made of carbonitic stainless steel or martensitic stainless steel with a thickness of 1mm. The pressure block 3 has a hollow window 31, which is matched with the position of the chip 12 and the packaged chip 12a to avoid damaging the chip 12.

[0027] A magnet is installed on the edge of the upper surface of the test socket 2, and a pressure block 3 is surrounded around the packaged chip 12a to attract the pressure block 3 onto the test socket 2, ensuring a tight fit between the chip strip 1 and the test socket 2 and avoiding any misalignment in the circuit connection.

[0028] The pressure block 3 has a second positioning hole 32, the position and size of which match the position and size of the first positioning hole 13.

[0029] The usage method of this application embodiment is as follows:

[0030] First, install some of the packaged chip strips onto the test socket through the first positioning hole and positioning pin, so that the pin pads of the packaged chip abut against the elastic ejector pin; then, press the pressure block through the second positioning hole and positioning pin; finally, insert the card opening board, connect the card opening board to the test host through the USB cable, and open the corresponding test software to start the test.

[0031] The technical solutions provided in this application have at least the following technical effects or advantages:

[0032] By packaging and testing chips after partial wire bonding, it is possible to quickly confirm whether there are any abnormalities in each process before packaging, which greatly accelerates chip testing and verification, shortens the functional verification cycle, and reduces product development risks, as well as ineffective production investment and application risks in the end.

[0033] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0034] In the description of this utility model, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this utility model and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this utility model. The directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0035] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this utility model.

[0036] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. An embedded memory chip testing device, characterized in that, include: A chip strip, wherein the chip strip is a splice of several chips after being surface-mounted and wire-bonded, and the several chips are distributed in an array; The test socket has several connectors on its upper surface, and each connector corresponds to a pin pad on the back of the chip strip. A pressure block is used to press the chip strip onto the test socket. The pressure block has a cutout window that matches the position of the chip.

2. The embedded memory chip testing device according to claim 1, characterized in that, The chip strip has a first positioning hole, the pressure block has a second positioning hole, and the test seat has a positioning pin. The positions of the second positioning hole and the positioning pin match the positions of the first positioning hole.

3. The embedded memory chip testing device according to claim 1, characterized in that, The pressure block is a rectangular plate made of carbonitic stainless steel or martensitic stainless steel, and magnets are arranged around the upper surface of the test seat.

4. The embedded memory chip testing device according to claim 1, characterized in that, The test socket has a slot on its side, and a card opening plate is detachably installed in the slot. One end of the card opening plate is electrically connected to the connector, and the other end of the card opening plate is electrically connected to the test host via a data cable.

5. The embedded memory chip testing device according to claim 1, characterized in that, The connector is a flexible pin, and the position and number of the flexible pins are matched with the position and number of the pin pads of the packaged chip.

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