Packaging structure
By introducing a double-sided heat dissipation design into the chip packaging structure, and utilizing the flat and vertical plates of the conductive frame to conduct heat, the problem of low heat dissipation efficiency in existing packaging structures is solved, resulting in faster signal transmission and higher device performance.
Patent Information
- Application Number
- CN202422974429.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-12-02
AI Technical Summary
Existing chip packaging structures have low heat dissipation efficiency, which affects chip performance.
An encapsulation structure is adopted, including a lead frame, a chip to be encapsulated, a first conductive frame, a second conductive frame, and a molding layer. The pins of the chip to be encapsulated are electrically connected to the pin portion. Heat is conducted through the flat and vertical plates of the first and second conductive frames to achieve double-sided heat dissipation, and the components are protected by the molding layer.
It improves the heat dissipation efficiency of the packaging structure, enhances signal transmission speed, and improves device performance.
Smart Images
Figure CN223501861U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of packaging technology, and in particular to a packaging structure. Background Technology
[0002] With the development of the 5G industry, consumer electronics, and new energy vehicle industry, higher requirements are being placed on the heat dissipation rate of chips. However, the existing chip packaging structure has low heat dissipation efficiency, which affects chip performance. Utility Model Content
[0003] This invention provides a packaging structure to improve the heat dissipation rate of the packaging structure and improve chip performance.
[0004] According to one aspect of the present invention, a packaging structure is provided, comprising:
[0005] Lead frame, chip to be packaged, first conductive frame, second conductive frame, and molding layer;
[0006] The lead frame includes a main body, a first lead portion, a second lead portion, and a third lead portion; wherein the main body, the first lead portion, the second lead portion, and the third lead portion are located in the same plane;
[0007] The chip to be packaged is disposed on the surface of the main body. The surface of the chip to be packaged away from the main body includes a first pin, at least two second pins, and at least two third pins. Along a first direction, the second pins and third pins are arranged alternately in sequence. The first direction is parallel to one side of the chip to be packaged. The first pin is electrically connected to the first pin portion through a lead wire.
[0008] The first conductive frame includes a first plate, a connecting plate, a second plate, and a first vertical plate connected in sequence; the first plate is disposed on the side of the chip to be packaged away from the main body, and at least two first connecting ends are disposed on the surface of the first plate adjacent to the chip, each first connecting end being electrically connected to a second pin, and the first vertical plate being electrically connected to the second pin portion; the second plate is parallel to the main body; the first plate is also provided with at least two through holes;
[0009] The second conductive frame includes a third plate and a second vertical plate connected in sequence; the third plate is disposed on the side of the first plate away from the main body; at least two second connection terminals are disposed on the surface of the third plate adjacent to the chip to be packaged, each second connection terminal passing through a through hole and electrically connected to the third pin; the second vertical plate is electrically connected to the third pin portion; the third plate and the main body are parallel;
[0010] The molding compound covers the lead frame, the chip to be packaged, the first conductive frame and the second conductive frame, and the surfaces of the first pin portion, the second pin portion and the main body portion away from the chip to be packaged are exposed by the molding compound, and the surfaces of the first plate and the third plate away from the chip to be packaged are exposed by the molding compound.
[0011] Optionally, each second pin is electrically connected to at least two first connection terminals, and the at least two first connection terminals electrically connected to the same second pin are arranged sequentially along the length of the second pin;
[0012] Each third pin is electrically connected to at least two second connection terminals, and the at least two second connection terminals electrically connected to the same third pin are arranged sequentially along the length of the third pin.
[0013] Optionally, the second connecting end and the through hole correspond one-to-one, with one second connecting end passing through each through hole; or, at least two second connecting ends pass through each through hole.
[0014] Optionally, the distance between the edge of the through-hole and the edge of the second connection end passing through the through-hole is greater than or equal to 100 micrometers.
[0015] Optionally, the surfaces of the second plate away from the chip to be packaged and the surfaces of the third plate away from the chip to be packaged are located on the same plane.
[0016] Optionally, heat sinks are provided on the surfaces of the second plate away from the chip to be packaged and the surfaces of the third plate away from the chip to be packaged.
[0017] Optionally, the second pin portion and the third pin portion are disposed on both sides of the main body portion along the first direction;
[0018] The first pin portion and the second pin portion are located on the same side of the main body portion.
[0019] Optionally, the angle between the connecting plate and the first plate is greater than 90 degrees, the first plate and the second plate are parallel to each other, and the first vertical plate and the second plate are perpendicular to each other.
[0020] The third flat plate and the second vertical plate are perpendicular to each other.
[0021] Optionally, along the direction from the chip to be packaged to the first plate, the height of the first connection end is greater than or equal to 200 micrometers and less than or equal to 300 micrometers, and the height of the second connection end is greater than or equal to 500 micrometers and less than or equal to 600 micrometers.
[0022] The thickness of the first plate, the second plate, the third plate, the first vertical plate, and the second vertical plate is greater than or equal to 80 micrometers and less than or equal to 120 micrometers.
[0023] Optionally, the vertical projection of the first connection terminal onto the chip to be packaged is located within the second pin, and the distance between the edge of the vertical projection of the first connection terminal onto the chip to be packaged and the edge of the second pin is greater than or equal to 30 micrometers and less than or equal to 50 micrometers.
[0024] The second connection terminal is located within the third pin in the vertical projection of the chip to be packaged. The distance between the edge of the vertical projection of the second connection terminal on the chip to be packaged and the edge of the third pin is greater than or equal to 30 micrometers and less than or equal to 50 micrometers.
[0025] This embodiment of the invention involves placing a chip to be packaged on the surface of a main body. A first pin of the chip is electrically connected to a first pin portion via a lead, and a second pin is electrically connected to a second pin portion via a first conductive frame. The first conductive frame includes a first flat plate, a connecting plate, a second flat plate, and a first vertical plate connected in sequence. The second flat plate is parallel to the main body. The first flat plate also has at least two through holes. The second conductive frame includes a third flat plate and a second vertical plate connected in sequence. Each second connecting end passes through a through hole and is electrically connected to a third pin. The second vertical plate is electrically connected to the third pin portion. The third flat plate is parallel to the main body. The plastic encapsulation layer is exposed on the surfaces of the chip to be packaged, including the feet, the second pin, and the main body. The first and third plates are also exposed on the surfaces of the chip to be packaged, allowing heat generated by the chip to be packaged to be directly dissipated through the main body. Furthermore, the heat generated by the chip is conducted through the first connector to the first plate, the connector plate, and the second plate, where it is rapidly dissipated. The heat generated by the chip is also conducted through the second connector to the third plate, where it is dissipated. This means that the packaging structure in this embodiment can dissipate heat on both sides, improving heat dissipation while enabling faster interconnect signal transmission and effectively enhancing device performance.
[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a three-dimensional schematic diagram of a packaging structure provided in an embodiment of this utility model.
[0029] Figure 2 This is a front view of a packaging structure provided in an embodiment of this utility model.
[0030] Figure 3 This is another perspective view of the packaging structure provided in this embodiment of the utility model.
[0031] Figure 4 This is a schematic diagram of the chip to be packaged being placed on the lead frame.
[0032] Figure 5 This is a mounting diagram of a packaging structure provided in an embodiment of this utility model.
[0033] Figure 6 This is another perspective view of a packaging structure provided in an embodiment of this utility model.
[0034] Figure 7 This is a front view of another packaging structure provided in this utility model embodiment. Detailed Implementation
[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.
[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0037] This utility model embodiment provides a packaging structure. Figure 1 This is a three-dimensional schematic diagram of a packaging structure provided in an embodiment of the present invention. Figure 2 This is a front view of a packaging structure provided in an embodiment of the present invention. Figure 3 This is another perspective view of the packaging structure provided in this embodiment of the utility model. Figure 4 This is a schematic diagram showing the chip to be packaged mounted on the lead frame. (Refer to...) Figures 1-4 The packaging structure includes:
[0038] Lead frame 10, chip to be packaged 20, first conductive frame 30, second conductive frame 40 and molding layer 50;
[0039] The lead frame 10 includes a main body 11, a first pin portion 12, a second pin portion 13, and a third pin portion 14; wherein the main body 11, the first pin portion 12, the second pin portion 13, and the third pin portion 14 are located on the same plane;
[0040] The chip to be packaged 20 is disposed on the surface of the main body 11. The surface of the chip to be packaged 20 away from the main body 11 includes a first pin 21, at least two second pins 22 and at least two third pins 23. Along a first direction, the second pins 22 and the third pins 23 are arranged alternately in sequence. The first direction is parallel to one side of the chip to be packaged 20. The first pin 21 is electrically connected to the first pin portion 12 through a lead wire.
[0041] The first conductive frame 30 includes a first plate 31, a connecting plate 32, a second plate 33, and a first vertical plate 34 connected in sequence. The first plate 31 is disposed on the side of the chip to be packaged 20 away from the main body 11. At least two first connecting ends 35 are disposed on the surface of the first plate 31 adjacent to the chip. Each first connecting end 35 is electrically connected to a second pin 22. The first vertical plate 34 is electrically connected to the second pin portion 13. The second plate 33 is parallel to the main body 11. The first plate 31 is also provided with at least two through holes 36.
[0042] The second conductive frame 40 includes a third plate 41 and a second vertical plate 42 connected in sequence; the third plate 41 is disposed on the side of the first plate 31 away from the main body 11; at least two second connection ends 43 are disposed on the surface of the third plate 41 adjacent to the chip 20 to be packaged, and each second connection end 43 passes through a through hole 36 and is electrically connected to the third pin 23; the second vertical plate 42 is electrically connected to the third pin portion 14; the third plate 41 is parallel to the main body 11;
[0043] The molding compound 50 covers the lead frame 10, the chip to be packaged 20, the first conductive frame 30 and the second conductive frame 40, and the surfaces of the first pin portion 12, the second pin portion 13 and the main body portion 11 away from the chip to be packaged 20 are exposed by the molding compound 50, and the surfaces of the first plate 31 and the third plate 41 away from the chip to be packaged 20 are exposed by the molding compound 50.
[0044] In this design, the first direction is the length direction of the chip to be packaged 20. Along the length direction of the chip to be packaged 22, the second pin 22 and the third pin 23 are arranged alternately. The chip to be packaged 22 can be a planar gallium nitride chip, and all pins of the planar gallium nitride chip are located on the same plane. The first pin 21 can be the gate pin, the second pin 22 can be the source pin, and the third pin 23 can be the drain pin. The lead frame 10, the first conductive frame 30, and the second conductive frame 40 are all made of conductive materials, such as copper or other metal materials. The first conductive frame 30 and the second conductive frame 40 are insulated from each other. The second connection end 43 of the second conductive frame 40 passes through the through hole 36 on the first conductive frame 30, and the second connection end 43 does not contact the first conductive frame 30.
[0045] The molding compound 50 fills the gaps and surfaces between the lead frame 10, the chip to be packaged 20, the first conductive frame 30, and the second conductive frame 40. The molding compound 50 protects the lead frame 10, the chip to be packaged 20, the first conductive frame 30, and the second conductive frame 40, thus protecting the chip to be packaged 20 from moisture intrusion and ensuring solder joint stability. The molding compound 50 also fills the space between the second connection terminal 43 and the through-hole 36, further ensuring that the first conductive frame 30 and the second conductive frame 40 are mutually insulated and improving the stability of the first conductive frame 30 and the second conductive frame 40.
[0046] The first pin 21 is electrically connected to the first pin portion 12 via a lead wire. The second pin 22 is electrically connected to the second pin portion 13 via the first conductive frame 30. The third pin 23 is electrically connected to the third pin portion 14 via the second conductive frame 40. The first vertical plate 34 can be connected to the second pin portion 13 and the second pin 22 via a soldering material. The second vertical plate 42 can be connected to the third pin portion 14 and the third pin 23 via a soldering material. A plurality of first connecting ends 35 can be provided on the first plate 31, and the first connecting ends 35 can be columnar. Each second pin 22 is electrically connected to one or more first connecting ends 35. A plurality of second connecting ends 43 can also be provided on the third plate 41, and the second connecting ends 43 can be columnar. Each third pin 23 is electrically connected to one or more second connecting ends 43.
[0047] The plastic encapsulation layer 50 is exposed on the surfaces of the main body 11, the first pin 12, the second pin 13, and the third pin 14 that are away from the chip to be packaged 20. The main body 11 is used for heat dissipation, and the first pin 12, the second pin 13, and the third pin 14 are used for connection with external circuits to realize signal interaction between the chip to be packaged 20 and external circuits.
[0048] The second plate 33 of the first conductive frame 30 and the third plate 41 of the second conductive frame 40 expose the molding layer 50 on the surface away from the chip to be packaged 20, so that the heat generated by the chip to be packaged 20 is conducted to the first plate 31, the connecting plate 32 and the second plate 33 through the first connection terminal 35, and is quickly dissipated by the second plate 33. The heat generated by the chip to be packaged 20 is conducted to the third plate 41 through the second connection terminal 43, and is dissipated by the third plate 41.
[0049] In this embodiment of the invention, a chip to be packaged 20 is disposed on the surface of the main body 11. The first pin 21 of the chip to be packaged 20 is electrically connected to the first pin portion 12 via a lead wire. The second pin 22 is electrically connected to the second pin portion 13 via a first conductive frame 30. The first conductive frame 30 includes a first plate 31, a connecting plate 32, a second plate 33, and a first vertical plate 34 connected in sequence. The second plate 33 is parallel to the main body 11. The first plate 31 also has at least two through holes 36. The second conductive frame 40 includes a third plate 41 and a second vertical plate 42 connected in sequence. Each second connecting end 43 passes through a through hole 36 and is electrically connected to the third pin 23. The second vertical plate 42 is electrically connected to the third pin portion 14. The third plate 41 and the main body 11... The first pin portion 12, the second pin portion 13, and the main body portion 11 are parallel to each other, with the plastic encapsulation layer 50 exposed on the surfaces of the chip to be packaged 20 away from the surface of the chip to be packaged 20. The first plate 31 and the third plate 41 are also exposed to the plastic encapsulation layer 50 on the surfaces of the chip to be packaged 20 away from the surface of the chip to be packaged 20. This allows the heat generated by the chip to be packaged 20 to be directly dissipated through the main body portion 11. The heat generated by the chip to be packaged 20 is conducted through the first connection terminal 35 to the first plate 31, the connection plate 32, and the second plate 33, where it is quickly dissipated. The heat generated by the chip to be packaged 20 is conducted through the second connection terminal 43 to the third plate 41, where it is also dissipated. In other words, the packaging structure of this embodiment can dissipate heat on both sides, which improves the heat dissipation effect and allows for faster interconnection signal transmission, effectively improving device performance.
[0050] Optionally, each second pin 22 is electrically connected to at least two first connection terminals 35, and the at least two first connection terminals 35 electrically connected to the same second pin 22 are arranged sequentially along the length direction of the second pin 22;
[0051] Each third pin 23 is electrically connected to at least two second connection terminals 43, and the at least two second connection terminals 43 electrically connected to the same third pin 23 are arranged sequentially along the length of the third pin 23.
[0052] Specifically, each second pin 22 is electrically connected to at least two first connection terminals 35, and each third pin 23 is electrically connected to at least two second connection terminals 43. The molding compound 50 can fill between multiple first connection terminals 35, between multiple second connection terminals 43, and in the gap between the second connection terminals 43 and the through-hole 36, which can further increase the contact area between the first connection terminals 35 and the second connection terminals 43 and the molding compound 50, improve the connection stability between the first connection terminals 35 and the second connection terminals 43 and the chip to be packaged 20, and further improve the packaging reliability.
[0053] Figure 5 This is a mounting diagram of a packaging structure provided in an embodiment of this utility model, for reference. Figure 5 Optionally, the second connecting end 43 and the through hole 36 correspond one-to-one, with one second connecting end 43 passing through each through hole 36; or, at least two second connecting ends 43 pass through each through hole 36.
[0054] Specifically, the second connection terminal 43 can be selected to correspond one-to-one with the through hole 36 or to pass through multiple holes, depending on the size requirements of the third pin 23 and the second connection terminal 43.
[0055] For example, a third pin 23 can be electrically connected to two or more second connection terminals 43, and each second connection terminal 43 corresponds to a through hole 36. This configuration makes the relative position between the second conductive frame 40 and the first conductive frame 30 more stable, resulting in higher reliability of the package structure.
[0056] Optionally, the distance between the edge of the through hole 36 and the edge of the second connection end 43 passing through the through hole 36 is greater than or equal to 100 micrometers.
[0057] Specifically, when the distance between the edge of the through hole 36 and the edge of the second connecting end 43 passing through the through hole 36 is too small, the second connecting end 43 is prone to contact with the through hole 36 when it shifts, causing a short circuit between the first conductive frame 30 and the second conductive frame 40. By setting the distance between the edge of the through hole 36 and the edge of the second connecting end 43 passing through the through hole 36 to be greater than or equal to 100 micrometers, a larger gap is created between the second connecting end 43 and the through hole 36. This prevents the second connecting end 43 from contacting the through hole 36 when it shifts, avoids a short circuit between the first conductive frame 30 and the second conductive frame 40, and avoids compromising the alignment process requirements of the second conductive frame 40 and the first conductive frame 30.
[0058] Figure 6 This is another perspective view of the packaging structure provided in this embodiment of the utility model, see reference. Figure 6 Optionally, the surface of the second plate 33 away from the chip 20 to be packaged and the surface of the third plate 41 away from the chip 20 to be packaged are located on the same plane.
[0059] Specifically, the surfaces of the second plate 33 and the third plate 41 that are away from the chip 20 to be packaged are located on the same plane, which can improve the flatness of the packaging structure and reduce the volume of the packaging structure.
[0060] Figure 7 This is a front view of another packaging structure provided in this embodiment of the utility model. Optional, see reference. Figure 7 Heat sinks 60 are provided on the surface of the second plate 33 away from the chip 20 to be packaged and on the surface of the third plate 41 away from the chip 20 to be packaged.
[0061] Specifically, the function of heat sink 60 is to enhance heat conduction and convection, thereby accelerating heat dissipation. Heat sink 60 can quickly conduct heat from the heat source area of the package structure to the external environment. By placing heat sink 60 on the surfaces of the second plate 33 and the third plate 41 away from the chip surface, heat dissipation efficiency can be improved, the operating temperature of the package structure can be reduced, the lifespan of the internal chip can be extended, and the reliability and stability of the package structure can be improved.
[0062] Optionally, the second pin portion 13 and the third pin portion 14 are disposed on both sides of the main body portion 11 along the first direction;
[0063] The first pin portion 12 and the second pin portion 13 are located on the same side of the main body portion 11.
[0064] Specifically, by placing the pins on both sides of the main body 11, the package space can be effectively utilized, interference between pins can be avoided, and the package density can be increased. Optimizing the pin layout can reduce the overall size of the package structure, making it more compact, and can also simplify the manufacturing process of the package structure, reducing production costs. A reasonable pin layout can distribute the stress during pin connection, reducing the risk of pin breakage or connection failure due to stress concentration. A reasonable pin layout can also help with heat dissipation by guiding airflow or providing heat dissipation channels to reduce the operating temperature of the package structure.
[0065] Optionally, the angle between the connecting plate 32 and the first plate 31 is greater than 90 degrees, the first plate 31 and the second plate 33 are parallel to each other, and the first vertical plate 34 and the second plate 33 are perpendicular to each other.
[0066] The third flat plate 41 and the second vertical plate 42 are perpendicular to each other.
[0067] Specifically, since the angle between the connecting plate 32 and the first plate 31 is greater than 90 degrees, more installation space can be provided for other components within a limited space, making the connection between components such as the connecting plate 32, the first plate 31, and the second plate 33 more stable and helping to improve the strength of the entire packaging structure. The vertical and parallel structural relationship helps to maintain the stability of the packaging structure. By adjusting the angle and positional relationship between the plates, the heat dissipation path can be designed more effectively, improving the heat dissipation performance of the packaging structure and allowing heat to be transferred to the external environment more quickly.
[0068] Optionally, along the direction from the chip to be packaged 20 to the first plate 31, the height of the first connection end 35 is greater than or equal to 200 micrometers and less than or equal to 300 micrometers, and the height of the second connection end 43 is greater than or equal to 500 micrometers and less than or equal to 600 micrometers.
[0069] The thickness of the first plate 31, the second plate 33, the third plate 41, the first vertical plate 34, and the second vertical plate 42 is greater than or equal to 80 micrometers and less than or equal to 120 micrometers.
[0070] Specifically, setting the thickness of the first plate 31, the second plate 33, the third plate 41, the first vertical plate 34, and the second vertical plate 42 to be greater than or equal to 80 micrometers and less than or equal to 120 micrometers can improve the structural strength of the first plate 31, the second plate 33, the third plate 41, the first vertical plate 34, and the second vertical plate 42, enabling them to withstand certain external pressure and vibration, improving packaging reliability. Furthermore, the appropriate plate thickness helps to achieve uniform heat distribution and rapid heat conduction, thereby improving the heat dissipation performance of the packaging structure. By limiting the thickness of the first plate 31, the second plate 33, the third plate 41, the first vertical plate 34, and the second vertical plate 42, as well as the height of the first connecting end 35 and the second connecting end 43, it is possible to achieve higher packaging density and integration within a limited space, reduce interference and conflicts between components, and make the layout of various components within the entire packaging structure more reasonable. While ensuring high signal transmission reliability and high heat dissipation speed, it also allows for a smaller packaging structure.
[0071] Optionally, the vertical projection of the first connection terminal 35 onto the chip to be packaged 20 is located within the second pin 22, and the distance between the edge of the vertical projection of the first connection terminal 35 onto the chip to be packaged 20 and the edge of the second pin 22 is greater than or equal to 30 micrometers and less than or equal to 50 micrometers.
[0072] The vertical projection of the second connection terminal 43 onto the chip to be packaged 20 is located within the third pin 23. The distance between the edge of the vertical projection of the second connection terminal 43 onto the chip to be packaged 20 and the edge of the third pin 23 is greater than or equal to 30 micrometers and less than or equal to 50 micrometers.
[0073] Specifically, the vertical projection of the first connection terminal 35 onto the chip to be packaged 20 is located within the second pin 22, resulting in a large contact area between the first connection terminal 35 and the second pin 22, ensuring connection stability and signal transmission stability. If the distance between the edge of the vertical projection of the first connection terminal 35 onto the chip to be packaged 20 and the edge of the second pin 22 is too small, the alignment accuracy requirement when placing the first conductive frame 30 onto the chip to be packaged 20 becomes excessively high. By setting the distance between the edge of the vertical projection of the first connection terminal 35 onto the chip to be packaged 20 and the edge of the second pin 22 to be greater than or equal to 30 micrometers and less than or equal to 50 micrometers, the alignment accuracy requirement can be reduced, thus lowering process costs.
[0074] The second connection terminal 43, when projected vertically onto the chip 20 to be packaged, lies within the third pin 23, providing a large contact area between them and ensuring connection and signal transmission stability. If the distance between the edge of the vertical projection of the second connection terminal 43 onto the chip 20 and the edge of the third pin 23 is too small, the alignment accuracy requirement when placing the second conductive frame 40 onto the chip 20 becomes excessively high. By setting the distance between the edge of the vertical projection of the second connection terminal 43 onto the chip 20 and the edge of the third pin 23 to be greater than or equal to 30 micrometers and less than or equal to 50 micrometers, the alignment accuracy requirement can be reduced, thus lowering process costs.
[0075] The packaging process of the chip to be packaged is described below with reference to the accompanying drawings:
[0076] refer to Figures 4-7 When encapsulating the chip 20, the chip 20 is first placed on the surface of the main body 11. Then, a first conductive frame 30 is placed on the surface of the chip 20, electrically connecting the first connection terminal 35 and the first pin 22, and electrically connecting the first vertical portion 34 and the second pin portion 13. Next, a second conductive frame 40 is placed on the side of the first conductive frame 30 away from the chip 20. The second connection terminal 43 of the second conductive frame 40 passes through the through hole 36 and is electrically connected to the third pin 23. The second vertical plate 42 is electrically connected to the third pin portion 14. Finally, a molding compound 50 is applied, which can be made of resin or the like.
[0077] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.
[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.
Claims
1. A packaging structure, characterized in that, include: Lead frame, chip to be packaged, first conductive frame, second conductive frame, and molding layer; The lead frame includes a main body, a first pin portion, a second pin portion, and a third pin portion; wherein the main body, the first pin portion, the second pin portion, and the third pin portion are located on the same plane; The chip to be packaged is disposed on the surface of the main body portion. The surface of the chip to be packaged away from the main body portion includes a first pin, at least two second pins, and at least two third pins. Along a first direction, the second pins and the third pins are arranged alternately in sequence. The first direction is parallel to one side of the chip to be packaged. The first pin is electrically connected to the first pin portion through a lead wire. The first conductive frame includes a first plate, a connecting plate, a second plate, and a first vertical plate connected in sequence; the first plate is disposed on the side of the chip to be packaged away from the main body, and at least two first connecting ends are disposed on the surface of the first plate adjacent to the chip, each first connecting end being electrically connected to a second pin, and the first vertical plate being electrically connected to the second pin portion; the second plate is parallel to the main body; the first plate is also provided with at least two through holes; The second conductive frame includes a third plate and a second vertical plate connected in sequence; the third plate is disposed on the side of the first plate away from the main body; the surface of the third plate adjacent to the chip to be packaged is provided with at least two second connection terminals, each of the second connection terminals passing through a through hole and electrically connected to the third pin; the second vertical plate is electrically connected to the third pin portion; the third plate and the main body are parallel. The molding compound covers the lead frame, the chip to be packaged, the first conductive frame, and the second conductive frame, with the first pin portion, the second pin portion, and the main body portion having their surfaces exposed away from the chip to be packaged, and the first plate and the third plate having their surfaces exposed away from the chip to be packaged, also having their surfaces exposed away from the chip to be packaged, all of which are part of the molding compound.
2. The packaging structure according to claim 1, characterized in that: Each of the second pins is electrically connected to at least two first connection terminals, and the at least two first connection terminals electrically connected to the same second pin are arranged sequentially along the length of the second pin. Each of the third pins is electrically connected to at least two second connection terminals, and the at least two second connection terminals electrically connected to the same third pin are arranged sequentially along the length of the third pin.
3. The packaging structure according to claim 2, characterized in that: The second connecting end and the through hole correspond one-to-one, with one second connecting end passing through each through hole; or, at least two second connecting ends passing through each through hole.
4. The packaging structure according to claim 1, characterized in that: The distance between the edge of the through hole and the edge of the second connection end passing through the through hole is greater than or equal to 100 micrometers.
5. The packaging structure according to claim 1, characterized in that: The surface of the second plate away from the chip to be packaged and the surface of the third plate away from the chip to be packaged are located on the same plane.
6. The packaging structure according to claim 1, characterized in that: Heat sinks are provided on the surface of the second plate away from the chip to be packaged and on the surface of the third plate away from the chip to be packaged.
7. The packaging structure according to claim 1, characterized in that: The second pin portion and the third pin portion are disposed on both sides of the main body portion along the first direction; The first pin portion and the second pin portion are located on the same side of the main body portion.
8. The packaging structure according to claim 1, characterized in that: The angle between the connecting plate and the first plate is greater than 90 degrees, the first plate and the second plate are parallel to each other, and the first vertical plate and the second plate are perpendicular to each other. The third flat plate and the second vertical plate are perpendicular to each other.
9. The packaging structure according to claim 1, characterized in that: Along the direction from the chip to be packaged to the first plate, the height of the first connection end is greater than or equal to 200 micrometers and less than or equal to 300 micrometers, and the height of the second connection end is greater than or equal to 500 micrometers and less than or equal to 600 micrometers. The thickness of the first plate, the second plate, the third plate, the first vertical plate, and the second vertical plate is greater than or equal to 80 micrometers and less than or equal to 120 micrometers.
10. The packaging structure according to claim 1, characterized in that: The first connection terminal is located within the second pin in the vertical projection of the chip to be packaged, and the distance between the edge of the vertical projection of the first connection terminal on the chip to be packaged and the edge of the second pin is greater than or equal to 30 micrometers and less than or equal to 50 micrometers. The second connection terminal is located within the third pin in the vertical projection of the chip to be packaged, and the distance between the edge of the vertical projection of the second connection terminal on the chip to be packaged and the edge of the third pin is greater than or equal to 30 micrometers and less than or equal to 50 micrometers.