Inverter topology circuit

Abstract

The utility model discloses an inverter topology circuit which is characterized in that the positive electrode of a first capacitor is connected with one end of a first inductor, the other end of the first inductor is connected with the drain electrode of a first power tube, the source electrode of the first power tube is connected with the drain electrode of a third power tube, and the source electrode of the third power tube is connected with the negative electrode of the first capacitor; the positive electrode of the first capacitor is further connected with one end of a second inductor, the other end of the second inductor is connected with the drain electrode of a second power tube, the source electrode of the second power tube is connected with the drain electrode of a fourth power tube, and the source electrode of the fourth power tube is connected with the negative electrode of the first capacitor. According to the utility model, the inductor is added in the full-bridge inverter topology, so that the power tube is switched on under the zero-current condition, and the switching loss of the power tube is effectively reduced; the inductor is connected in parallel with the diode and the resistor, so that the inductor energy can be consumed to prepare for next soft switching when the inductor does not work, and the peak voltage can be absorbed, the stress of the device can be reduced and the power tube can be protected when the power tube is turned off.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, and in particular to an inverter topology circuit. Background Technology

[0002] With continuous economic development, people are using electrical appliances more and more frequently, and power electronics, as the technological foundation for the development of electrical appliances, is becoming increasingly mature. Due to the increasing electricity consumption, inverters, as energy-saving products, have emerged, and the full-bridge inverter topology plays a crucial role in inverters. This technology converts direct current (DC) into alternating current (AC), which is then directly supplied to the user. Existing full-bridge inverter circuits use a paired-transistor switching method for energy flow. This method first turns on two diagonally opposite power transistors, at which point part of the DC energy is stored at the inductor terminal and part is supplied to the load; then, one power transistor is turned off. During the turning-off process, because the voltage and current changes are not instantaneous but rather involve a rise and fall, there is an overlap region between voltage and current, resulting in losses. Therefore, the system's operating efficiency is low. The switching losses of power devices are also significant, leading to a short service life and easy damage to the power devices. Utility Model Content

[0003] The purpose of this invention is to solve the problem of high power device losses in the prior art.

[0004] The technical solution adopted by this utility model to solve its technical problem is: to provide an inverter topology circuit, including a first capacitor, a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a first inductor, a second inductor, and a third inductor;

[0005] The positive and negative terminals of the first capacitor are connected to the positive and negative terminals of the power supply, respectively. The positive terminal of the first capacitor is connected to one end of the first inductor, and the other end of the first inductor is connected to the drain of the first power transistor. The source of the first power transistor is connected to the drain of the third power transistor, and the source of the third power transistor is connected to the negative terminal of the first capacitor. The positive terminal of the first capacitor is also connected to one end of the second inductor, and the other end of the second inductor is connected to the drain of the second power transistor. The source of the second power transistor is connected to the drain of the fourth power transistor, and the source of the fourth power transistor is connected to the negative terminal of the first capacitor. The source of the first power transistor is connected to one end of the third inductor, and the other end of the third inductor is connected to one end of the load. The other end of the load is connected to the source of the second power transistor.

[0006] Preferably, a first resistor and a first diode are connected in parallel across the two ends of the first inductor.

[0007] Preferably, the end of the first inductor connected to the first capacitor is designated as terminal A of the first inductor, and the end of the first inductor connected to the first power transistor is designated as terminal B of the first inductor; terminal A of the first inductor is connected to one end of the first resistor, the other end of the first resistor is connected to the negative terminal of the first diode, and the positive terminal of the first diode is connected to terminal B of the first inductor.

[0008] Preferably, a second resistor and a second diode are connected in parallel across the two ends of the second inductor.

[0009] Preferably, the end of the second inductor connected to the first capacitor is used as the C terminal of the second inductor, and the end of the second inductor connected to the second power transistor is used as the D terminal of the first inductor; the C terminal of the first inductor is connected to one end of the second resistor, the other end of the second resistor is connected to the negative terminal of the second diode, and the positive terminal of the second diode is connected to the D terminal of the second inductor.

[0010] This utility model has the following beneficial effects:

[0011] (1) This utility model adds a soft-switching circuit to the full-bridge inverter topology. Due to the hysteresis effect of the inductor on the current, the power transistor turns on under zero current conditions, which can effectively reduce the switching loss of the power transistor and improve the system operating efficiency.

[0012] (2) The present invention connects a diode and a resistor in parallel with the inductor, which can consume the inductor energy when the inductor is not working to prepare for the next soft switch, and absorb the peak voltage when the power transistor is turned off, reduce the stress on the device, and protect the power transistor.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments, but the present invention is not limited to the embodiments. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of an embodiment of the present utility model;

[0015] Figure 2 This is a schematic diagram of the first mode of an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the second mode of an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of the third mode of an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of the fourth mode of an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of the fifth mode of an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of the sixth mode of an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of the seventh mode of an embodiment of the present invention;

[0022] Figure 9 This is a schematic diagram of the eighth mode of an embodiment of the present invention. Detailed Implementation

[0023] To reduce system losses and improve system operating efficiency, this invention adds diodes, inductors, and resistors to the full-bridge inverter topology. Connecting the inductor in series before the power transistor creates a zero-current turn-on condition for the transistor, and the diode then dissipates the inductor's energy, preparing for the next turn-on. When the power transistor is turned off, the diodes and resistors also absorb voltage spikes, protecting the device. Therefore, this topology effectively reduces power transistor switching losses and improves system operating efficiency.

[0024] This embodiment of the utility model includes four power transistors, a buffer inductor connected in series with the power transistors, a bus capacitor, a freewheeling diode, and a resistor. See details below. Figure 1 As shown, it includes a first capacitor C1 (bus capacitor), a first power transistor Q1, a second power transistor Q2, a third power transistor Q3, a fourth power transistor Q4, a first inductor L1 (buffer inductor), a second inductor L2 (buffer inductor), and a third inductor L3.

[0025] The positive and negative terminals of the first capacitor C1 are connected to the positive and negative terminals of the power supply, respectively. The positive terminal of the first capacitor C1 is connected to one end of the first inductor L1, and the other end of the first inductor L1 is connected to the drain of the first power transistor Q1. The source of the first power transistor Q1 is connected to the drain of the third power transistor Q3, and the source of the third power transistor Q3 is connected to the negative terminal of the first capacitor C1. The positive terminal of the first capacitor C1 is also connected to one end of the second inductor L2, and the other end of the second inductor L2 is connected to the drain of the second power transistor Q2. The source of the second power transistor Q2 is connected to the drain of the fourth power transistor Q4, and the source of the fourth power transistor Q4 is connected to the negative terminal of the first capacitor C1. The source of the first power transistor Q1 is connected to one end of the third inductor L3, and the other end of the third inductor L3 is connected to one end of the load. The other end of the load is connected to the source of the second power transistor Q2.

[0026] The end of the first inductor L1 connected to the first capacitor C1 is taken as the A terminal of the first inductor L1, and the end of the first inductor L1 connected to the first power transistor Q1 is taken as the B terminal of the first inductor L1; the A terminal of the first inductor L1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the negative terminal of the first diode D1, and the positive terminal of the first diode D1 is connected to the B terminal of the first inductor L1.

[0027] The end of the second inductor L2 connected to the first capacitor C1 is taken as the C terminal of the second inductor L2, and the end of the second inductor L2 connected to the second power transistor Q2 is taken as the D terminal of the first inductor L1; the C terminal of the first inductor L1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the negative terminal of the second diode D2, and the positive terminal of the second diode D2 is connected to the D terminal of the second inductor L2.

[0028] This utility model embodiment has eight working modes during operation, see [link to documentation]. Figures 2 to 9 As shown, the corresponding operating modes are:

[0029] First operating mode: Power transistors Q1 and Q4 are turned on, while the remaining power transistors are turned off. Current flows through the positive bus, the first inductor L1, the first power transistor Q1, the third inductor L3, the fourth power transistor Q4, and the negative bus. The DC terminal provides energy to the first inductor L1, the third inductor L3, and the load. Due to the effect of the first inductor L1, the first power transistor Q1 is turned on when there is zero current.

[0030] Second operating mode: The fourth power transistor Q4 is turned on, and the other power transistors are turned off. The current flows through the fourth power transistor Q4 and freewheels through the body diode of the third power transistor. At this time, the third inductor L3 provides energy to the load, and the first resistor R1 releases energy to the first inductor L1 through the first diode D1, creating conditions for the zero-current conduction of the first power transistor Q1.

[0031] Third operating mode: The first power transistor Q1 is turned on, and the other power transistors are turned off. The current flows through the first inductor L1, the first power transistor Q1, the third inductor L3, and the second inductor L2, and freewheels through the body diode of the second power transistor Q2. At this time, the load and the first resistor R1 simultaneously release energy for the first inductor L1, and the load releases energy for the third inductor L3.

[0032] Fourth operating mode: The first power transistor Q1 and the second power transistor Q2 are turned on, while the other power transistors are turned off. Current flows through the first inductor L1, the first power transistor Q1, the third inductor L3, the second power transistor Q2, and the second inductor L2. At this time, the load and the first resistor R1 simultaneously release energy for the first inductor L1, and the load releases energy for the third inductor L3.

[0033] Fifth operating mode: The second power transistor Q2 and the third power transistor are turned on, while the remaining power transistors are turned off. Current flows through the positive bus, the second inductor L2, the second power transistor Q2, the third inductor L3, the third power transistor, and the negative bus. The DC terminal provides energy to the second inductor L2, the third inductor L3, and the load. Due to the effect of the second inductor L2, the second power transistor Q2 is turned on when there is zero current.

[0034] The sixth operating mode: the third power transistor Q3 is turned on, the other power transistors are turned off, and the current flows through the third power transistor Q3 and freewheeling through the body diode of the fourth power transistor Q4. At this time, the third inductor L3 provides energy to the load, and the second resistor R2 releases energy to the second inductor L2 through the second diode D2, creating conditions for the zero-current conduction of the second power transistor Q2.

[0035] Seventh operating mode: The second power transistor Q2 is turned on, and the other power transistors are turned off. The current flows through the second inductor L2, the second power transistor Q2, the third inductor L3, and the first inductor L1. The current freewheels through the body diode of the first power transistor Q1. At this time, the load and the second resistor R2 simultaneously release energy for the second inductor L2, and the load releases energy for the third inductor L3.

[0036] Eighth operating mode: The first power transistor Q1 and the second power transistor Q2 are turned on, while the other power transistors are turned off. Current flows through the second inductor L2, the second power transistor Q2, the third inductor L3, the first power transistor Q1, and the first inductor L1. At this time, the load and the second resistor R2 simultaneously release energy for the second inductor L2, and the load releases energy for the third inductor L3.

[0037] In this embodiment, during the first and fifth operating modes, the third inductor L3 stores energy; in other operating modes, the third inductor L3 releases energy. This inductor allows the load to operate continuously, avoiding power outages during mode switching. The system has high operating efficiency, reliable device protection measures, and provides continuous and uninterrupted energy to the load.

[0038] As can be seen, this invention adds a soft-switching circuit to the full-bridge inverter topology. Due to the hysteresis effect of the inductor on current, the power transistor turns on under zero-current conditions, which can effectively reduce the switching losses of the power transistor and improve the system operating efficiency. Connecting a diode and resistor in parallel with the inductor can both dissipate the inductor's energy when the inductor is not working to prepare for the next soft switching, and absorb peak voltage when the power transistor is turned off, reducing device stress and protecting the power transistor.

[0039] The above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. An inverter topology circuit, characterized in that, It includes a first capacitor, a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a first inductor, a second inductor, and a third inductor; The positive and negative terminals of the first capacitor are connected to the positive and negative terminals of the power supply, respectively. The positive terminal of the first capacitor is connected to one end of the first inductor, and the other end of the first inductor is connected to the drain of the first power transistor. The source of the first power transistor is connected to the drain of the third power transistor, and the source of the third power transistor is connected to the negative terminal of the first capacitor. The positive terminal of the first capacitor is also connected to one end of the second inductor, and the other end of the second inductor is connected to the drain of the second power transistor. The source of the second power transistor is connected to the drain of the fourth power transistor, and the source of the fourth power transistor is connected to the negative terminal of the first capacitor. The source of the first power transistor is connected to one end of the third inductor, and the other end of the third inductor is connected to one end of the load. The other end of the load is connected to the source of the second power transistor.

2. The inverter topology circuit according to claim 1, characterized in that, A first resistor and a first diode are connected in parallel across the two ends of the first inductor.

3. The inverter topology circuit according to claim 2, characterized in that, The end of the first inductor connected to the first capacitor is designated as terminal A of the first inductor, and the end of the first inductor connected to the first power transistor is designated as terminal B of the first inductor. Terminal A of the first inductor is connected to one end of the first resistor, the other end of the first resistor is connected to the negative terminal of the first diode, and the positive terminal of the first diode is connected to terminal B of the first inductor.

4. The inverter topology circuit according to claim 1, characterized in that, A second resistor and a second diode are connected in parallel across the two ends of the second inductor.

5. The inverter topology circuit according to claim 4, characterized in that, The end of the second inductor connected to the first capacitor is taken as the C terminal of the second inductor, and the end of the second inductor connected to the second power transistor is taken as the D terminal of the first inductor; the C terminal of the first inductor is connected to one end of the second resistor, the other end of the second resistor is connected to the negative terminal of the second diode, and the positive terminal of the second diode is connected to the D terminal of the second inductor.

Images