Switching circuit

Abstract

The utility model discloses a switching circuit, which comprises a first metal oxide semiconductor (MOS) tube and a second MOS tube, the control end of the first MOS tube is connected with a first control node, and the control end of the second MOS tube is connected with the collector of a third transistor; the emitter of the first transistor is connected with the first control node, the base of the second transistor is connected with the collector of the first transistor, the emitter is connected with the second control node, the collector is connected with the base of the third transistor, and the emitter of the third transistor is connected with the second control node. In the first state, the first control node is connected with a reference potential; in the second state, the first control node and the second control node are connected with the reference potential; and in the third state, the second control node is connected with the reference potential. On-off of the two switch units is controlled based on control of the connection relation between the first control node and the reference potential and between the second control node and the reference potential, load power supply is switched, and mistaken opening of the second switch unit is prevented based on the delay unit.

Description

Technical Field

[0001] This utility model belongs to the field of control circuit technology, specifically relating to a switching circuit. Background Technology

[0002] The switching circuit is part of the vehicle lighting control circuit and is used to control the switching of vehicle lights. Existing switching circuits, due to their simple structure, usually use only one MOSFET as the switching transistor, which cannot realize the control logic to power two loads. Moreover, the circuit is prone to false triggering and the power supply switching control of the load is not stable enough.

[0003] Therefore, it is necessary to provide a switching circuit to address the aforementioned technical problems. Utility Model Content

[0004] The purpose of this invention is to provide a switching circuit that can solve the problems of unstable switching control and accidental switch activation.

[0005] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows:

[0006] A switching circuit, the switching circuit comprising:

[0007] The first switching unit includes a first MOSFET, the first terminal of which is connected to the power supply voltage, the second terminal of which is connected to the first output node, and the control terminal of which is connected to the first control node.

[0008] The control unit includes a first transistor, a second transistor, a third transistor, and a delay unit. The base of the first transistor is connected to a power supply voltage, the collector is connected to the base of the second transistor, and the emitter is connected to a first control node. The base of the second transistor is connected to a power supply voltage, the emitter is connected to a second control node, and the collector is connected to the base of the third transistor. The emitter of the third transistor is connected to the second control node, and the collector generates a control signal. The delay unit includes a first delay device connected between the base and emitter of the second transistor and a second delay device connected between the base and emitter of the third transistor. The third transistor is delayed in turning on after the second transistor.

[0009] The second switching unit includes a second MOS transistor. The first terminal of the second MOS transistor is connected to the power supply voltage, the second terminal is connected to the second output node, and the control terminal is connected to the collector of the third transistor and receives the control signal.

[0010] In the first state, the first control node is connected to the reference potential, and the first MOS transistor is turned on;

[0011] In the second state, the first control node and the second control node are connected to the reference potential, and the first MOSFET and the second MOSFET are turned on.

[0012] In the third state, the second control node is connected to the reference potential, and the first MOSFET and the second MOSFET are turned off.

[0013] In one or more embodiments of this utility model, the control unit further includes a first capacitor and a first voltage divider circuit; wherein,

[0014] The first terminal of the first capacitor is connected to the base of the first transistor, and the second terminal is connected to the first control node;

[0015] The first voltage divider circuit is connected between the power supply voltage and the first control node, and is used to generate a first voltage divider voltage based on the power supply voltage. The base of the first transistor receives the first voltage divider voltage.

[0016] In one or more embodiments of the present invention, the first delay device includes a second capacitor, the first end of the second capacitor being connected to the base of the second transistor, and the second end being connected to the second control node;

[0017] The second delay device includes a third capacitor, the first terminal of which is connected to the base of a third transistor, and the second terminal of which is connected to a second control node;

[0018] The capacitance of the second capacitor is less than that of the third capacitor.

[0019] In one or more embodiments of the present invention, the control unit includes a second voltage divider circuit, the second voltage divider circuit including at least two voltage divider resistors connected in series between the power supply voltage and the second control node, for generating a second voltage divider voltage based on the power supply voltage, and the base of the second transistor receiving the second voltage divider voltage.

[0020] In one or more embodiments of the present invention, the control unit further includes a first voltage regulator unit connected between the collector of the first transistor and the base of the second transistor.

[0021] In one or more embodiments of the present invention, the first voltage regulator unit includes a first diode and a second diode. The cathode of the first diode is connected to the collector of the first transistor, and the anode is connected to the anode of the second diode. The anode of the second diode is directly or indirectly connected to the power supply voltage, and the cathode is connected to the base of the second transistor.

[0022] In one or more embodiments of the present invention, the control unit includes a third voltage divider circuit connected between the power supply voltage and the second control node, for generating a third voltage divider voltage based on the power supply voltage, and the base of the third transistor receives the third voltage divider voltage.

[0023] In one or more embodiments of the present invention, the first switching unit further includes a second voltage regulator unit. The second voltage regulator unit includes a first Zener diode, a first resistor, a second resistor, and a fourth capacitor. The anode of the first Zener diode, the second terminal of the first resistor, the second terminal of the fourth capacitor, and the first terminal of the second resistor are all connected to the control terminal of the first MOSFET. The cathode of the first Zener diode, the first terminal of the first resistor, and the first terminal of the fourth capacitor are all connected to the power supply voltage. The second terminal of the second resistor is connected to the first control node.

[0024] In one or more embodiments of the present invention, the second switching unit further includes a third voltage regulator unit, the third voltage regulator unit including a second Zener diode, a third resistor, a fourth resistor and a fifth capacitor, the anode of the second Zener diode, the second terminal of the third resistor, the second terminal of the fifth capacitor and the first terminal of the fourth resistor are all connected to the control terminal of the second MOS transistor, the cathode of the second Zener diode, the first terminal of the third resistor and the first terminal of the fifth capacitor are all connected to the power supply voltage, and the second terminal of the fourth resistor is connected to the collector of the third transistor.

[0025] In one or more embodiments of the present invention, the switching circuit further includes a reverse connection protection unit, which is connected between the input voltage and the power supply voltage and includes a third Zener diode, several filter resistors, a third diode and a fourth diode.

[0026] The third Zener diode is connected between the input voltage and ground voltage. The filter resistor is connected between the input voltage and ground voltage. The anode of the third diode is connected to the input voltage, and the cathode is connected to the power supply voltage. The anode of the fourth diode is connected to the input voltage, and the cathode is connected to the power supply voltage.

[0027] Compared with the prior art, the switching circuit of this utility model controls the conduction and cutoff of the first switching unit and the second switching unit based on the connection relationship between the first control node and the second control node and the reference potential, thereby achieving the effect of switching the power supply to the load.

[0028] This invention uses a delay unit to control the third transistor to turn on later than the second transistor, thereby preventing the second MOS transistor from turning on erroneously and thus preventing the second switching unit from turning on erroneously in a transient state, protecting the downstream load circuit. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a structural diagram of the switching circuit in one embodiment of the present invention;

[0031] Figure 2 This is a structural diagram of the first switching unit and the reverse connection protection unit of the switching circuit in one embodiment of the present invention;

[0032] Figure 3 This is a structural diagram of the second switching unit and control unit of the switching circuit in one embodiment of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0034] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0035] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0036] like Figure 1 , Figure 2 and Figure 3As shown, the switching circuit in one embodiment of the present invention includes a first switching unit 10, a control unit 20, a second switching unit 30, and a reverse connection protection unit 40.

[0037] The first switching unit 10 includes a first MOSFET M1. The first terminal of the first MOSFET M1 is connected to the power supply voltage VCC, and the second terminal is connected to the first output node VBAT1. The control terminal of the first MOSFET M1 is connected to the first control node LB-. In one embodiment, the first output node VBAT1 is connected to a first load. In another embodiment, the first MOSFET M1 is a P-channel MOSFET M1, with its first terminal being the source, its second terminal being the drain, and its control terminal being the gate.

[0038] The control unit 20 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, and a delay unit. The base of the first transistor Q1 is directly or indirectly connected to the power supply voltage VCC, its collector is directly or indirectly connected to the base of the second transistor Q2, and its emitter is connected to the first control node LB-. The base of the second transistor Q2 is directly or indirectly connected to the power supply voltage VCC, its emitter is connected to the second control node HB-, and its collector is connected to the base of the third transistor Q3. The emitter of the third transistor Q3 is connected to the second control node HB-, and its collector generates a control signal S1. The delay unit includes a first delay device connected between the base and emitter of the second transistor Q2 and a second delay device connected between the base and emitter of the third transistor Q3. The delay unit controls the third transistor Q3 to turn on later than the second transistor Q2.

[0039] In one embodiment, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all NPN transistors.

[0040] The second switching unit 30 includes a second MOSFET M2. The first terminal of the second MOSFET M2 is connected to the power supply voltage VCC, the second terminal is connected to the second output node VBAT2, and the control terminal is connected to the collector of the third transistor Q3 and receives the control signal S1. In one embodiment, the second output node VBAT2 is connected to a second load.

[0041] In one embodiment, the second MOS transistor M2 is a P-channel MOS transistor M2, and the first terminal of the second MOS transistor M2 is the source, the second terminal is the drain, and the control terminal is the gate.

[0042] In the first state, the first control node LB- is connected to the reference potential, the first MOSFET M1 is turned on, and the power supply voltage VCC supplies power to the first load through the first output node VBAT1. It is understood that the reference potential in this application can be ground voltage GND.

[0043] In the second state, the first control node LB- and the second control node HB- are connected to the reference potential, the first MOSFET M1 and the second MOSFET M2 are turned on, and the power supply voltage VCC supplies power to the first load and the second load respectively through the first output node VBAT1 and the second output node VBAT2.

[0044] In the third state, the second control node HB- is connected to the reference potential, the first MOSFET M1 and the second MOSFET M2 are turned off, and the power supply voltage VCC is disconnected from the first load and the second load.

[0045] In other embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 can be PNP transistors, and the first MOS transistor M1 and the second MOS transistor M2 can be N-channel MOS transistors, in which case the connection method of the above devices can be adapted.

[0046] like Figure 2 As shown, in one embodiment, the first switching unit 10 further includes a second voltage regulating unit 11.

[0047] The second voltage regulator unit includes a first Zener diode Z1, a first resistor R1, a second resistor R2, and a fourth capacitor C4. The anode of the first Zener diode Z1, the second terminal of the first resistor R1, the second terminal of the fourth capacitor C4, and the first terminal of the second resistor R2 are all connected to the control terminal of the first MOSFET M1. The cathode of the first Zener diode Z1, the first terminal of the first resistor R1, and the first terminal of the fourth capacitor C4 are all connected to the power supply voltage VCC and the first terminal of the first MOSFET M1. The second terminal of the second resistor R2 is connected to the first control node LB-. In one embodiment, the first Zener diode Z1 is a Zener diode. The first Zener diode Z1, the first resistor R1, the second resistor R2, and the fourth capacitor C4 all serve to stabilize the voltage.

[0048] like Figure 3 As shown, in one embodiment, the first delay device includes a second capacitor C2, and the second delay device includes a third capacitor C3. The first terminal of the second capacitor C2 is connected to the base of the second transistor Q2, and the second terminal is connected to the second control node HB-. The first terminal of the third capacitor C3 is connected to the base of the third transistor Q3, and the second terminal is connected to the second control node HB-.

[0049] Furthermore, the capacitance of the second capacitor C2 is smaller than that of the third capacitor C3. This application utilizes the charging and discharging rates of the second capacitor C2 and the third capacitor C3 to adjust the conduction sequence of the second transistor Q2 and the third transistor Q3, causing the third transistor Q3 to conduct later than the second transistor. Preferably, the capacitance of the third capacitor C3 is 100 times that of the second capacitor C2; for example, the value of the third capacitor C3 is 1uF, and the value of the second capacitor C2 is 10nF.

[0050] like Figure 3 As shown, in one embodiment, the control unit 20 further includes a first capacitor C1, a first voltage divider circuit 21, a second voltage divider circuit, a first voltage regulator unit 22, and a third voltage divider circuit 23. Further, in one embodiment, the capacitance of the first capacitor C1 is equal to the capacitance of the second capacitor C2.

[0051] The first terminal of the first capacitor C1 is connected to the base of the first transistor Q1, and the second terminal is connected to the first control node LB-.

[0052] The first voltage divider circuit 21 is connected between the power supply voltage VCC and the first control node LB-, and is used to generate a first voltage divider voltage based on the power supply voltage VCC. The base of the first transistor Q1 receives the first voltage divider voltage.

[0053] The first voltage divider circuit 21 includes at least two voltage divider resistors connected in series between the power supply voltage VCC and the first control node LB-. Preferably, the first voltage divider circuit 21 has two voltage divider resistors, namely a first voltage divider resistor R5 and a second voltage divider resistor R6. The first terminal of the first voltage divider resistor R5 is connected to the power supply voltage VCC, and the second terminal is connected to the first terminal of the second voltage divider resistor R6 and the base of the first transistor Q1 to generate a first voltage divider voltage. The second terminal of the second voltage divider resistor R6 is connected to the first control node LB-.

[0054] like Figure 3 As shown, in one embodiment, the second voltage divider circuit includes at least two voltage divider resistors connected in series between the power supply voltage VCC and the second control node HB-, for generating a second voltage divider voltage based on the power supply voltage VCC, and the base of the second transistor Q2 receives the second voltage divider voltage.

[0055] The first voltage regulator unit 22 is connected between the collector of the first transistor Q1 and the base of the second transistor Q2 to prevent reverse current flow. The first voltage regulator unit includes a first diode D1 and a second diode D2. The cathode of the first diode D1 is connected to the collector of the first transistor Q1, and the anode is connected to the anode of the second diode D2. The anode of the second diode D2 is directly or indirectly connected to the power supply voltage VCC, and the cathode is connected to the base of the second transistor Q2.

[0056] Preferably, the second voltage divider circuit has two voltage divider resistors: a third voltage divider resistor R7 and a fourth voltage divider resistor R8. The first terminal of the third voltage divider resistor R7 is connected to the power supply voltage VCC, and the second terminal is connected to the anode of the second diode D2. The first terminal of the fourth voltage divider resistor R8 is connected to the base of the second transistor Q2 to generate the second voltage divider, and the second terminal is connected to the second control node HB-.

[0057] like Figure 3As shown, in one embodiment, the control unit 20 includes a third voltage divider circuit 23. The third voltage divider circuit 23 is connected between the power supply voltage VCC and the second control node HB-, and is used to generate a third voltage divider voltage based on the power supply voltage VCC. The base of the third transistor Q3 receives the third voltage divider voltage. Preferably, the third voltage divider circuit has two voltage divider resistors, namely a fifth voltage divider resistor R9 and a sixth voltage divider resistor R10. The first end of the fifth voltage divider resistor R9 is connected to the power supply voltage VCC, and the second end is connected to the first end of the sixth voltage divider resistor R10, the base of the third transistor Q3, and the collector of the second transistor Q2, thereby generating the third voltage divider voltage. The second end of the sixth voltage divider resistor R10 is connected to the second control node HB-.

[0058] In one embodiment, the second switching unit 30 further includes a third voltage regulator unit 31, which includes a second Zener diode Z2, a third resistor R3, a fourth resistor R4, and a fifth capacitor C5.

[0059] The anode of the second Zener diode Z2, the second terminal of the third resistor R3, the second terminal of the fifth capacitor C5, and the first terminal of the fourth resistor R4 are all connected to the control terminal of the second MOSFET M2. The cathode of the second Zener diode Z2, the first terminal of the third resistor R3, and the first terminal of the fifth capacitor C5 are all connected to the power supply voltage VCC and the first terminal of the second MOSFET M2. The second terminal of the fourth resistor R4 is connected to the collector of the third transistor Q3. The second Zener diode Z2 is a Zener diode. The second Zener diode Z2, the third resistor R3, the fourth resistor R4, and the fifth capacitor C5 all serve to stabilize the voltage.

[0060] like Figure 2 As shown, in one embodiment, the reverse connection protection unit 40 is connected between the input voltage VIN and the power supply voltage VCC, and includes a third Zener diode Z3, several filter resistors, a third diode D3, and a fourth diode D4. The third Zener diode Z3 is connected between the input voltage VIN and the ground voltage GND, the filter resistors are connected between the input voltage VIN and the ground voltage GND, the anode of the third diode D3 is connected to the input voltage VIN, and the cathode is connected to the power supply voltage VCC, and the anode of the fourth diode D4 is connected to the input voltage VIN, and the cathode is connected to the power supply voltage VCC.

[0061] In one embodiment, the third diode D3 and the fourth diode D4 are used for inverting cutoff to prevent damage to the circuit from reverse current. A filter resistor is placed between the input voltage VIN and the ground voltage GND. The filter resistor is used to prevent electromagnetic interference from entering the subsequent circuit. The filter resistor can be designed to be about 330Ω, so that the circuit avoids excessive current loss at the input voltage VIN during normal operation. In one embodiment, the third Zener diode Z3 is a TVS diode (i.e., a transient voltage suppressor diode).

[0062] In the first state, the first control node LB- is connected to ground voltage GND, the first MOSFET M1 is turned on, and the power supply voltage VCC supplies power to the first load through the first output node VBAT1. At this time, the first transistor Q1 is turned on, the second transistor Q2 and the third transistor Q3 are turned off, and the second MOSFET M2 is in the off state, that is, the second output node VBAT2 is disconnected from the second load.

[0063] In the second state, the first control node LB- and the second control node HB- are connected to ground voltage GND, the first MOSFET M1 is turned on, and the power supply voltage VCC supplies power to the first load through the first output node VBAT1. At this time, the first transistor Q1 is turned on and pulls the base of the second transistor Q2 low, causing the second transistor Q2 to turn off. The third transistor Q3 is turned on and pulls the control terminal of the second MOSFET M2 low (i.e., the control signal S1 is low), the second MOSFET M2 is turned on, and the power supply voltage VCC supplies power to the second load through the second output node VBAT2.

[0064] In the third state, the second control node HB- is connected to ground voltage GND, the first MOSFET M1 is turned off, and the power supply voltage VCC is disconnected from the first load. At this time, the second transistor Q2 turns on and pulls the base potential of the third transistor Q3 low, causing the third transistor Q3 to turn off, which in turn causes the second MOSFET M2 to turn off, and the power supply voltage VCC is disconnected from the second load.

[0065] When the switching circuit switches to the third state, the third transistor Q3 may turn on before the second transistor Q2, causing the second MOSFET M2 to turn on mistakenly in a transient state. If the second load is a lighting unit, the light will flicker momentarily. This invention controls the turn-on time of the second transistor Q2 and the third transistor Q3 by setting a delay circuit, delaying the turn-on time of the third transistor Q3. When the second control node HB- is connected to ground voltage GND, the second transistor Q2 will turn on before the third transistor Q3, preventing the second MOSFET M2 from turning on mistakenly.

[0066] It is understood that the power supply voltage VCC in this utility model refers to the positive terminal of the power supply, and the reference potential refers to the negative terminal of the power supply. The switching circuit proposed in this utility model realizes the switching control logic of controlling the load power supply based on the common positive terminal of the power supply and the negative terminal of the control power supply.

[0067] As can be seen from the above technical solutions, this utility model has the following beneficial effects:

[0068] This utility model controls the conduction and cutoff of the first and second switching units based on the connection relationship between the first control node and the second control node and the reference potential, thereby achieving the effect of switching the power supply to the load.

[0069] This invention uses a delay unit to control the third transistor to turn on later than the second transistor, thereby preventing the second MOS transistor from turning on erroneously and thus preventing the second switching unit from turning on erroneously in a transient state, protecting the downstream load circuit.

[0070] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0071] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A switching circuit, characterized in that, The switching circuit includes: The first switching unit includes a first MOSFET, the first terminal of which is connected to the power supply voltage, the second terminal of which is connected to the first output node, and the control terminal of which is connected to the first control node. The control unit includes a first transistor, a second transistor, a third transistor, and a delay unit. The base of the first transistor is connected to a power supply voltage, the collector is connected to the base of the second transistor, and the emitter is connected to a first control node. The base of the second transistor is connected to a power supply voltage, the emitter is connected to a second control node, and the collector is connected to the base of the third transistor. The emitter of the third transistor is connected to the second control node, and the collector generates a control signal. The delay unit includes a first delay device connected between the base and emitter of the second transistor and a second delay device connected between the base and emitter of the third transistor. The third transistor is delayed in turning on after the second transistor. The second switching unit includes a second MOS transistor. The first terminal of the second MOS transistor is connected to the power supply voltage, the second terminal is connected to the second output node, and the control terminal is connected to the collector of the third transistor and receives the control signal. In the first state, the first control node is connected to the reference potential, and the first MOS transistor is turned on; In the second state, the first control node and the second control node are connected to the reference potential, and the first MOSFET and the second MOSFET are turned on. In the third state, the second control node is connected to the reference potential, and the first MOSFET and the second MOSFET are turned off.

2. The switching circuit according to claim 1, characterized in that, The control unit further includes a first capacitor and a first voltage divider circuit; wherein... The first terminal of the first capacitor is connected to the base of the first transistor, and the second terminal is connected to the first control node; The first voltage divider circuit is connected between the power supply voltage and the first control node, and is used to generate a first voltage divider voltage based on the power supply voltage. The base of the first transistor receives the first voltage divider voltage.

3. The switching circuit according to claim 1, characterized in that, The first delay device includes a second capacitor, the first end of which is connected to the base of the second transistor, and the second end of which is connected to the second control node; The second delay device includes a third capacitor, the first terminal of which is connected to the base of a third transistor, and the second terminal of which is connected to a second control node; The capacitance of the second capacitor is less than that of the third capacitor.

4. The switching circuit according to claim 1, characterized in that, The control unit includes a second voltage divider circuit, which includes at least two voltage divider resistors connected in series between the power supply voltage and the second control node, for generating a second voltage divider voltage based on the power supply voltage, and the base of the second transistor receives the second voltage divider voltage.

5. The switching circuit according to claim 1, characterized in that, The control unit further includes a first voltage regulator unit, which is connected between the collector of the first transistor and the base of the second transistor.

6. The switching circuit according to claim 5, characterized in that, The first voltage regulator unit includes a first diode and a second diode. The cathode of the first diode is connected to the collector of the first transistor, and the anode is connected to the anode of the second diode. The anode of the second diode is directly or indirectly connected to the power supply voltage, and the cathode is connected to the base of the second transistor.

7. The switching circuit according to claim 1, characterized in that, The control unit includes a third voltage divider circuit connected between the power supply voltage and the second control node, which is used to generate a third voltage divider voltage based on the power supply voltage. The base of the third transistor receives the third voltage divider voltage.

8. The switching circuit according to claim 1, characterized in that, The first switching unit further includes a second voltage regulator unit, which includes a first Zener diode, a first resistor, a second resistor, and a fourth capacitor. The anode of the first Zener diode, the second terminal of the first resistor, the second terminal of the fourth capacitor, and the first terminal of the second resistor are all connected to the control terminal of the first MOSFET. The cathode of the first Zener diode, the first terminal of the first resistor, and the first terminal of the fourth capacitor are all connected to the power supply voltage. The second terminal of the second resistor is connected to the first control node.

9. The switching circuit according to claim 1, characterized in that, The second switching unit further includes a third voltage regulator unit, which includes a second Zener diode, a third resistor, a fourth resistor, and a fifth capacitor. The anode of the second Zener diode, the second terminal of the third resistor, the second terminal of the fifth capacitor, and the first terminal of the fourth resistor are all connected to the control terminal of the second MOSFET. The cathode of the second Zener diode, the first terminal of the third resistor, and the first terminal of the fifth capacitor are all connected to the power supply voltage. The second terminal of the fourth resistor is connected to the collector of the third transistor.

10. The switching circuit according to claim 1, characterized in that, The switching circuit also includes a reverse connection protection unit, which is connected between the input voltage and the power supply voltage and includes a third Zener diode, several filter resistors, a third diode and a fourth diode. The third Zener diode is connected between the input voltage and ground voltage. The filter resistor is connected between the input voltage and ground voltage. The anode of the third diode is connected to the input voltage, and the cathode is connected to the power supply voltage. The anode of the fourth diode is connected to the input voltage, and the cathode is connected to the power supply voltage.

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