Self-adaptive high-linearity switching circuit
By rationally arranging transistors in the RF switch circuit and using variable feedforward capacitors and adaptive bias modules, the problems of insufficient linearity, high insertion loss, and heat dissipation of traditional RF switches are solved, and efficient performance adjustment under different power scenarios is achieved.
Patent Information
- Application Number
- CN202422984238.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-12-04
AI Technical Summary
Traditional RF switches suffer from insufficient linearity, high insertion loss, and heat dissipation issues, especially when high-power signals are input, and they cannot adaptively adjust according to the scenario.
An adaptive high-linearity switching circuit design is adopted. By rationally arranging transistors in the transmit and receive branches, combined with a variable feedforward capacitor and an adaptive bias module, the transistor voltage divider is dynamically adjusted to balance the circuit performance under different power scenarios.
It improves the linearity of the switch, reduces insertion loss, enhances the ability to process high-power signals, alleviates heat dissipation problems, and enables adaptive adjustment for different power scenarios.
Smart Images
Figure CN223502845U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of radio frequency circuits, and in particular to an adaptive high linearity switching circuit. Background Technology
[0002] As a crucial control unit in wireless communication systems, RF switch chips are responsible for switching between transmit and receive modes. The performance of RF switches is typically measured by four main metrics: insertion loss, isolation, linearity, and switching time. Linearity is primarily characterized by the 1-dB compression point (P1dB) to represent the switch's maximum power handling capability. With the rapid development of high-power applications such as 5G base stations and routers, the switches in RF transceiver chips need to support even higher power handling capabilities. Currently, RF switches on the market generally employ a transistor stacking circuit structure to improve switch linearity.
[0003] Traditional high-linearity RF switches distribute the voltage swing of high-power signals across each transistor by directly stacking transistors. This method effectively improves the linearity of the switch, but it also has certain drawbacks in practical applications: when a high-power signal is input, the distribution of the RF voltage swing is not uniform. This is due to the presence of substrate leakage current. As the number of stacked transistors increases, the source-drain voltage division of the top transistor is the largest, while that of the bottom transistor is the smallest. This uneven voltage division can cause the top transistor to saturate or break down, thus deteriorating the linearity of the switch.
[0004] Specifically, the existing RF switches have the following problems:
[0005] 1. From a performance perspective, due to the presence of substrate leakage, the actual transistor voltage division is not uniform, leading to premature compression, which limits the switching linearity and results in performance waste.
[0006] 2. From a structural perspective, high linearity switches require stacking a large number of transistors, resulting in significant insertion loss. However, this loss cannot be avoided depending on the application scenario when there is no high-power signal input.
[0007] 3. From a reliability perspective, when traditional switches are used for high-power input, heat is concentrated in the first transistor, resulting in heat dissipation problems. Utility Model Content
[0008] The purpose of this invention is to solve the problem of insufficient linearity of traditional switches, improve the adaptability of the switch structure to various scenarios, and alleviate the problem of high-power heat dissipation, and to provide an adaptive high-linearity switching circuit.
[0009] The objective of this utility model is achieved through the following technical solution:
[0010] An adaptive high-linearity switching circuit includes a transmitting branch, a receiving branch, and an antenna branch connected between the transmitting branch and the receiving branch. The transmitting branch includes a transmitting port and a transistor connected in series on the branch, the gate of which is connected to a gate control voltage. The receiving branch includes multiple transistors connected in series and a receiving port, wherein the gates of the multiple transistors are connected to a voltage opposite to the gate control voltage. The antenna branch includes an antenna port connected between the transistors in the transmitting branch and the transistors in the receiving branch.
[0011] In some embodiments, the size of the transistors in the receiving branch gradually decreases in the direction away from the antenna port.
[0012] In some embodiments, the transistors in the transmitting and receiving branches are NMOS transistors.
[0013] In some embodiments, a variable feedforward capacitor is connected in parallel to both the first-end transistor and the last-end transistor of the receiving branch.
[0014] Preferably, a variable feedforward capacitor is connected in parallel between the gate-source or gate-drain terminals of the first-end transistor, and a variable feedforward capacitor is connected in parallel between the gate-source or gate-drain terminals of the last-end transistor.
[0015] In some embodiments, an adaptive bias module is further included, which includes an envelope detection circuit and a current copy circuit connected in sequence. The input terminal of the envelope detection circuit is connected to the transmit port, and the output terminal of the current copy circuit is connected to the variable feedforward capacitor.
[0016] Preferably, both the envelope detection circuit and the current copying circuit are composed of multiple transistors.
[0017] In some embodiments, the envelope detection circuit includes a first transistor, a second transistor, and a third transistor connected in sequence. The gate of the first transistor is connected to the transmit port, the drain of the first transistor is connected to a power supply, the drain of the second transistor is connected to the source of the first transistor, the gate of the second transistor is connected to the gate of the third transistor, and a capacitor is connected between the source and drain of the second transistor.
[0018] In some embodiments, the current copying circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. The source of the fourth transistor is connected to the drain of the third transistor, the drain of the fourth transistor is connected to the power supply, the gate of the fourth transistor is connected to the gate of the fifth transistor, the drain of the fifth transistor is connected to the power supply, the source of the fifth transistor is connected to the drain of the sixth transistor, the source of the sixth transistor is grounded, and the gate of the sixth transistor is connected to a variable feedforward capacitor.
[0019] In some embodiments, the adaptive bias module further includes a current source connected to the gate of the sixth transistor.
[0020] It should be further noted that the technical features corresponding to the above options can be combined or substituted to form new technical solutions.
[0021] Compared with the prior art, the beneficial effects of this utility model are:
[0022] (1) This utility model improves the linearity of switching and reduces insertion loss by designing the arrangement of transistors on the transmitting and receiving branches. In particular, by connecting multiple transistors in series on the receiving branch to divide the voltage, the single transistor is prevented from being broken down due to a large voltage swing, thereby improving the switching linearity of the transmitting mode. By setting a transistor on the transmitting branch to reduce the number of transistors, the insertion loss of the transmitting mode can be alleviated.
[0023] (2) In one example, the multiple transistors in the receiving branch of this utility model are arranged in a gradually decreasing size manner in order to balance the voltage division of each transistor in the stack, thereby improving the switching linearity at no cost. In addition, increasing the size of the front-stage transistor can alleviate the problem of poor heat dissipation in the front stage.
[0024] (3) This switch innovatively achieves an adaptive function to input power. By adjusting the capacitance value of the variable feedforward capacitor through an innovative adaptive bias module, the voltage division of the transistors in the receiving branch is dynamically adjusted. The purpose is to further alleviate the uneven voltage division at the beginning and end of the stack and to achieve adaptive adjustment of the transistor capacitive reactance for different power scenarios, avoiding unnecessary insertion loss. That is, when the input power is high, the switch's power handling capability is enhanced; when the input power is low, unnecessary isolation is sacrificed to optimize insertion loss. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the switching circuit structure shown in an embodiment of the present invention;
[0026] Figure 2 This is a circuit structure diagram of the adaptive bias module shown in an embodiment of the present invention. Detailed Implementation
[0027] The technical solution of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0028] In the description of this utility model, it should be noted that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this utility model. Furthermore, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0029] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0030] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.
[0031] Reference Figure 1 In one exemplary embodiment, a single-pole double-throw transceiver switch is provided, comprising a transmitting branch, a receiving branch, and an antenna branch connected between the transmitting branch and the receiving branch. The transmitting branch includes a transmitting port TX and a transistor M0 connected in series on the branch, the gate of which is connected to a gate control voltage VG. The receiving branch includes n transistors (M1-Mn) connected in series and a receiving port RX, wherein the gates of the plurality of transistors are connected to a voltage opposite to the gate control voltage. The antenna branch includes an antenna port ANT, which is connected between the transistor M0 of the transmitting branch and the transistor M1 of the receiving branch. The transistors in the transmitting and receiving branches are NMOS transistors.
[0032] Specifically, the single-pole double-throw (SPDT) transceiver switch includes transmit (TX) mode and receive (RX) mode. In transmit mode, VG is high, transistor M0 is turned on, and transistors M1-Mn are turned off. At this time, transistor M0 is in a low-impedance conducting state, and the signal path is from the transmit port TX input through the conducting transistor M0 to the antenna port ANT output. Transistors M1-Mn are in a high-impedance off state, which isolates the transmit path from the receive port RX, preventing high-power RF signal leakage, reducing the switch's linearity, and protecting the module downstream of the RX port from being damaged or broken down by the leaked high-power signal. Similarly, in receive mode, when VG is low, transistor M0 is turned off, and transistors M1-Mn are turned on. At this time, transistors M1-Mn are in a low-impedance conducting state, and the signal path is from the antenna port ANT input through the conducting transistors M1-Mn to the receive port RX. Transistor M0 is in a high-impedance off state, which isolates the TX port from the receive path. Typically, transmit mode requires handling very high signal power, demanding high switching linearity. Based on the principle of stacked structures, in transmit mode, transistor M0 is in a low-impedance state with almost equal source and drain voltages, while transistors M1-Mn are in a high-impedance state, bearing the voltage swing of the high-power signals at the TX and ANT terminals. Therefore, n transistors need to be connected in series for voltage division to prevent a single transistor from breaking down due to a large voltage swing, thus improving the switching linearity of transmit mode. Therefore, the number of stacked transistors n is generally chosen based on the power requirements. In contrast, the signal power received at the ANT terminal is relatively small, and the isolation transistor M0 bears a smaller voltage swing, requiring fewer stacked transistors. Furthermore, a smaller number of M0 transistors can alleviate insertion loss in transmit mode; therefore, the number of M0 transistors is generally one.
[0033] In other examples, the transistors in the receiving branch gradually decrease in size along the direction away from the antenna port, i.e., the size of M1 to Mn gradually decreases. The purpose is to balance the voltage division of the individual transistors in the stack, thereby improving switching linearity. Furthermore, increasing the size of the preceding transistors can alleviate the problem of poor heat dissipation in the preceding stage. The working principle of this unique feature is based on the breakdown mechanism of the stacked structure and the switching characteristics of the transistors. First, the breakdown mechanism of the stacked structure: the turn-off transistors M1-Mn, due to the large RF swing, cause the internal PN junction to reopen and conduct, resulting in power leakage and premature switching compression. Second, the turn-off characteristics of the transistors: the equivalent model for transistor turn-off is capacitance C. OFF And C OFF The increase with increasing transistor size also indicates that the capacitive reactance 1 / jωCO FFThe capacitance decreases as the transistor size increases. Based on the above understanding of the working principle, increasing the size of the turn-off transistors M1-Mn can reduce their capacitive reactance, thereby reducing the voltage division borne by the transistors. Since the voltage division borne by the turn-off transistors M1-Mn in the stack shows a decreasing trend due to the influence of the substrate leakage current Isub, the unique feature is that by arranging the turn-off transistors M1-Mn in a gradually decreasing size manner, the capacitive reactance of the preceding transistors is low, reducing the voltage division, while the capacitive reactance of the following transistors is high, increasing the voltage division. This makes the overall voltage division of transistors M1-Mn more uniform, avoiding the breakdown of a single transistor bearing a large voltage division and deteriorating the switching linearity.
[0034] In other examples, a variable feedforward capacitor is connected in parallel with both the first-end transistor and the last-end transistor of the receiving branch. Specifically, a variable feedforward capacitor C1 is connected in parallel between the gate-source or gate-drain terminals of the first-end transistor M1, and a variable feedforward capacitor C2 is connected in parallel between the gate-source or gate-drain terminals of the last-end transistor Mn. This switch also includes an adaptive bias module, which comprises an envelope detection circuit and a current copy circuit connected in sequence. The input terminal of the envelope detection circuit is connected to the transmitting port, and the output terminal of the current copy circuit is connected to the variable feedforward capacitor.
[0035] The Adaptive Bias Module (ADB) structure is as follows: Figure 2 As shown, both the envelope detection circuit and the current copying circuit are composed of multiple transistors. The envelope detection circuit includes a first transistor N1, a second transistor N2, and a third transistor N3 connected in sequence. The gate of the first transistor N1 is connected to the transmit port TX, and the drain of the first transistor N1 is connected to the power supply VDD. The drain of the second transistor N2 is connected to the source of the first transistor N1, and the gate of the second transistor N2 is connected to the gate of the third transistor N3. A capacitor C3 is connected between the source and drain of the second transistor N2.
[0036] The current copying circuit includes a fourth transistor N4, a fifth transistor N5, and a sixth transistor N6. The source of the fourth transistor N4 is connected to the drain of the third transistor N3, and the drain of the fourth transistor N4 is connected to the power supply VDD. The gate of the fourth transistor N4 is connected to the gate of the fifth transistor N5, and the drain of the fifth transistor N5 is connected to the power supply VDD. The source of the fifth transistor N5 is connected to the drain of the sixth transistor N6, the source of the sixth transistor N6 is grounded, and the gate of the sixth transistor N6 is connected to a variable feedforward capacitor. The adaptive bias module also includes a current source T1, which is connected to the gate of the sixth transistor N6.
[0037] Specifically, the innovative adaptive bias module (ADB) adjusts the capacitance values of variable capacitors C1 and C2 to dynamically adjust the voltage division of transistors M1 and Mn. This aims to further alleviate uneven voltage division at the beginning and end of the stack and to adaptively adjust the transistor capacitive reactance for different power scenarios, avoiding unnecessary insertion losses. The working principle of this unique feature is based on the voltage division characteristics of the stacked structure, feedforward capacitor technology, and the adaptive bias module (ADB). First, the voltage division characteristics of the stacked structure: Due to the more severe substrate leakage at high power, coupled with delay and heat accumulation, the RF swing of the first turn-off transistor M1 is larger than that of other transistors, while the other transistors M2-Mn will have significantly smaller swings, causing the first transistor M1 to break down first. Second, the feedforward capacitor technology: By connecting capacitors in parallel between the gate-source or gate-drain terminals of transistors M1 and Mn, the COFF of turn-off transistors M1 and Mn can be increased or decreased, thereby reducing the voltage division of transistor M1 and increasing the voltage division of transistor Mn, achieving uniform voltage division.
[0038] The adaptive bias module (ADB) works as follows: The TX RF signal is coupled to the first transistor N1, forming a dynamic current in the path from the power supply VDD to the ground via the second transistor N2. This current is converted into a dynamic voltage at the gate-drain short circuit of the second transistor N2 and transmitted to the third transistor N3, forming an envelope detection circuit. The fourth transistor N4 and the fifth transistor N5, depending on their dimensions, form a fixed-ratio current copying circuit, ultimately generating the adaptive output voltage Vout on the sixth transistor N6. When the input signal is very small, N1 is not turned on, and the current source I1 outputs a static voltage Vout through the sixth transistor N6. Based on the above, the working principle is as follows: when the input power at the TX port increases, the adaptive bias module (ADB) detects an increase and generates an adaptive output voltage Vout that increases with the TX power. This causes the variable feedforward capacitors C1 to increase and C2 to decrease, resulting in an adaptive decrease in the voltage division of transistor M1 according to Vout, and an adaptive increase in the voltage division of transistor Mn. This further improves the uneven voltage division at the beginning and end of the stack. When the TX port power is low, the output Vout of the adaptive bias ADB module is the static output voltage Vout set by the current source I1, causing the capacitance values of the variable feedforward capacitors C1 and C2 to decrease, thus increasing the overall capacitance of the RX branch. OFF This allows the switch to sacrifice excess isolation in low-power scenarios, reducing the insertion loss of the transmit branch.
[0039] It should be noted that single-pole double-throw is only one implementation example, and variations in the number of blades and throws of the switch should also be within the scope of protection of this utility model.
[0040] The above detailed embodiments are a detailed description of the present utility model. It should not be considered that the specific embodiments of the present utility model are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present utility model, and all of these should be considered to fall within the protection scope of the present utility model.
Claims
1. An adaptive high linearity switching circuit, comprising a transmitting branch, a receiving branch, and an antenna branch connected between the transmitting branch and the receiving branch, characterized in that, The transmitting branch includes a transmitting port and a transistor connected in series on the branch, the gate of which is connected to a gate control voltage; the receiving branch includes multiple transistors connected in series and a receiving port, wherein the gates of the multiple transistors are connected to a voltage opposite to the gate control voltage; the antenna branch includes an antenna port, the antenna port being connected between the transistors of the transmitting branch and the transistors of the receiving branch.
2. The adaptive high linearity switching circuit according to claim 1, characterized in that, The size of the transistor in the receiving branch gradually decreases in the direction away from the antenna port.
3. The adaptive high linearity switching circuit according to claim 1, characterized in that, The transistors in the transmitting and receiving branches are NMOS transistors.
4. The adaptive high linearity switching circuit according to claim 1, characterized in that, A variable feedforward capacitor is connected in parallel to both the first-end transistor and the last-end transistor of the receiving branch.
5. The adaptive high linearity switching circuit according to claim 4, characterized in that, A variable feedforward capacitor is connected in parallel between the gate-source or gate-drain terminals of the first-end transistor, and a variable feedforward capacitor is connected in parallel between the gate-source or gate-drain terminals of the last-end transistor.
6. The adaptive high linearity switching circuit according to claim 4, characterized in that, It also includes an adaptive bias module, which includes an envelope detection circuit and a current copy circuit connected in sequence. The input terminal of the envelope detection circuit is connected to the transmit port, and the output terminal of the current copy circuit is connected to the variable feedforward capacitor.
7. The adaptive high linearity switching circuit according to claim 6, characterized in that, Both the envelope detection circuit and the current copying circuit are composed of multiple transistors.
8. The adaptive high linearity switching circuit according to claim 7, characterized in that, The envelope detection circuit includes a first transistor, a second transistor, and a third transistor connected in sequence. The gate of the first transistor is connected to the transmitting port, and the drain of the first transistor is connected to a power supply. The drain of the second transistor is connected to the source of the first transistor, and the gate of the second transistor is connected to the gate of the third transistor. A capacitor is connected between the source and drain of the second transistor.
9. The adaptive high linearity switching circuit according to claim 8, characterized in that, The current copying circuit includes a fourth transistor, a fifth transistor, and a sixth transistor. The source of the fourth transistor is connected to the drain of the third transistor, the drain of the fourth transistor is connected to the power supply, the gate of the fourth transistor is connected to the gate of the fifth transistor, the drain of the fifth transistor is connected to the power supply, the source of the fifth transistor is connected to the drain of the sixth transistor, the source of the sixth transistor is grounded, and the gate of the sixth transistor is connected to a variable feedforward capacitor.
10. The adaptive high linearity switching circuit according to claim 9, characterized in that, The adaptive bias module further includes a current source connected to the gate of the sixth transistor.