Analog signal receiving circuit with high common-mode voltage input

Abstract

The utility model relates to a circuit structure capable of meeting high common-mode voltage input, and mainly aims at an analog signal receiving circuit of high common-mode voltage input of an ARINC 429 bus in the field of avionics industrial integrated circuits. The circuit is used for processing an analog differential input signal with a high common-mode component and finally converting the analog differential input signal into a digital logic level as final output. According to the utility model, under the condition of high common-mode voltage input, the circuit can normally process an input signal, the logic function of a finally output digital signal is ensured to be correct, and meanwhile, a negative feedback circuit formed by an integrated operational amplifier in the circuit can have a relatively high phase margin, so that the reliability of the circuit is improved. Therefore, the whole circuit is ensured to have good stability.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuits in the avionics industry, specifically an analog signal receiving circuit with high common-mode voltage input. Background Technology

[0002] In the field of integrated circuits for avionics, existing ARINC 429 bus signal receiving circuits suffer from poor stability and low overall circuit reliability when the common-mode component of the input signal is too large, even leading to malfunctions. This invention proposes an analog signal receiving circuit for the ARINC 429 bus that ensures normal operation under high common-mode voltage input conditions. Simultaneously, the negative feedback circuit, composed of an integrated operational amplifier, provides a high phase margin, resulting in excellent overall circuit stability. Utility Model Content

[0003] This invention primarily addresses the analog signal receiving circuit of the ARINC 429 bus in the field of integrated circuits for the avionics industry. Under high common-mode voltage input conditions, the circuit can process the input signal normally, ensuring the correct logic function of the final output digital signal. Simultaneously, the negative feedback circuit composed of integrated operational amplifiers in the circuit has a high phase margin, thereby ensuring good stability of the overall circuit.

[0004] The technical solution adopted by this utility model to achieve the above objectives is as follows:

[0005] An analog signal receiving circuit with high common-mode voltage input includes: a proportional voltage divider circuit, a voltage follower, an operational amplifier circuit, and a digital-to-analog converter circuit connected in sequence. The proportional voltage divider circuit includes a first voltage divider circuit and a second voltage divider circuit, and the voltage follower includes a first voltage follower and a second voltage follower. The first voltage divider circuit is connected to the operational amplifier circuit through the first voltage follower, and the second voltage divider circuit is connected to the operational amplifier circuit through the second voltage follower.

[0006] The first and second voltage divider circuits have the same structure, including three resistors, wherein the input signal V in The output is provided to the voltage follower through resistor Ra. The node between resistor Ra and the voltage follower is connected to voltage VCC through resistor Rb, and also grounded through resistor Rc.

[0007] The first voltage follower and the second voltage follower have the same structure. Both are integrated operational amplifiers with a two-stage amplification structure, and the output of the proportional voltage divider circuit is used as the non-inverting input of the integrated operational amplifier.

[0008] The specific addition / subtraction amplifier circuit is as follows:

[0009] One end a of resistor R1a serves as the first input terminal of the operational amplifier circuit, connected to the first voltage follower. The other end b of R1a is connected to the inverting input terminal of the first operational amplifier A1. The end a of R1a is also grounded through resistors R1b and R2a in sequence. The inverting input terminal of A1 is connected to the output terminal of A1 through resistor Rf1. The output terminal of A1 serves as the first output terminal of the operational amplifier circuit. One end a of resistor R1d serves as the second input terminal of the operational amplifier circuit, connected to the second voltage follower. The other end b of R1d is connected to the inverting input terminal of the second operational amplifier A2. The end a of R1d is also grounded through resistors R1c and R2b in sequence. The inverting input terminal of A2 is connected to the output terminal of A2 through resistor Rf2. The output terminal of A2 serves as the second output terminal of the operational amplifier circuit. The node between R1b and R2a is connected to the non-inverting input terminal of A2. The node between R1c and R2b is connected to the non-inverting input terminal of A1.

[0010] The analog-to-digital converter circuit includes a reference voltage generator circuit and an analog-to-digital converter connected in sequence. The two input terminals of the analog-to-digital converter are respectively connected to the two output terminals of the addition / subtraction operation circuit. Its output terminal serves as an analog signal receiving circuit, outputting a digital signal V. outa and V outb .

[0011] The digital-to-analog converter has two enable terminals, ENA and ENB.

[0012] This utility model has the following beneficial effects and advantages:

[0013] The circuit structure of this invention enables the circuit to process the input signal normally even when accompanied by a high common-mode voltage, ensuring the correct logic function of the final output digital signal. Furthermore, the analog-to-digital converter circuit inside the circuit has two output enable control terminals to control the output of the final digital signal. At the same time, the negative feedback circuit composed of an integrated operational amplifier in the circuit has a high phase margin, thereby ensuring the overall circuit has good stability. Attached Figure Description

[0014] Figure 1 Receiver input status diagram.

[0015] Figure 2 Input signal and output signal waveform diagram.

[0016] Figure 3 Schematic diagram of a voltage divider circuit.

[0017] Figure 4 Schematic diagram of the internal structure of an integrated operational amplifier.

[0018] Figure 5 Schematic diagram of differential operational amplifier circuit.

[0019] Figure 6 Schematic diagram of the overall circuit structure of the receiver.

[0020] Figure 7 A schematic diagram of the overall analog signal receiving circuit. Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0022] ARINC 429 is a bus protocol used in the aerospace industry for data exchange between electronic systems on aircraft and spacecraft. This bus protocol uses a point-to-point transmission method, and one transmitter can connect to up to one hundred receivers. The transmission rates are primarily 12.5 kbps or 100 kbps, corresponding to low-speed and high-speed transmission modes, respectively. ARINC 429 uses twisted-pair cable as the physical transmission medium and employs differential signal transmission to improve interference immunity.

[0023] This utility model discloses a circuit for receiving ARINC 429 bus signals with high common-mode input voltage. For example... Figure 7 As shown, the receiving circuit has differential inputs, with input terminals Vina and Vinb respectively, and outputs digital signals, with output terminals Vouta and Voutb respectively.

[0024] The input signal with a high common-mode voltage is divided by a proportional voltage divider circuit to reduce its voltage to the range within which the subsequent voltage follower can operate normally.

[0025] The voltage after voltage division by the proportional voltage divider circuit is used as the input to the voltage follower circuit, which is composed of an integrated operational amplifier, thereby improving signal stability. At the same time, the presence of the voltage follower provides isolation between the preceding proportional voltage divider circuit and the subsequent operational amplifier circuit. In addition, the integrated operational amplifier constituting the voltage follower adopts a two-stage amplification structure. By adjusting the second-stage circuit structure and device parameters of the operational amplifier, the phase margin of the voltage follower is improved, thereby ensuring the stability of the circuit.

[0026] The output signal of the voltage follower serves as the input to the subsequent operational amplifier circuit, which is composed of integrated operational amplifiers. This amplifies the differential voltage value output by the voltage follower and outputs it to the subsequent stage of the circuit for further processing. Similar to the voltage follower, the integrated operational amplifier circuit that constitutes the operational amplifier circuit adopts a two-stage amplification structure. By adjusting the second-stage circuit structure and component parameters of the operational amplifier, the phase margin of the operational amplifier circuit is improved, thereby ensuring the stability of the circuit.

[0027] The differential voltage signal is amplified by the addition and subtraction operational amplifier circuit and then used as its output to act on the subsequent analog-to-digital converter circuit. The amplified voltage signal is compared with the reference voltage generated by the reference circuit in the analog-to-digital converter circuit, and finally output as a digital signal of the whole circuit. In addition, the analog-to-digital converter circuit has two enable terminals to control the output of the digital signal.

[0028] like Figure 1 As shown, the ARINC 429 bus uses differential voltage to represent HI, LO, and NULL. Theoretically, +10V represents HI, -10V represents LO, and 0V represents NULL. However, in practice, it is generally considered that +6.5V to +13V represents HI, -13V to -6.5V represents LO, and -2.5V to +2.5V represents NULL.

[0029] like Figure 2 As shown, taking typical differential voltage values ​​as an example, when Vina is +5V and Vinb is -5V, Vina is HI relative to Vinb, and the output digital signal of the output terminal Vouta is high, i.e., logic '1'; conversely, Vinb is LO relative to Vina, and the output signal of the output terminal Voutb is low, i.e., logic '0'. When Vina is 0V and Vinb is 0V, the input state is NULL, and the output signals of both the output terminals Vouta and Voutb are low, i.e., logic '0'. When Vina is -5V and Vinb is +5V, Vina is LO relative to Vinb, and the output digital signal of the output terminal Vouta is low, i.e., logic '0'; conversely, Vinb is HI relative to Vina, and the output signal of the output terminal Voutb is high, i.e., logic '1'.

[0030] like Figure 3 As shown, the differential-mode signals Vina and Vinb, which have high common-mode voltage components, are divided by a proportional voltage divider circuit to reduce their voltage to the range within which the subsequent voltage follower can operate normally, which are Va and Vb respectively. a and V bMeanwhile, the presence of the voltage follower isolates its preceding proportional voltage divider circuit from its subsequent operational amplifier circuit; furthermore, the integrated operational amplifier constituting the voltage follower employs a two-stage amplification structure, such as... Figure 4 As shown, the first stage of the operational amplifier is used to ensure the gain. The phase margin of the voltage follower is improved by adjusting the circuit structure and device parameters of the second stage of the operational amplifier, thereby ensuring the stability of the circuit.

[0031] like Figure 5 As shown, the output signal V of the voltage follower a and V b As the input to the subsequent operational amplifier circuit (composed of integrated operational amplifiers), it amplifies the differential voltage output from the voltage follower and outputs it to the next stage for further processing. In the operational amplifier circuit, resistor R... 2a =R 2b =R f1 =R f2 R 1a =R 1b =R 1c =R 1d Therefore, the magnified values ​​of V1 and V2 are respectively: V1 = R f1 / R 1a (V b -V a V2 = R f2 / R 1d (V a -V b Similar to a voltage follower, such as... Figure 4 As shown, the integrated operational amplifier constituting the addition and subtraction operational amplifier circuit adopts a two-stage amplification structure. By adjusting the second-stage circuit structure and device parameters of the operational amplifier, the phase margin of the addition and subtraction operational amplifier circuit is improved, thereby ensuring the stability of the circuit.

[0032] like Figure 6As shown, the differential voltage signals V1 and V2, amplified by the addition and subtraction operational amplifier circuit, are used as outputs of the subsequent analog-to-digital converter circuit. The amplified voltage signals V1 and V2 are compared with the reference voltage generated by the reference circuit in the analog-to-digital converter circuit, and finally output as digital signals. Specifically, when the voltage value of Vina-Vinb is between +6.5V and +13V, the output terminal Vouta is high and the output terminal Voutb is low; when the voltage value of Vina-Vinb is between -13V and -6.5V, the output terminal Vouta is low and the output terminal Voutb is high; when the voltage value of Vina-Vinb is between -2.5V and +2.5V, the output terminal Vouta is low and the output terminal Voutb is low. In addition, this analog-to-digital converter circuit has two enable terminals, ENA and ENB, to control the output of digital signals. When the enable terminals ENA and ENB are invalid, the output terminals Vouta and Voutb will be low regardless of the state of the input signal. The circuit can only work normally when both the enable terminals ENA and ENB are valid.

Claims

1. An analog signal receiving circuit with high common-mode voltage input, characterized in that, include: The circuit consists of a proportional voltage divider circuit, a voltage follower, an operational amplifier circuit, and a digital-to-analog converter circuit connected in sequence. The proportional voltage divider circuit includes a first voltage divider circuit and a second voltage divider circuit. The voltage follower circuit includes a first voltage follower and a second voltage follower. The first voltage divider circuit is connected to the operational amplifier circuit through the first voltage follower. The second voltage divider circuit is connected to the operational amplifier circuit through the second voltage follower.

2. The analog signal receiving circuit with high common-mode voltage input according to claim 1, characterized in that, The first and second voltage divider circuits have the same structure, including three resistors, wherein the input signal V in The output is provided to the voltage follower through resistor Ra. The node between resistor Ra and the voltage follower is connected to voltage VCC through resistor Rb, and also grounded through resistor Rc.

3. The analog signal receiving circuit with high common-mode voltage input according to claim 1, characterized in that, The first voltage follower and the second voltage follower have the same structure. Both are integrated operational amplifiers with a two-stage amplification structure, and the output of the proportional voltage divider circuit is used as the non-inverting input of the integrated operational amplifier.

4. The analog signal receiving circuit with high common-mode voltage input according to claim 1, characterized in that, The specific addition / subtraction amplifier circuit is as follows: One end a of resistor R1a serves as the first input terminal of the operational amplifier circuit, connected to the first voltage follower. The other end b of R1a is connected to the inverting input terminal of the first operational amplifier A1. The end a of R1a is also grounded through resistors R1b and R2a in sequence. The inverting input terminal of A1 is connected to the output terminal of A1 through resistor Rf1. The output terminal of A1 serves as the first output terminal of the operational amplifier circuit. One end a of resistor R1d serves as the second input terminal of the operational amplifier circuit, connected to the second voltage follower. The other end b of R1d is connected to the inverting input terminal of the second operational amplifier A2. The end a of R1d is also grounded through resistors R1c and R2b in sequence. The inverting input terminal of A2 is connected to the output terminal of A2 through resistor Rf2. The output terminal of A2 serves as the second output terminal of the operational amplifier circuit. The node between R1b and R2a is connected to the non-inverting input terminal of A2. The node between R1c and R2b is connected to the non-inverting input terminal of A1.

5. An analog signal receiving circuit with high common-mode voltage input according to claim 1, characterized in that, The analog-to-digital converter circuit includes a reference voltage generator circuit and an analog-to-digital converter connected in sequence. The two input terminals of the analog-to-digital converter are respectively connected to the two output terminals of the addition / subtraction operation circuit. Its output terminal serves as an analog signal receiving circuit, outputting a digital signal V. outa and V outb .

6. The analog signal receiving circuit with high common-mode voltage input according to claim 5, characterized in that, The analog-to-digital converter has two enable terminals, ENA and ENB.

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