PCB structure for improving strip line loss

Abstract

The utility model discloses a printed circuit board (PCB) structure for improving strip line loss, which is a PCB with an asymmetric laminated structure or a composite PCB with a symmetric laminated structure formed by reversely and symmetrically distributing and pressing two PCBs with asymmetric laminated structures, the PCBs with asymmetric laminated structures respectively comprise more than three wiring layers and dielectric layers positioned between the adjacent wiring layers, and the dielectric layers are arranged between the wiring layers and the dielectric layers. Strip lines are arranged on at least one wiring layer between the wiring layers of the surface layer and the bottom layer; the wiring structure is characterized in that the upper wiring layer adjacent to the wiring layer where the strip line is located is provided with a hollowed-out groove belt opposite to the strip line, and the width of the hollowed-out groove belt is 2-4 times that of the strip line. According to the utility model, required characteristic impedance can be achieved on the premise that the width of the strip line is not reduced, so that the transmission loss of the strip line is greatly improved.

Description

Technical Field

[0001] This utility model relates to a PCB structure for improving stripline loss. Background Technology

[0002] Currently, microstrip lines and striplines are two common types of transmission lines used for signal transmission in PCB design. Generally, traces running on the surface layer of a PCB are called microstrip lines, while traces running inside the PCB are called striplines. Physically, a microstrip line has one side exposed to air (allowing it to radiate outwards or be subject to external interference), while the other side is attached to the insulating dielectric of the PCB. Therefore, its electric field is partly distributed in the air and partly within the insulating dielectric of the PCB. A stripline, on the other hand, is embedded between two conductors, so its electric field is confined between the two conductors (planes) surrounding it. It is less prone to radiating energy and less susceptible to external interference, thus offering better crosstalk suppression.

[0003] In a stacked structure with a finite dielectric thickness, the equivalent dielectric constant of a stripline is greater than that of a microstrip line, and the equivalent capacitance formed with adjacent conductors is also larger. Therefore, the stripline trace width needs to be narrower than that of a microstrip line in order to obtain the same characteristic impedance (50 Ω). However, excessively narrow traces lead to increased manufacturing tolerances and greater transmission losses.

[0004] In existing technologies, controlling the transmission loss of microstrip lines is much simpler compared to striplines. For example, the utility model patent with publication number CN208863097 U utilizes symmetrically arranged vias on both sides of the microstrip line, with a distance of less than one-twenty-second, to achieve shielding. This, combined with a shielding layer bonded underneath the PCB, provides even better shielding, thereby reducing the transmission loss of the microstrip line. However, there is currently no good solution to the loss problem caused by striplines. Summary of the Invention

[0005] The purpose of this invention is to provide a PCB structure that improves stripline loss, which can achieve the required characteristic impedance without reducing the stripline width, thereby greatly improving the transmission loss of the stripline.

[0006] The technical solution of this utility model is as follows: a PCB structure for improving stripline loss, which is an asymmetric stacked PCB, or a symmetric stacked composite PCB composed of two asymmetric stacked PCBs distributed symmetrically in opposite directions and laminated together. The asymmetric stacked PCBs include three or more wiring layers and a dielectric layer located between adjacent wiring layers, and at least one wiring layer located between the top and bottom wiring layers is provided with a stripline. The feature is that a hollow slot is opened on the upper wiring layer adjacent to the wiring layer where the stripline is located, and the width of the hollow slot is 2 to 4 times the width of the stripline.

[0007] More preferably, the width of the hollowed-out groove in this invention is 3 to 4 times the width of the strip line.

[0008] More preferably, the width of the strip line in this invention is 4 mil, while the width of the corresponding hollow groove is 13 mil.

[0009] Furthermore, in this utility model, at least one wiring layer located between the top and bottom wiring layers is provided with a plurality of parallel strip lines, and the upper wiring layer adjacent to the wiring layer where these strip lines are located has a hollow groove strip that is one-to-one with each strip line.

[0010] Furthermore, in this invention, each of the strip lines has two parallel rows of ground holes symmetrically distributed on both sides, and the ground holes in each row of ground holes penetrate the wiring layer where the strip line is located, and connect the two wiring layers adjacent to the wiring layer where the strip line is located.

[0011] Furthermore, in this invention, the boreholes in each row of borehole strips are evenly spaced, and the spacing between them is less than one-tenth of the wavelength corresponding to the highest frequency of the transmitted signal of the strip.

[0012] Preferably, in this invention, the diameter of the boreholes in each row of borehole strips is 5 mil, and the spacing is 10 mil.

[0013] Furthermore, similar to conventional techniques, the two asymmetric stacked PCBs in the symmetrical stacked composite PCB are connected via dielectric lamination.

[0014] The advantages of adopting the technical solution of this utility model are as follows:

[0015] 1. In the PCB structure of this utility model, by introducing a hollowed-out groove on the upper wiring layer adjacent to the stripline, the equivalent capacitance formed between the stripline and the adjacent upper wiring layer can be reduced, thereby ensuring that the required impedance can be achieved without reducing the stripline width, and thus greatly reducing transmission loss and crosstalk.

[0016] 2. In the PCB structure of this utility model, two rows of ground vias are symmetrically added on both sides of the stripline. The ground vias in the ground vias are connected to the two adjacent wiring layers above and below the wiring layer where the stripline is located, forming a coaxial structure, which can effectively shield external interference and further enhance the stability of the signal transmitted inside the stripline. Attached Figure Description

[0017] Figure 1 This is a cross-sectional structural schematic diagram of a specific embodiment of the present invention;

[0018] Figure 2 yes Figure 1 Top view of the embodiment;

[0019] Figure 3 This is a cross-sectional structural schematic diagram of another specific embodiment of the present invention;

[0020] Figure 4 yes Figure 3 The example shows the trace loss curves of striplines on a conventional PCB at different frequencies;

[0021] Figure 5 yes Figure 3 The example shows a comparison of near-end crosstalk and far-end crosstalk curves between the stripline simulation of the embodiment and that of a conventional PCB.

[0022] In the diagram: 1. Routing layer; 101. First routing layer; 102. Second routing layer; 103. Third routing layer; 104. Fourth routing layer; 105. Fifth routing layer; 2. Dielectric layer; 201. First dielectric layer; 202. Second dielectric layer; 203. Third dielectric layer; 204. Fourth dielectric layer; 205. Fifth dielectric layer; 3. Stripline; 4. Cutout groove; 5. Ground via. Detailed Implementation

[0023] Example 1: Combination Figure 1 and Figure 2 The following is a specific embodiment of a PCB structure for improving stripline loss provided by this utility model:

[0024] This embodiment uses a three-layer PCB with an asymmetric stacked structure, such as... Figure 1 As shown, it consists of three independently routed routing layers 1 and two dielectric layers 2 stacked alternately. For ease of explanation, we name the three routing layers 1 from top to bottom as first routing layer 101, second routing layer 102 and third routing layer 103, where first routing layer 101 is the top routing layer and third routing layer 103 is the bottom routing layer, and the two dielectric layers 2 are first dielectric layer 201 and second dielectric layer 202, respectively.

[0025] In this embodiment, the wiring layer 1 is made of copper, while the dielectric layer 2 is made of Panasonic Megatron 6 substrate with a dielectric constant Dk of approximately 3.0. The thicknesses of each layer are as follows: the first wiring layer 101 has a thickness of 1.57mil (0.040mm), the first dielectric layer 201 has a thickness of 3.0mil (0.076mm), the second wiring layer 102 has a thickness of 1.38mil (0.035mm), the second dielectric layer 202 has a thickness of 3.0mil (0.076mm), and the third wiring layer 103 has a thickness of 1.5mil (0.038mm).

[0026] Still combined Figure 1 As shown, in this embodiment, the inner wiring layer 1, that is, the second wiring layer 102, is provided with two parallel strip lines 3, each of which is a single line used to transmit signals.

[0027] The core improvement of this utility model is as follows: the upper wiring layer 1, that is, the first wiring layer 101, which is adjacent to the second wiring layer 102 where the strip line 3 is located, has a hollow groove 4 opposite to each strip line 3. In this embodiment, the width of the strip line 3 is 4mil, and the width of the hollow groove 4 opposite to it is 13mil.

[0028] At the same time, combined Figure 2 As shown, in this invention, each stripline 3 has two parallel rows of ground vias 5 symmetrically distributed on both sides (two striplines 3 share one row of ground vias 5). The ground vias 5 in each row penetrate the second wiring layer 102 where the stripline 3 is located, and connect to the first wiring layer 101 and the third wiring layer 103 adjacent to the second wiring layer 102 where the stripline 3 is located. Simultaneously, the ground vias 5 in each row are evenly spaced, with a spacing less than one-tenth of the wavelength corresponding to the highest frequency of the transmitted signal of the stripline 3. In this embodiment, the diameter of the ground vias 5 in each row is 5 mil, and the spacing is 10 mil.

[0029] Example 2: Combination Figure 3 The image shows another specific embodiment of a PCB structure for improving stripline loss provided by this utility model:

[0030] It is a symmetrical stacked composite PCB composed of two asymmetric stacked PCBs arranged in opposite directions and laminated together, such as... Figure 3As shown, each asymmetric stacked PCB consists of five independently routed routing layers 1 and four dielectric layers 2, stacked alternately. For ease of explanation, we name the five routing layers 1 from the top to the innermost layer of each asymmetric stacked PCB in this embodiment as first routing layer 101, second routing layer 102, third routing layer 103, fourth routing layer 104, and fifth routing layer 105, respectively, and the four dielectric layers 2 from the outside to the inside as first dielectric layer 201, second dielectric layer 202, third dielectric layer 203, and fourth dielectric layer 204, respectively. The two asymmetric stacked PCBs in this symmetrical stacked composite PCB are bonded together via a dielectric layer 2, which is named the intermediate dielectric layer 205.

[0031] Similarly, in this embodiment, the wiring layer 1 is made of copper, while the dielectric layer 2 is made of Panasonic Megatron 6 substrate with a dielectric constant Dk of approximately 3.0. For each asymmetric stacked PCB, the thicknesses of each layer from the outside to the inside are as follows: the first wiring layer 101 has a thickness of 1.57mil (0.040mm), the first dielectric layer 201 has a thickness of 3.0mil (0.076mm), the second wiring layer 102 has a thickness of 1.38mil (0.035mm), the second dielectric layer 202 has a thickness of 3.0mil (0.076mm), the third wiring layer 103 has a thickness of 1.5mil (0.038mm), the third dielectric layer 203 has a thickness of 3.0mil (0.076mm), the fourth wiring layer 104 has a thickness of 0.59mil (0.015mm), the fourth dielectric layer 204 has a thickness of 3.0mil (0.076mm), the fifth wiring layer 105 has a thickness of 0.59mil (0.015mm), and the thickness of the middle dielectric layer 205 is 3.0mil (0.076mm).

[0032] Still combined Figure 3 As shown, in each asymmetric stacked PCB in this embodiment, the second wiring layer 102, which is the inner wiring layer 1, is provided with two parallel strip lines 3. Each strip line 3 is a single line used to transmit signals. The core improvement is that the upper wiring layer 1, that is, the first wiring layer 101, which is adjacent to the second wiring layer 102 where the strip lines 3 are located, has a cutout groove 4 opposite to each strip line 3. In this embodiment, the width of the strip line 3 is 4mil, and the width of the cutout groove 4 opposite to it is 13mil.

[0033] Also, see Example 1 Figure 1As shown, in this invention, each stripline 3 also has two parallel rows of ground vias 5 symmetrically distributed on both sides (two striplines 3 share one row of ground vias 5). The ground vias 5 in each row of ground vias 5 penetrate the second wiring layer 102 where the stripline 3 is located, and connect to the first wiring layer 101 and the third wiring layer 103 adjacent to the second wiring layer 102 where the stripline 3 is located. Simultaneously, the ground vias 5 in each row of ground vias 5 are evenly spaced, with a spacing less than one-tenth of the wavelength corresponding to the highest frequency of the transmitted signal of the stripline 3. In this embodiment, the diameter of the ground vias 5 in each row of ground vias 5 is 5 mil, and the spacing is 10 mil.

[0034] Compared with conventional symmetrical stacked composite PCB (without cutout slots 4 and ground vias 5), under the premise of the same board material and stack thickness, the above-described solution of this embodiment can achieve a width of 4 mil for the stripline 3 in conventional composite PCBs, which is only 2 mil, while this solution can achieve a width of 4 mil, an increase of 100%, in order to make the stripline 3 reach the required impedance. The increase in the width of the stripline 3 leads to a reduction in loss.

[0035] Specifically, we calculate and compare the PCB attenuation value of this embodiment with that of the conventional solution based on the following formula for calculating the average approximate PCB attenuation value transmitted at a certain frequency f:

[0036] atten dB in ~ 1 w[mils] f[Ghz] +2.3×f[GHz]×Df×

[0037] Where: w is the width of strip 3 (mil);

[0038] f = the sinusoidal frequency of the transmitted signal (GHz), which is 26.56 in this example;

[0039] Df = dissipation factor, which is 0.004 in this example;

[0040] Dk = dielectric constant, which is taken as 3.0 in this example.

[0041] For a standard PCB design, the stripe width w = 2mil. =3, meaning a loss of 3dB per inch; while for the PCB in this case, its stripline width w=4mil, =1.71, which means a loss of 1.71dB per inch, a 43% reduction in loss per inch compared to conventional solutions.

[0042] Similar results can be obtained in 3D electromagnetic field simulation software, such as... Figure 4As shown in the figure, the horizontal axis represents frequency, while the vertical axis represents the insertion loss of the 5mm long stripline 3 in the simulation model. Curve m1 is the stripline 3 loss curve of this embodiment, while curve m2 is the stripline 3 loss curve of the conventional scheme. It can be seen that the stripline 3 loss of this embodiment is significantly reduced across the entire frequency band. The longer the transmission line and the higher the frequency, the more obvious the loss reduction.

[0043] Meanwhile, we compared the near-end crosstalk and far-end crosstalk of this scheme and conventional schemes in 3D electromagnetic field simulation software, such as... Figure 5 As shown, the horizontal axis represents frequency, and the vertical axis represents the near-end crosstalk and far-end crosstalk of the 5mm long stripline 3 in the simulation model. Curve L1 is the far-end crosstalk curve of a conventional stripline 3, curve L2 is the near-end crosstalk curve of a conventional stripline 3, while curve I1 is the far-end crosstalk curve of the stripline 3 in this design, and curve I2 is the near-end crosstalk curve of the stripline 3 in this design. It can be seen that compared to the conventional design, the near-end and far-end crosstalk of the stripline 3 in this design are significantly reduced across the entire frequency band, from ≤ -25dB to ≤ -55dB, a reduction of approximately 30dB. This significant reduction in crosstalk effectively reduces the mutual interference between striplines 3 as signal transmission channels, as well as the radiation emitted during signal transmission, thereby greatly improving the signal transmission quality of the stripline 3.

[0044] Of course, the above are merely specific application examples of this utility model and do not constitute any limitation on the scope of protection of this utility model. In addition to the above embodiments, this utility model may have other implementation methods. All technical solutions formed by equivalent substitutions or equivalent transformations fall within the scope of protection claimed by this utility model.

Claims

1. A PCB structure for improving stripline loss, comprising an asymmetric stacked PCB or a symmetric stacked composite PCB composed of two asymmetric stacked PCBs arranged in opposite directions and laminated together, wherein each asymmetric stacked PCB includes three or more wiring layers (1) and a dielectric layer (2) located between adjacent wiring layers (1), and at least one wiring layer (1) located between the top and bottom wiring layers (1) is provided with a stripline (3); characterized in that On the upper wiring layer (1) adjacent to the wiring layer (1) where the stripline (3) is located, there is a cutout groove (4) opposite to the stripline (3), and the width of the cutout groove (4) is 2 to 4 times the width of the stripline.

2. The PCB structure for improving stripline loss according to claim 1, characterized in that... The width of the hollowed-out groove (4) is 3 to 4 times the width of the strip (3).

3. A PCB structure for improving stripline loss according to claim 2, characterized in that... The width of the strip (3) is 4 mil, while the width of the corresponding hollowed-out groove (4) is 13 mil.

4. A PCB structure for improving stripline loss according to claim 1, characterized in that... At least one of the wiring layers (1) located between the top and bottom layers is provided with a plurality of parallel strip lines (3), and the upper wiring layer (1) adjacent to the wiring layer (1) where these strip lines (3) are located has a hollowed-out groove (4) that is one-to-one with each strip line (3).

5. A PCB structure for improving stripline loss according to claim 1 or 4, characterized in that... Each strip (3) has two parallel rows of ground holes (5) symmetrically distributed on both sides. The ground holes (5) in each row of ground holes (5) penetrate the wiring layer where the strip (3) is located and connect the two wiring layers (1) adjacent to the wiring layer (1) where the strip (3) is located.

6. A PCB structure for improving stripline loss according to claim 5, characterized in that... The boreholes (5) in each row of boreholes (5) are evenly spaced, and the spacing between them is less than one-tenth of the wavelength corresponding to the highest frequency of the transmitted signal of the strip (3).

7. A PCB structure for improving stripline loss according to claim 6, characterized in that... The diameter of each borehole (5) in each row of boreholes (5) is 5 mil, and the spacing is 10 mil.

8. A PCB structure for improving stripline loss according to claim 1, characterized in that... The two asymmetric stacked PCBs in the symmetric stacked composite PCB are bonded together via a dielectric layer (2).

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