Heat dissipation structure for QFN chip test seat
By designing a heat dissipation structure with upper and lower grounded copper blocks and a limiting structure, the problem of excessive temperature in the QFN chip test socket was solved, achieving efficient heat dissipation, improving detection accuracy and safety, and reducing loss costs.
Patent Information
- Application Number
- CN202422902112.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2034-11-27
AI Technical Summary
The design of the existing QFN chip test socket leads to excessively high temperatures during testing, which can damage the chip solder balls and reduce testing accuracy, posing a safety hazard.
A heat dissipation structure consisting of an upper grounding copper block and a lower grounding copper block is adopted, including an upper mating plate, an upper protrusion and an upper heat dissipation through hole, as well as a lower mating plate, a lower protrusion and a lower heat dissipation through hole. These components absorb the heat during the testing process, and the combination of limiting protrusions and groove structures ensures stable assembly.
It effectively reduces the detection temperature, prevents damage to chip solder balls, improves detection accuracy and safety, and reduces waste costs.
Smart Images
Figure CN223503243U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of heat dissipation application technology for QFN chip testing, and specifically relates to a heat dissipation structure for a QFN chip test socket. Background Technology
[0002] Chip testing involves testing the chip's performance, reliability, and other key data to improve chip manufacturing and increase yield.
[0003] Chip testing requires chip test sockets. Currently, test sockets for QFN chips have an unreasonable design structure, which causes excessively high temperatures during testing, leading to damage to the chip's solder balls and resulting in losses for customers. It also indirectly affects the accuracy of the test and poses certain safety risks. Therefore, it is necessary to design a structure that can quickly absorb heat to match the QFN chip test socket.
[0004] To address the aforementioned issues, this invention provides a heat dissipation structure for a QFN chip test socket. Utility Model Content
[0005] Purpose of the utility model: The purpose of this utility model is to address the shortcomings of the existing technology by providing a heat dissipation structure for a QFN chip test socket, thereby solving the problems existing in the current QFN chip test socket during testing, and rapidly absorbing the heat generated during the testing process.
[0006] Technical Solution: The heat dissipation structure for a QFN chip test socket provided by this utility model consists of an upper grounding copper block and a lower grounding copper block. The upper grounding copper block includes an upper mating plate, an upper protrusion, and upper heat dissipation through holes. The upper protrusion is disposed on one side of the upper mating plate, and the upper heat dissipation through holes are evenly disposed within the connecting surface of the upper mating plate and the upper protrusion. The lower grounding copper block includes a lower mating plate, a lower protrusion, and lower heat dissipation through holes. The lower protrusion is disposed on one side of the lower mating plate, and the lower heat dissipation through holes are evenly disposed within the connecting surface of the lower mating plate and the lower protrusion.
[0007] The heat dissipation structure for the QFN chip test socket in this technical solution further includes limiting protrusions and limiting grooves symmetrically arranged in the outer layers of the upper and lower docking plates.
[0008] In this technical solution, the connecting surfaces of the upper connecting plate and the upper protrusion are both boss-type structures.
[0009] In this technical solution, the upper connecting plate, lower connecting plate, upper protrusion, and lower protrusion are configured as, but are not limited to, circular or polygonal structures.
[0010] Compared with the prior art, the beneficial effects of the heat dissipation structure of the QFN chip test socket of this utility model are as follows: 1. The upper grounding copper block and the lower grounding copper block structure used in conjunction can absorb the excess heat generated during the test, achieve the purpose of power dissipation, thereby reducing the test temperature and preventing the phenomenon of excessive temperature affecting the test of the chip under test; 2. The whole is a split combination design, which is convenient for operation and assembly, improves the test efficiency, and is conducive to promotion. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is an exploded view of the heat dissipation structure of the QFN chip test socket according to this utility model.
[0013] Figure 2 This is a schematic diagram of the split structure of the heat dissipation structure for the QFN chip test socket of this utility model;
[0014] Figure 3 yes Figure 2 A schematic diagram of the combined structure;
[0015] The numbers in the diagram are as follows: 1-Upper grounding copper block, 2-Lower grounding copper block, 1A-Upper mating plate, 1B-Upper protrusion, 1C-Upper heat dissipation through hole, 1D-Limiting protrusion, 2A-Lower mating plate, 2B-Lower protrusion, 2C-Lower heat dissipation through hole, 2D-Limiting groove, 10-Lower mounting plate, 11-Upper mounting plate, 12-Test probe, 13-QFN chip. Detailed Implementation
[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.
[0017] In the description of this utility model, it should be noted that the terms "top," "bottom," "one side," "the other side," "front," "back," "middle part," "inner," "top," and "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this utility model and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "joined" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0018] Example 1
[0019] like Figure 1 , Figure 2 and Figure 3 The heat dissipation structure shown for the QFN chip test socket consists of an upper grounding copper block 1 and a lower grounding copper block 2;
[0020] The upper grounding copper block 1 includes an upper docking plate 1A, an upper protrusion 1B, and an upper heat dissipation through hole 1C. The upper protrusion 1B is disposed on one side of the upper docking plate 1A, and the upper heat dissipation through hole 1C is evenly disposed in the connecting surface of the upper docking plate 1A and the upper protrusion 1B.
[0021] The lower grounding copper block 2 includes a lower connecting plate 2A, a lower protrusion 2B, and a lower heat dissipation through hole 2C. The lower protrusion 2B is disposed on one side of the lower connecting plate 2A, and the lower heat dissipation through hole 2C is evenly disposed in the connecting surface of the lower connecting plate 2A and the lower protrusion 2B.
[0022] Among them, the upper heat dissipation through hole 1C and the lower heat dissipation through hole 2C are aligned one to one and have the same diameter.
[0023] The working principle is as follows: the upper grounding copper block 1 and the lower grounding copper block 2 are located between the lower needle plate 10 and the upper needle plate 11, and are in contact with the lower needle plate 10 and the upper needle plate 11 respectively. The test probe 12 is installed in the lower needle plate 10 and the upper needle plate 11. At the same time, the upper part of the test probe 12 is in contact with the solder ball pin of the QFN chip 13. The heat generated during the test enters the upper grounding copper block 1 and the lower grounding copper block 2 through the upper heat dissipation hole 1C and the lower heat dissipation hole 2C. At this time, the upper mating plate 1A, the upper protrusion 1B and the lower mating plate 2A and the lower protrusion 2B absorb the high temperature excess power consumption heat.
[0024] Example 2
[0025] Based on Embodiment 1, the heat dissipation structure for the QFN chip test socket further includes a limiting protrusion 1D and a limiting groove 2D symmetrically arranged in the outer layer of the upper docking plate 1A and the lower docking plate 2A.
[0026] The limiting protrusion 1D is embedded in the limiting groove 2D, and the limiting protrusion 1D and the limiting groove 2D are set as a circular structure or a polygonal structure for mutual use.
[0027] This prevents horizontal detachment after the upper docking plate 1A and the lower docking plate 2A are assembled, facilitating assembly and ensuring safe detection of high-temperature absorption.
[0028] In addition, preferably, the connecting surfaces of the upper connecting plate 1A and the upper protrusion 1B are boss-type structures, and the connecting surfaces of the lower connecting plate 2A and the lower protrusion 2B are boss-type structures.
[0029] Among them, the upper mating plate 1A and the lower mating plate 2A have the same size, the upper protrusion 1B and the lower protrusion 2B have the same size, and the size of the upper mating plate 1A and the lower mating plate 2A are respectively larger than the size of the upper protrusion 1B or the size of the lower protrusion 2B.
[0030] The above structural design ensures that the contact surface is relatively stable and reliable after assembly, achieving safe heat absorption and compatibility with different chip detection devices.
[0031] In addition, the upper mating plate 1A, the lower mating plate 2A, the upper protrusion 1B, and the lower protrusion 2B are preferably configured as including but not limited to circular or polygonal structures. This design is used to match different chip detection devices.
[0032] This heat dissipation structure for QFN chip test sockets, when used with QFN chip test sockets, can solve the problem of excessive temperature during customer testing, improve the accuracy and safety of testing, prevent solder ball damage, and reduce costs.
[0033] It should be noted that, in this document, terms such as "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0034] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
Claims
1. A heat dissipation structure for a QFN chip test socket, characterized in that: It consists of an upper grounding copper block (1) and a lower grounding copper block (2); The upper grounding copper block (1) includes an upper docking plate (1A), an upper protrusion (1B) and an upper heat dissipation through hole (1C). The upper protrusion (1B) is disposed on one side of the upper docking plate (1A), and the upper heat dissipation through hole (1C) is evenly disposed in the connecting surface of the upper docking plate (1A) and the upper protrusion (1B). The lower grounding copper block (2) includes a lower connecting plate (2A), a lower protrusion (2B) and a lower heat dissipation through hole (2C). The lower protrusion (2B) is disposed on one side of the lower connecting plate (2A), and the lower heat dissipation through hole (2C) is evenly disposed in the connecting surface of the lower connecting plate (2A) and the lower protrusion (2B).
2. The heat dissipation structure for a QFN chip test socket according to claim 1, characterized in that: The heat dissipation structure for the QFN chip test socket also includes limiting protrusions (1D) and limiting grooves (2D) symmetrically arranged in the outer layers of the upper docking plate (1A) and the lower docking plate (2A).
3. The heat dissipation structure for a QFN chip test socket according to claim 1, characterized in that: The connecting surfaces of the upper connecting plate (1A) and the upper protrusion (1B) are boss-type structures, and the connecting surfaces of the lower connecting plate (2A) and the lower protrusion (2B) are boss-type structures.
4. The heat dissipation structure for a QFN chip test socket according to claim 1 or 3, characterized in that: The upper connecting plate (1A), lower connecting plate (2A), upper protrusion (1B), and lower protrusion (2B) are configured as including, but not limited to, circular or polygonal structures.