SiC MOSFET device with reduced bipolar degradation risk

Abstract

The utility model discloses a SiC MOSFET device capable of reducing bipolar degradation risk, and relates to the technical field of semiconductors. Source polycrystalline silicon and a P-shield region form a heterojunction diode in an N-epitaxial layer, so that current flowing through a body diode during reverse conduction of the device is shared, and the risk of degradation of a PW region of the device is reduced. And meanwhile, the P-shield region is arranged below the gate oxide layer, so that the impact of gate oxide of a peak electric field can be inhibited, and the reliability problem of the gate oxide layer of the trench SiC MOSFET is improved. The overlapping area of the grid electrode and the drain electrode is reduced in structural design, so that the purpose of reducing the grid-drain capacitance is achieved, the Miller plateau time is shortened, the switching performance of the device is improved, and the switching loss is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to SiC MOSFET devices that reduce the risk of bipolar degradation. Background Technology

[0002] In traditional power conversion circuits, silicon-based MOSFETs are typically used when higher switching frequencies are required, while silicon-based IGBTs are most commonly used in high-power conversion applications. As more and more power electronic devices strive to improve efficiency and power density, silicon power devices are facing performance challenges related to voltage withstand capability and efficiency. Compared to silicon devices, SiC MOSFETs have lower on-resistance, higher efficiency, and smaller chip size. Therefore, they help power systems reduce the size of inductors, capacitors, power modules / devices, and heat sinks through higher frequency operation, achieving miniaturization and thinning. For this reason, SiC MOSFETs are gradually replacing silicon MOSFETs and silicon IGBTs in fields such as new energy vehicles, photovoltaic charging and energy storage.

[0003] In power electronic system applications, the stability and reliability of devices are crucial metrics. When a power electronic system malfunctions and the protection circuit fails to function, the SiC MOSFET will be subjected to surge current. Current flows through the body diode of the SiC MOSFET, and when the surge current exceeds the device's current-carrying capacity, phenomena such as gate-source short circuit and PW region degradation may occur. Utility Model Content

[0004] To address the above problems, this invention provides a SiC MOSFET device that reduces the risk of bipolar degradation, thereby improving the reverse freewheeling capability of the device, while suppressing the impact of the gate oxide on the peak electric field, and improving the reliability of the gate oxide layer of trench SiC MOSFETs.

[0005] The technical solution of this utility model is:

[0006] A SiC MOSFET device that reduces the risk of bipolar degradation includes, from bottom to top, an N+ substrate layer, an N- epitaxial layer, a PW region, an ohmic contact alloy layer, and a front electrode metal layer.

[0007] The PW region is equipped with:

[0008] The P-shield region extends downward from the top of the PW region into the N-epipolar layer;

[0009] The N+ region has a pair located on both sides of the P-shield region, extending downwards from the top of the PW region respectively;

[0010] The P+ region is provided with a pair of regions, which extend downward from the top surface of the PW region and are connected to the N+ region;

[0011] Source polycrystalline silicon extends downward from the top surface of the P-shield region;

[0012] A pair of gate trench regions are provided, each etched downwards from the top surface of the PW region;

[0013] A gate oxide layer is located on the side and bottom of the gate trench region. The side is connected to the N+ region and the PW region, respectively, and the bottom is connected to the P-shield region and the source polysilicon, respectively.

[0014] An isolation dielectric layer a is located in the gate trench region, with its bottom surface connected to the gate oxide layer and its side surface connected to the source polysilicon.

[0015] A poly layer is filled between the gate oxide layer and the isolation dielectric layer a;

[0016] The isolation dielectric layer b is provided in pairs, and its bottom surface is respectively connected to the N+ region, the gate oxide layer, the Poly layer and the isolation dielectric layer a;

[0017] The ohmic contact alloy layer has a pair, which are respectively located on the side of the isolation medium layer b, and their bottom surfaces are respectively connected to the N+ region and the P+ region;

[0018] Specifically, the bottom surface of the front electrode metal layer is connected to the ohmic contact alloy layer, the isolation dielectric layer b, the isolation dielectric layer a, and the source polysilicon, respectively.

[0019] Specifically, the depth of the P+ region is 0.4-0.8 μm.

[0020] Specifically, the depth of the source trench region is 1.8um-2um.

[0021] Specifically, the depth of the gate trench region is 1.8um-2um.

[0022] Specifically, the gate trench region has the same depth as the source trench region.

[0023] The heterojunction diode formed by the polysilicon source and the P-shield region of this invention shares the current flowing through the body diode during reverse conduction, reducing freewheeling losses. The forward conduction voltage of the freewheeling diode is lower than that of the parasitic PN junction diode, so the freewheeling diode turns on earlier, reducing the risk of bipolar degradation and thus improving the reverse freewheeling capability of the device. Simultaneously, the P-shield region is located below the gate oxide layer, which can suppress the gate oxide impact of peak electric fields and improve the reliability of the gate oxide layer in trench SiC MOSFETs. This structure reduces the overlap area between the gate and drain, thereby reducing the gate-drain capacitance, shortening the Miller plateau time, and thus improving the switching performance and reducing switching losses. Attached Figure Description

[0024] Figure 1 , Figure 2 This is a structural diagram of step S100 of this utility model;

[0025] Figure 3 This is a structural diagram of step S200 of this utility model;

[0026] Figure 4 This is a structural diagram of step S300 of this utility model;

[0027] Figure 5 This is a structural diagram of step S400 of this utility model;

[0028] Figure 6 This is a structural diagram of the source trench region formed in step S500 of this utility model;

[0029] Figure 7 This is a structural diagram of the source polycrystalline silicon formed in step S500 of this utility model;

[0030] Figure 8 This is a structural diagram of step S600 of this utility model;

[0031] Figure 9 This is a structural diagram of the gate oxide layer prepared in step S600 of this utility model;

[0032] Figure 10 This is a structural diagram of step S600 of this utility model for preparing the isolation dielectric layer a;

[0033] Figure 11 This is a structural diagram of the Poly layer prepared in step S600 of this utility model;

[0034] Figure 12 This is a structural diagram of the preparation of the isolation dielectric layer b in step S700 of this utility model;

[0035] Figure 13 This is a structural diagram of the preparation of the ohmic contact alloy layer in step S700 of this utility model;

[0036] Figure 14 This is a structural diagram of the preparation of the front electrode metal layer in step S700 of this utility model;

[0037] In the figure, 1 is the N+ substrate layer, 2 is the N- epitaxial layer, 3 is the PW region, 4 is the P-shield region, 5 is the N+ region, 6 is the P+ region, 7 is the source trench region, 8 is the source polysilicon, 9 is the gate trench region, 10 is the gate oxide layer, 11 is the isolation dielectric layer a, 12 is the poly layer, 13 is the isolation dielectric layer b, 14 is the ohmic contact alloy layer, and 15 is the front electrode metal layer. Detailed Implementation

[0038] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0039] A method for fabricating SiC MOSFET devices with reduced bipolar degradation risk includes the following steps:

[0040] S100, such as Figure 1 As shown, an N- epitaxial layer 2 is epitaxially grown on an N+ substrate layer 1, and a PW region 3 is formed on top of the N- epitaxial layer 2 by ion implantation.

[0041] Specifically, the concentration range of PW region 3 is 1E. 17 cm -2 -1E 18 cm -2 The injection depth is 0.8-1.5 μm, such as... Figure 2 As shown;

[0042] S200, such as Figure 3 As shown, Al ions were repeatedly implanted downwards from the top surface of PW region 3 to form P-shield region 4 with a concentration of 1E. 18 -1E 19 cm -2 The injection depth is 2.2-2.5 μm;

[0043] S300, such as Figure 4 As shown, using SiO2 as a mask, N ions were implanted multiple times into PW region 3 to form N+ region 5, with a concentration range of 1E. 18 cm -2 -1E 19 cm -2 The injection depth is 0.4-0.8um, and RCA cleaning is performed after injection.

[0044] S400, such as Figure 5 As shown, using SiO2 as a mask, Al ions were implanted multiple times into PW region 3 to form P+ region 6, with a concentration range of 1E. 18 cm -2 -1E 19 cm -2 The implantation depth is 0.4-0.8 μm. After implantation, the mask is removed. Then, a thin graphite layer is deposited on the device surface as a protection and annealed at a high temperature of 1650℃-1690℃ for 15 min to activate the implanted ions.

[0045] The fact that the PW region 3, N+ region 5, and P+ region 6 are at the same potential can enhance the device's withstand voltage and short-circuit withstand capability.

[0046] S500, such as Figure 6 As shown, etching extends downwards from the top of P-shield region 4 to form source trench region 7, with an etching depth of 1.8um-2um; Figure 7 As shown, photoresist is used as a mask to deposit source polysilicon 8 in the source trench region 7;

[0047] S600, such as Figure 8 As shown, etching extends downwards from the top of PW region 3 to form gate trench region 9, with an etching depth of 1.8µm-2µm; Figure 9 As shown, a gate oxide layer 10 with a thickness of 40-60 nm was grown on the far sidewall and bottom of the gate trench region 9 using a dry oxygen thermal oxidation method. Annealing was then performed in a NO atmosphere at a temperature of 1250℃ for 1 hour to improve the density of the gate oxide layer and reduce defects. Figure 10 As shown, an isolation dielectric layer a11 is deposited on the other sidewall of the gate trench region 9; as Figure 11 As shown, polysilicon is then deposited in the gate trench region 9 using LPCVD to form a Poly layer 12, which serves as the gate electrode.

[0048] A pair of gate trench regions 9 are provided, located on both sides of the source polysilicon 8, and the etching depth is equal to the depth of the source trench region 7.

[0049] S700, an isolation dielectric layer b13, an ohmic contact alloy layer 14, and a front electrode metal layer 15 are sequentially prepared on the N-epitaxial layer 2.

[0050] The isolation medium layer b13 is provided in pairs, with its two ends overlapping the upper ends of the N+ region 5 and the isolation medium layer a11, respectively. The overlap distance is adjusted according to the actual process.

[0051] Specifically, such as Figure 12As shown, an isolation dielectric layer b13 is formed on the N-epitaxial layer 2 by depositing oxide; as Figure 13 As shown, an ohmic metal layer is formed on the N-epitaxial layer 2 by Ni metal sputtering deposition, followed by annealing at 1000℃ for 5 min to form an ohmic contact alloy layer 14, which forms an ohmic contact with the N+ region 5 and the P+ region 6 above it; as shown Figure 14 As shown, a front electrode metal layer 15 is formed on top of the N-epitaxial layer 2, the isolation dielectric layer b13 and the ohmic contact alloy layer 14 by Al metal sputtering, which serves as the source electrode.

[0052] A SiC MOSFET device that reduces the risk of bipolar degradation includes, from bottom to top, an N+ substrate layer 1, an N- epitaxial layer 2, a PW region 3, an ohmic contact alloy layer 14, and a front electrode metal layer 15.

[0053] The PW region 3 is equipped with:

[0054] P-shield region 4 extends downward from the top surface of PW region 3 into N-epipolar layer 2;

[0055] N+ region 5 is provided in pairs, located on both sides of P-shield region 4, extending downward from the top surface of PW region 3 respectively, and having a gap with the bottom surface of PW region 3; the depth of N+ region 5 is less than the depth of P-shield region 4;

[0056] P+ region 6 has a pair of regions, each extending downward from the top surface of PW region 3 and connected to N+ region 5; the depth of N+ region 5 is equal to the depth of P+ region 6.

[0057] The source polysilicon 8 extends downward from the top surface of the P-shield region 4 and is spaced from the bottom surface of the P-shield region 4; the source polysilicon 8 is located within the P-shield region 4;

[0058] A pair of gate trench regions 9 are provided, which are respectively etched downward from the top surface of the PW region 3;

[0059] The gate oxide layer 10 is located on the side and bottom of the gate trench region 9. The side is connected to the N+ region 5 and the PW region 3 respectively, and the bottom is connected to the P-shield region 4 and the source polysilicon 8 respectively.

[0060] An isolation dielectric layer a11 is located in the gate trench region 9, with its bottom surface connected to the gate oxide layer 10 and its side surface connected to the source polysilicon 8.

[0061] Poly layer 12 is filled between the gate oxide layer 10 and the isolation dielectric layer a11;

[0062] The top surfaces of the gate oxide layer 10, the isolation dielectric layer a11, and the Poly layer 12 are on the same plane;

[0063] The isolation dielectric layer b13 is provided in pairs, and its bottom surface is respectively connected to the N+ region 5, the gate oxide layer 10, the Poly layer 12 and the isolation dielectric layer a11;

[0064] The ohmic contact alloy layer 14 is provided in pairs, located on the side of the isolation medium layer b13 respectively, and its bottom surface is connected to the N+ region 5 and the P+ region 6 respectively.

[0065] The bottom surface of the front electrode metal layer 15 is connected to the ohmic contact alloy layer 14, the isolation dielectric layer b13, the isolation dielectric layer a11, and the source polysilicon 8, respectively.

[0066] The heterojunction diode formed by the source polysilicon 8 and the P-shield region 4 of this invention shares the current flowing through the body diode during reverse conduction, reducing freewheeling losses. The forward conduction voltage of the freewheeling diode is lower than that of the parasitic PN junction diode, so the freewheeling diode turns on earlier, reducing the risk of bipolar degradation and thus improving the reverse freewheeling capability of the device. Simultaneously, the P-shield region 4 is located below the gate oxide layer 10, which can suppress the impact of peak electric fields on the gate oxide, improving the reliability of the trench SiC MOSFET gate oxide layer.

[0067] The structure in this design reduces the overlap area between the gate and drain, thereby reducing the gate-drain capacitance, shortening the Miller plateau time, and thus improving the switching performance of the device and reducing switching losses.

[0068] Regarding the information disclosed in this case, the following points need to be clarified:

[0069] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.

[0070] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0071] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A SiC MOSFET device with reduced risk of bipolar degradation, characterized in that, It includes, from bottom to top, an N+ substrate layer (1), an N- epitaxial layer (2), a PW region (3), an ohmic contact alloy layer (14), and a front electrode metal layer (15). The PW region (3) is provided with: The P-shield region (4) extends downward from the top surface of the PW region (3) into the N-epilayer (2); The N+ region (5) has a pair located on both sides of the P-shield region (4), extending downward from the top surface of the PW region (3); The P+ region (6) is provided with a pair of regions, which extend downward from the top surface of the PW region (3) and are connected to the N+ region (5); The source polycrystalline silicon (8) extends downward from the top surface of the P-shield region (4); A pair of gate trench regions (9) are provided, which are etched downward from the top surface of the PW region (3); The gate oxide layer (10) is located on the side and bottom of the gate trench region (9). The side is connected to the N+ region (5) and the PW region (3) respectively, and the bottom is connected to the P-shield region (4) and the source polysilicon (8) respectively. An isolation dielectric layer a (11) is located in the gate trench region (9), with its bottom surface connected to the gate oxide layer (10) and its side surface connected to the source polysilicon (8); A poly layer (12) is filled between the gate oxide layer (10) and the isolation dielectric layer a (11); The isolation dielectric layer b (13) is provided in pairs, and its bottom surface is connected to the N+ region (5), the gate oxide layer (10), the Poly layer (12) and the isolation dielectric layer a (11) respectively; The ohmic contact alloy layer (14) has a pair, which are located on the side of the isolation medium layer b (13) respectively, and their bottom surfaces are connected to the N+ region (5) and P+ region (6) respectively.

2. The SiC MOSFET device with reduced bipolar degradation risk according to claim 1, characterized in that, The bottom surface of the front electrode metal layer (15) is connected to the ohmic contact alloy layer (14), the isolation dielectric layer b (13), the isolation dielectric layer a (11), and the source polysilicon (8), respectively.

3. The SiC MOSFET device with reduced bipolar degradation risk according to claim 1, characterized in that, The depth of the P+ region (6) is 0.4-0.8 μm.

4. The SiC MOSFET device with reduced bipolar degradation risk according to claim 1, characterized in that, The depth of the gate trench region (9) is 1.8um-2um.

5. The SiC MOSFET device for reducing bipolar degradation risk according to claim 1, characterized in that, The gate trench region (9) has the same depth as the source trench region (7).

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