Semiconductor device

Abstract

A semiconductor device includes a substrate, an oxide semiconductor channel layer, a gate structure, a conductive layer, and a source / drain electrode. The oxide semiconductor channel layer is vertically stacked over the substrate. The gate structure surrounds each of the channel regions of the oxide semiconductor channel layer. The conductive layer is vertically stacked over the substrate, wherein the conductive layer is interposed between two adjacent ones of the oxide semiconductor channel layers. The source / drain electrode is electrically connected to the source / drain region of the oxide semiconductor channel layer, wherein the source / drain electrode is in contact with the conductive layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in generation after generation of ICs. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of handling and manufacturing ICs. In the evolution of ICs, functional density (i.e., the number of interconnects per wafer area) has generally increased, while geometry (i.e., the smallest element (or line) that can be produced using manufacturing processes) has decreased. This shrinkage process typically provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to decrease, manufacturing processes become increasingly difficult. Therefore, forming reliable semiconductor devices in ever-smaller sizes remains a challenge. Utility Model Content

[0003] In some embodiments disclosed herein, the semiconductor device includes a substrate, an oxide semiconductor channel layer, a gate structure, a conductive layer, and source / drain electrodes. The oxide semiconductor channel layer is vertically stacked over the substrate. The gate structure surrounds each channel region of the oxide semiconductor channel layer. The conductive layer is vertically stacked over the substrate, wherein the conductive layer is interposed between adjacent oxide semiconductor channel layers. The source / drain electrodes are electrically connected to the source / drain regions of the oxide semiconductor channel layer, wherein the source / drain electrodes are in contact with the conductive layer.

[0004] In some embodiments disclosed herein, the semiconductor device includes a substrate, an oxide semiconductor channel layer, a gate structure, a conductive layer, and source / drain electrodes. The oxide semiconductor channel layer is vertically stacked over the substrate. The gate structure surrounds each of the channel regions of the oxide semiconductor channel layer. The conductive layer is vertically stacked over the substrate, wherein the conductive layer is interposed between two adjacent oxide semiconductor channel layers. The source / drain electrodes are electrically connected to the source / drain regions of the oxide semiconductor channel layer, wherein the source / drain electrodes are in contact with the conductive layer, and wherein the source / drain electrodes surround each of the source / drain regions of the oxide semiconductor channel layer.

[0005] In some embodiments disclosed herein, the semiconductor device includes a substrate, an oxide semiconductor channel layer, a gate structure, a conductive layer, and source / drain electrodes. The oxide semiconductor channel layer is vertically stacked over the substrate. The gate structure surrounds each of the channel regions of the oxide semiconductor channel layer. The conductive layer is vertically stacked over the substrate, wherein the conductive layer is interposed between two adjacent oxide semiconductor channel layers. The source / drain electrodes are electrically connected to the source / drain regions of the oxide semiconductor channel layer, wherein the source / drain electrodes are in contact with the conductive layer, and wherein the source / drain electrodes are spaced apart from the source / drain regions of the oxide semiconductor channel layer via the conductive layer. Attached Figure Description

[0006] The various features of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 14D This describes methods for forming a semiconductor device at various stages according to some embodiments of this disclosure;

[0008] Figure 15 This invention describes a method for forming a semiconductor device according to some embodiments of the present disclosure;

[0009] Figures 16A to 17C This describes methods for forming a semiconductor device at various stages according to some embodiments of this disclosure;

[0010] Figures 18 to 22 This describes methods for forming a semiconductor device at various stages according to some embodiments of this disclosure.

[0011] [Symbol Explanation]

[0012] 100, 300: substrate

[0013] 102, 302: Channel material layer

[0014] 102CH, 302CH: Passage Area

[0015] 102SD, 302SD: Source / Drain Region

[0016] 104, 304: Sacrificial Layer

[0017] 106: Overlay

[0018] 110: Gate structure

[0019] 112, 352: High-k dielectric layer

[0020] 114: First gate metal

[0021] 116: Second gate metal

[0022] 120, 330: Source / Drain electrodes

[0023] 200: Plasma Chamber

[0024] 210: Gas Source

[0025] 220: Plasma generation zone

[0026] 230: RF power supply

[0027] 240: Ion filter

[0028] 250: Reaction Chamber

[0029] 310: Dummy gate structure

[0030] 312: Dummy gate dielectric

[0031] 314: Dummy gate electrode

[0032] 316: Hard Mask

[0033] 320: Gate spacer

[0034] 340: Interlayer dielectric layer

[0035] 350: Metal gate structure

[0036] 354: Gate metal

[0037] AG: Air gap

[0038] BB, CC, DD: lines

[0039] G1: Gas

[0040] IO: Ion Plasma

[0041] MA1, MA2, MA3, MA4: Patterned Mask

[0042] O1: Opening

[0043] RD: Free Radical Plasma

[0044] ST1, ST2: Stacking Detailed Implementation

[0045] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations described below are for the purpose of simplifying this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0046] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one component or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly. As used herein, “approximately,” “about,” “approximately,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “approximately,” or “substantially” may be speculative unless explicitly specified. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the specification are merely examples and may decrease or vary as integrated circuits shrink.

[0047] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the structure. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes to allow the formation of patterns with, for example, smaller pitches than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0048] Figures 1A to 14C The methods for forming a semiconductor device at various stages according to some embodiments of this disclosure are described. More specifically, Figures 1A to 14A This is a top view of a semiconductor device. Figures 1B to 14B respectively along Figures 1A to 14A A cross-sectional view of line BB. Figures 1C to 14C respectively along Figures 1A to 14A Cross-sectional view of line CC. Figure 14D For along Figure 14A A cross-sectional view of line DD. Although Figures 1A to 14C The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions described and / or illustrated may be omitted, in whole or in part.

[0049] refer to Figure 1A , Figure 1B and Figure 1C The diagram shows substrate 100. Generally, substrate 100 may comprise a host semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the host semiconductor typically comprise the crystalline semiconductor material silicon, but may comprise one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like) or alloys thereof (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1-x As and similar materials, oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3 and similar materials), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0050] A stack ST1 is formed over substrate 100. The stack ST1 includes alternating channel material layers 102 and sacrificial layers 104. The channel material layers 102 and sacrificial layers 104 can be formed using deposition processes such as atomic layer deposition (ALD), sputtering, plasma-enhanced chemical vapor deposition (PECVD), epitaxial growth, or other suitable deposition processes. In some embodiments, a portion of the sacrificial layer 104 may be removed during a subsequent gate formation process, and a portion of the sacrificial layer 104 may be removed during a subsequent source / drain contact formation process. In some embodiments, each of the channel material layers 102 may include a channel region 102CH and a source / drain region 102SD located on the opposite side of the channel region 102CH.

[0051] In some embodiments, the channel material layer 102 may comprise an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin oxide (InSnO), indium tungsten-doped indium oxide (InWO), or gallium oxide (GaO). x Indium oxide (InO) x In other embodiments, the channel material layer 102 may comprise a semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), germanium-tin (GeSn), or the like. In some embodiments, the thickness of each channel material layer 102 is in the range of about 1 nm to about 1000 nm.

[0052] The sacrificial layer 104 may comprise a different material than the channel material layer 102 to provide sufficient etch selectivity. In some embodiments where the channel material layer 102 is made of an oxide semiconductor material, the sacrificial layer 104 may comprise a dielectric material such as silicon nitride (SiN) or silicon oxide (SiO2). x Or similar. In some embodiments where the channel material layer 102 is made of an oxide semiconductor material, the sacrificial layer 104 may also comprise a conductive material, such as titanium nitride (TiN). In some embodiments where the channel material layer 102 is made of a semiconductor material such as silicon or germanium, the sacrificial layer 104 may comprise silicon germanium (Si). 1-x Ge x In some embodiments, the thickness of each sacrificial layer 104 is in the range of about 1 nm to about 1000 nm.

[0053] A capping layer 106 is formed over the stack ST1. More specifically, a capping layer 106 is formed that contacts the topmost sacrificial layer in the sacrificial layer 104. In some embodiments, the capping layer 106 may comprise a dielectric material, such as silicon oxide (SiO2). In some embodiments, the capping layer 106 and the sacrificial layer 104 are made of different materials.

[0054] refer to Figure 2A , Figure 2B and Figure 2C A patterned mask MA1 is formed over substrate 100. The patterned mask MA1 may include openings in the exposed portion of the cover layer 106 and the stacked ST1, wherein such portions will be removed in subsequent steps (see [reference]). Figures 3A to 3C In some embodiments, the patterned mask MA1 may comprise a photoresist or a hard mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0055] refer to Figure 3A , Figure 3B and Figure 3C Remove portions of the capping layer 106 and the stack ST1 exposed via the openings of the patterned mask MA1. Perform a removal process to define the width of the channel region 102CH of the channel material layer 102 along a first direction (e.g., the Y direction). In some embodiments, suitable etching processes such as wet etching, dry etching, combinations thereof, or the like may be used to remove portions of the capping layer 106 and the stack ST1. After the etching process is complete, the patterned mask MA1 may be removed.

[0056] refer to Figure 4A , Figure 4B and Figure 4C A patterned mask MA2 is formed above the substrate 100. More specifically, as shown... Figure 4C As shown, the patterned mask MA2 overlaps with the source / drain region 102SD of the channel material layer 102 along the vertical direction. The patterned mask MA2 may include openings in the exposed portion of the cover layer 106 and the stack ST1, wherein such portions will be removed in subsequent steps. Specifically, in Figure 4C In this embodiment, the opening of the patterned mask MA2 may overlap with the channel region 102CH of the channel material layer 102 along the vertical direction. In some embodiments, the patterned mask MA2 may comprise a photoresist or a hard mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0057] refer to Figure 5A , Figure 5B and Figure 5CThe portion of the cover layer 106 exposed via the patterned mask MA2 is removed, thereby exposing the top surface of the topmost sacrificial layer 104. In some embodiments, a suitable etching process, such as wet etching, dry etching, a combination thereof, or the like, may be used to remove this portion of the cover layer 106. After the etching process is complete, the patterned mask MA2 may be removed. Figure 5C As shown, the remaining portion of the capping layer 106 overlaps with the source / drain regions 102SD of the channel material layer 102.

[0058] refer to Figure 6A , Figure 6B and Figure 6C The etching process is performed using the remaining portion of the capping layer 106 as an etching mask to remove portions of the sacrificial layer 104 exposed via the remaining portion of the capping layer 106. Therefore, the channel region 102CH of the channel material layer 102 is suspended above the substrate 100. Alternatively, portions of the sacrificial layer 104 located between adjacent source / drain regions 102SD of the channel material layer 102 can be retained after the etching process is complete, because such portions are protected by the capping layer 106 during the etching process. In some embodiments, the etching process may include wet etching, dry etching, a combination thereof, or the like. This process may also be referred to as a "channel release process".

[0059] After the channel release process is completed, an oxygen removal process can be performed on the source / drain region 102SD of the channel material layer 102 to increase the dopant concentration in the source / drain region 102SD of the channel material layer 102. More specifically, the oxygen removal process is performed to reduce the oxygen atom concentration in the source / drain region 102SD of the channel material layer 102, so as to generate oxygen vacancies in the source / drain region 102SD of the channel material layer 102. In some embodiments, oxygen vacancies can also be considered as dopants in the source / drain region 102SD of the channel material layer 102. In some embodiments, the dopant concentration in the source / drain region 102SD of the channel material layer 102 is higher than the dopant concentration in the channel region 102CH of the channel material layer 102. That is, the oxygen vacancy concentration in the source / drain region 102SD of the channel material layer 102 is higher than the oxygen vacancy concentration in the channel region 102CH of the channel material layer 102. In other words, the oxygen concentration in the source / drain region 102SD of the channel material layer 102 is lower than the oxygen concentration in the channel region 102CH of the channel material layer 102. In some embodiments, the doped source / drain region 102SD of the channel material layer 102 may be referred to as an n-type doped region.

[0060] In some embodiments where the channel material layer 102 comprises an oxide semiconductor material, an oxygen removal process can be used to form source / drain doped regions in the source / drain regions 102SD of the channel material layer 102. The remaining portion of the sacrificial layer 104 can be used as the oxygen removal layer for the oxygen removal process. For example, the sacrificial layer 104 may comprise a material having a stronger oxygen affinity than the channel material layer 102 (e.g., TiN, Ti-containing materials, or the like). The oxygen removal process can be performed by an annealing process having a temperature in the range of about 25°C to about 500°C. During the annealing process, oxygen atoms in the source / drain regions 102SD of the channel material layer 102 can be attracted by the remaining portion of the sacrificial layer 104, allowing oxygen atoms in the source / drain regions 102SD of the channel material layer 102 to diffuse into the sacrificial layer 104, thereby leaving oxygen vacancies in the source / drain regions 102SD of the channel material layer 102. On the other hand, because a portion of the sacrificial layer 104 is removed from the channel region 102CH of the channel material layer 102, oxygen vacancies are not formed in the channel region 102CH of the channel material layer 102. That is, the channel region 102CH of the channel material layer 102 may not be doped by the annealing process. In some embodiments, features such as... Figures 6A to 6C The oxygen removal process discussed in the article.

[0061] refer to Figure 7A , Figure 7B and Figure 7C A high-k dielectric layer 112 is deposited above the substrate 100 and surrounds each of the channel regions 102CH of the channel material layer 102. For example... Figure 7B As shown in the cross-sectional view, the high-k dielectric layer 112 may contact at least four sides of each of the channel regions 102CH of the channel material layer 102. Examples of high-k dielectric materials include alumina (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the high-k dielectric layer 112 is deposited using a conformal deposition process such as ALD, CVD, or the like. Therefore, the high-k dielectric layer 112 may also extend to the surface of the capping layer 106 and the remainder of the sacrificial layer 104. In some embodiments, the thickness of the high-k dielectric layer 112 is in the range of about 1 nm to about 1000 nm.

[0062] refer to Figure 8A , Figure 8B and Figure 8C A first gate metal 114 is deposited above the substrate 100 and covered by a high-k dielectric layer 112. For example... Figure 8BAs shown in the cross-sectional view, the first gate metal 114 may be deposited to fill the space between two adjacent channel material layers in the channel material layer 102. Similarly, the first gate metal 114 may surround each of the channel regions 102CH of the channel material layer 102. In some embodiments, the first gate metal 114 may comprise titanium nitride (TiN), aluminum (Al), titanium (Ti), or the like. In some embodiments, the first gate metal 114 is deposited using a conformal deposition process such as ALD, CVD, or the like. Thus, the first gate metal 114 may also extend to the surface of the capping layer 106. In some embodiments, the thickness of the first gate metal 114 is in the range of about 1 nm to about 1000 nm.

[0063] refer to Figure 9A , Figure 9B and Figure 9C A second gate metal 116 is deposited over the substrate 100 and covers the first gate metal 114. The high-k dielectric layer 112, the first gate metal 114, and the second gate metal 116 may be collectively referred to as gate structure 110. In some embodiments, the second gate metal 116 may comprise titanium nitride (TiN), aluminum (Al), titanium (Ti), or the like. In some embodiments, the first gate metal 114 and the second gate metal 116 may comprise the same material, but are deposited using different deposition processes. For example, conformal deposition processes such as ALD, CVD, or the like may be used to deposit the first gate metal 114. Sputtering may be used to deposit the second gate metal 116. In some embodiments, the deposition process of the first gate metal 114 is performed such that the first gate metal 114 surrounds the channel material layer 102. The deposition process of the second gate metal 116 is performed to achieve the desired thickness of the gate metal. In some embodiments, the thickness of the second gate metal 116 is in the range of about 1 nm to about 1000 nm.

[0064] refer to Figure 10A , Figure 10B and Figure 10C A patterned mask MA3 is formed above the substrate 100. More specifically, as... Figure 10C As shown, the patterned mask MA3 overlaps with the channel region 102CH of the channel material layer 102 along the vertical direction. The patterned mask MA3 may include an exposed portion of the cover layer 106 and an opening in the stack ST1. Specifically, in Figure 10C In this embodiment, the opening of the patterned mask MA3 may overlap with the source / drain region 102SD of the channel material layer 102 along the vertical direction. In some embodiments, the patterned mask MA3 may comprise a photoresist or a hard mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0065] refer to Figure 11A , Figure 11B and Figure 11C The portion of the gate structure 110 that overlaps with the source / drain region 102SD of the channel material layer 102 is removed. Therefore, the remaining portion of the gate structure 110 overlaps with and surrounds each of the channel regions 102CH of the channel material layer 102. In some embodiments, suitable etching processes such as wet etching, dry etching, combinations thereof, or the like may be used to remove these portions of the gate structure 110. After the etching process is complete, the capping layer 106 is exposed.

[0066] refer to Figure 12A , Figure 12B and Figure 12C A patterned mask MA4 is formed above the substrate 100. More specifically, as shown... Figure 12C As shown, the patterned mask MA4 may include an exposed portion of the cover layer 106 and an opening O1 in the stacked ST1. Specifically, in Figure 12C In this embodiment, the opening O1 of the patterned mask MA4 may overlap with the source / drain region 102SD of the channel material layer 102 along the vertical direction. In some embodiments, the patterned mask MA4 may comprise a photoresist or a hard mask (e.g., silicon nitride) and may be formed by a suitable photolithography process.

[0067] refer to Figure 13A , Figure 13B and Figure 13C The etching process is performed using a patterned mask MA4 as an etching mask to remove a portion of the cover layer 106 and a portion of the sacrificial layer 104 exposed through the opening O1. Therefore, the source / drain regions 102SD of the channel material layer 102 are suspended above the substrate 100. In some embodiments, the etching process may include wet etching, dry etching, a combination thereof, or the like. Figure 13C As shown, after the etching process is completed, a portion of the sacrificial layer 104 remains on the opposite sidewalls of the gate structure 110. The remaining portion of the sacrificial layer 104 can serve as an internal spacer, and may also be referred to as an internal spacer below.

[0068] refer to Figure 14A , Figure 14B , Figure 14C and Figure 14D Source / drain electrodes 120 are formed above the substrate 100 and surround each of the source / drain regions 102SD of the channel material layer 102. Figure 14DAs shown in the cross-sectional view, the source / drain electrode 120 can contact the four sides of each of the source / drain regions 102SD of the channel material layer 102. In some embodiments, the source / drain electrode 120 may comprise titanium nitride (TiN), aluminum (Al), titanium (Ti), or the like. In some embodiments, the source / drain electrode 120 may be formed using a conformal deposition process such as ALD, CVD, or the like. As a result of the conformal deposition process, the material of the source / drain electrode 120 may be sealed at the opening of the capping layer 106, thereby leaving an air gap AG formed within the source / drain electrode 120. For example, as Figure 14C As shown in the cross-sectional view, each of the air gaps AG has four sides defined by the source / drain electrodes 120. At least one air gap AG is vertically located between two adjacent source / drain regions 102SD in the channel material layer 102. At least one air gap AG is vertically located between adjacent source / drain regions 102SD of the bottommost channel material layer 102 and the substrate 100. In some embodiments, the source / drain electrodes 120 are in contact with the sidewalls and top surface of the capping layer 106. In some embodiments, the source / drain electrodes 120 are in contact with the sacrificial layer 104.

[0069] As mentioned above, the following can be omitted: Figures 6A to 6C The oxygen removal process described herein. Instead, the oxygen removal process can be performed after the formation of the source / drain electrodes 120. An oxygen removal process is performed on the source / drain regions 102SD of the channel material layer 102 to increase the dopant concentration in the source / drain regions 102SD of the channel material layer 102. More specifically, an oxygen removal process is performed to reduce the oxygen atom concentration in the source / drain regions 102SD of the channel material layer 102 to generate oxygen vacancies within the source / drain regions 102SD of the channel material layer 102. In some embodiments, oxygen vacancies may also be considered as dopants in the source / drain regions 102SD of the channel material layer 102.

[0070] In some embodiments where the channel material layer 102 comprises an oxide semiconductor material, an oxygen removal process can be used to form source / drain doped regions in the source / drain regions 102SD of the channel material layer 102. The source / drain electrode 120 can be used as an oxygen removal layer for the oxygen removal process. For example, the source / drain electrode 120 may comprise a material having a stronger oxygen affinity than the channel material layer 102 (e.g., TiN, Ti-containing materials, or the like). During the annealing process, oxygen atoms in the source / drain regions 102SD of the channel material layer 102 can be attracted by the source / drain electrode 120, allowing oxygen atoms in the source / drain regions 102SD of the channel material layer 102 to diffuse to the source / drain electrode 120, thereby leaving oxygen vacancies in the source / drain regions 102SD of the channel material layer 102.

[0071] Figure 15 This invention describes a method for forming a semiconductor device according to some embodiments of the present disclosure. Figure 15 The cross-sectional view is similar to Figure 13C The cross-sectional view is shown. Similar parts are marked as identical, and for the sake of simplicity, related details will not be repeated.

[0072] Figure 15 This describes a method for forming doped regions in the source / drain regions 102SD of the channel material layer 102. A portion of the sacrificial layer 104 is removed from the source / drain regions 102SD (see [link to documentation]). Figures 13A to 13C Following this, the source / drain region 102SD of the channel material layer 102 is exposed. Next, the substrate 100, including the structure formed thereon, is transferred to the plasma chamber 200. The plasma chamber 200 includes a gas source 210, a plasma generation region 220 in gas communication with the gas source 210, a radio frequency (RF) power supply 230 adjacent to the plasma generation region 220, an ion filter 240 located below the plasma generation region 220, and a reaction chamber 250 located below the ion filter 240. The substrate 100 is transferred to the reaction chamber 250 and supported by a substrate stage.

[0073] During the doping process, gas G1 is supplied to the plasma generation region 220. Simultaneously, an RF power supply 230 is turned on to generate ionic plasma IO and radical plasma RD. In some embodiments, gas G1 may be a fluorine-containing (F) gas, such as nitrogen trifluoride (NF3). The RF power supply 230 is used to generate fluorine ionic plasma (F... - ) and fluorine radical plasma (F * On the other hand, gas G1 can be a hydrogen-containing (H) gas, such as nitrogen trifluoride (NF3). RF power supply 230 is used to generate hydrogen ion plasma (H). + ) and hydrogen radical plasma (H * Here, the term "ion" can refer to an atom or molecule with a net charge. On the other hand, the term "free radical" can refer to an atom or molecule with a neutral charge.

[0074] During the doping process, an ion filter 240 is applied to block certain types of ions from the plasma generation region 220 from entering the reaction chamber 250. The blocking is selective, depending on the ion type. The ion filter 240 can be operated via an electric or magnetic field. In some embodiments, the ion filter 240 includes a DC power supply with a variable voltage. For example, when the ion plasma IO and the radical plasma RD are respectively fluorine ion plasma (F... - ) and fluorine radical plasma (F * When the ion filter 240 is in operation, it can generate a positive electric field to attract fluoride ion plasma (F).- And therefore prohibits the attraction of fluoride ion plasma (F). - ) enters the reaction chamber 250. On the other hand, the neutral fluorine radical plasma (F) enters the reaction chamber 250. * ) can enter the reaction chamber 250. In some embodiments, when the ion plasma IO and the free radical plasma RD are respectively hydrogen ion plasma (H + ) and hydrogen radical plasma (H * When the ion filter 240 is in operation, it can generate a negative electric field to attract hydrogen ion plasma (H). + And therefore prohibit the attraction of hydrogen ion plasma (H) + ) enters the reaction chamber 250. On the other hand, the neutral hydrogen radical plasma (H) enters the reaction chamber 250. * It can enter the reaction chamber 250.

[0075] As shown in the figure, the source / drain region 102SD of the channel material layer 102 is exposed to the free radical plasma RD entering the reaction chamber 250. In some embodiments where the channel material layer 102 is made of an oxide semiconductor material, the free radical plasma RD may act as a donor for the source / drain region 102SD of the channel material layer 102. For example, when the free radical plasma RD contains fluorine free radical plasma (F... * When the channel material layer 102 contains hydrogen radical plasma (H2C), the source / drain region 102SD of the channel material layer 102 can be doped with fluorine, and therefore the fluorine atom concentration in the source / drain region 102SD of the channel material layer 102 can be higher than the fluorine atom concentration in the channel region 102CH of the channel material layer 102. On the other hand, when the radical plasma RD contains hydrogen radical plasma (H2C), the source / drain region 102SD of the channel material layer 102 can be doped with fluorine, and therefore the fluorine atom concentration in the source / drain region 102SD of the channel material layer 102 can be higher than the fluorine atom concentration in the channel region 102CH of the channel material layer 102. * When the source / drain region 102SD of the channel material layer 102 is doped with hydrogen, the hydrogen atom concentration of the source / drain region 102SD of the channel material layer 102 can be higher than the hydrogen atom concentration of the channel region 102CH of the channel material layer 102.

[0076] Figures 16A to 17C The methods for forming a semiconductor device at various stages according to some embodiments of this disclosure are described. More specifically, Figures 16A to 17A This is a top view of a semiconductor device. Figures 16B to 17B respectively along Figures 16A to 17A A cross-sectional view of line BB. Figures 16C to 17C respectively along Figures 16A to 17A The cross-sectional view of line CC. Note that... Figures 16A to 17C Some components are similar to those about Figures 1A to 14C The components described are marked as identical, and for the sake of brevity, no further details will be provided.

[0077] Return to reference Figures 12A to 12CAn etching process is performed using a patterned mask MA4 as an etching mask to remove the portion of the cover layer 106 exposed through the opening O1, and the resulting structure is shown in Figures 16A to 16C Middle. Different from Figures 13A to 13C The embodiments shown are in Figures 16A to 16C In this configuration, the sacrificial layer 104 is retained between the source / drain regions 102SD of the channel material layer 102. In some embodiments, the top and bottom surfaces of each channel material layer 102 may contact the respective sacrificial layer 104, while the sidewalls of each channel material layer 102 may not be covered by the sacrificial layer 104 (see [link to documentation]). Figure 1B ).

[0078] refer to Figures 17A to 17C Source / drain electrodes 120 are formed above substrate 100 and fill openings in capping layer 106. Source / drain electrodes 120 may contact the topmost sacrificial layer 104. In some embodiments where sacrificial layer 104 is made of a conductive material such as TiN, sacrificial layer 104 may also act as source / drain contacts, providing electrical connections between adjacent source / drain regions 102SD of channel material layer 102 and between the source / drain regions 102SD of channel material layer 102 and source / drain electrodes 120.

[0079] Figures 18 to 22 This describes methods for forming a semiconductor device at various stages according to some embodiments of this disclosure. Although Figures 18 to 22 The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions described and / or illustrated may be omitted, in whole or in part.

[0080] refer to Figure 18 A substrate 300 is disposed. A stack ST2 is formed on the substrate 300. The stack ST2 includes alternating channel material layers 302 and sacrificial layers 304. The substrate 300 may be similar to the substrate 100 described above, and for the sake of simplicity, the relevant details will not be repeated.

[0081] In some embodiments, the channel material layer 302 may comprise an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin oxide (InSnO), tungsten-doped indium oxide (InWO), or gallium oxide (GaO). x Indium oxide (InO) xIn other embodiments, the channel material layer 302 may comprise a semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), germanium-tin (GeSn), or the like.

[0082] The sacrificial layer 304 may comprise a different material than the channel material layer 302 to provide sufficient etch selectivity. In some embodiments where the channel material layer 302 is made of an oxide semiconductor material, the sacrificial layer 304 may comprise a dielectric material such as silicon nitride (SiN) or silicon oxide (SiO2). x Or similar. In some embodiments where the channel material layer 302 is made of an oxide semiconductor material, the sacrificial layer 104 may comprise a conductive material, such as titanium nitride (TiN). In some embodiments where the channel material layer 302 is made of a semiconductor material such as silicon or germanium, the sacrificial layer 304 may comprise silicon germanium (Si). 1-x Ge x ).

[0083] A dummy gate structure 310 is formed above and across the stack ST2. The dummy gate structure 310 includes a dummy gate dielectric 312, a dummy gate electrode 314 located above the dummy gate dielectric 312, and a hard mask 316 located above the dummy gate electrode 314. The dummy gate dielectric 312 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode 314 may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), metal nitrides, metal silicides, metal oxides, and metals. The hard mask 316 may comprise a dielectric material such as silicon oxide, silicon nitride, or combinations thereof.

[0084] The dummy gate structure 310 can be formed by, for example, the following steps: depositing a dummy dielectric layer, a dummy gate layer and a hard mask layer on a substrate 300, forming a patterned mask on the hard mask layer, and then performing an etching process on the dummy dielectric layer, the dummy gate layer and the hard mask layer by using the patterned mask as an etching mask.

[0085] Gate spacers 320 are formed on the opposite sidewalls of the dummy gate structure 310. In some embodiments, the gate spacers 320 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the gate spacers 320 may be formed by, for example, the following steps: depositing a spacer layer over a substrate and then performing an anisotropic etching process to remove the horizontal portion of the spacer layer, such that the vertical portion of the spacer layer remains on the sidewalls of the dummy gate structure 310.

[0086] refer to Figure 19An etching process is performed using a dummy gate structure 310 and a gate spacer 320 as an etching mask to remove the portion of the sacrificial layer 304 exposed through the dummy gate structure 310 and the gate spacer 320. Therefore, the source / drain region 302SD of the channel material layer 302 is suspended above the substrate 300.

[0087] After the etching process is completed, the source / drain regions 302SD can be doped to form doped regions in the source / drain regions 302SD. The doping process can be similar to that described above. Figure 15 The doping process described herein. For example, a substrate 300 containing a structure formed thereon is transferred to a plasma chamber for the doping process. The plasma chamber is used to generate ionic plasma and radical plasma, while the ionic plasma can be blocked by an ion filter so that only the radical plasma can reach the substrate 300. The source / drain regions 302SD of the channel material layer 302 are exposed to the radical plasma. In some embodiments where the channel material layer 302 is made of an oxide semiconductor material, the radical plasma can act as a donor for the source / drain regions 302SD of the channel material layer 302. For example, when the radical plasma contains fluorine radical plasma (F... * When the channel material layer 302 contains hydrogen radical plasma (H2C), the source / drain region 302SD of the channel material layer 302 can be doped with fluorine, and therefore the fluorine atom concentration in the source / drain region 302SD of the channel material layer 302 can be higher than the fluorine atom concentration in the channel region 302CH of the channel material layer 302. On the other hand, when the radical plasma contains hydrogen radical plasma (H2C), the source / drain region 302SD of the channel material layer 302 can be doped with fluorine, and therefore the fluorine atom concentration in the source / drain region 302SD of the channel material layer 302 can be higher than the fluorine atom concentration in the channel region 302CH of the channel material layer 302. * In this case, the source / drain region 302SD of the channel material layer 302 may be doped with hydrogen, and therefore the hydrogen atom concentration of the source / drain region 302SD of the channel material layer 302 may be higher than the hydrogen atom concentration of the channel region 302CH of the channel material layer 302. In some embodiments, the doping process may be omitted.

[0088] refer to Figure 20 A source / drain electrode 330 is formed to line the exposed surface of the source / drain region 302SD of the channel material layer 302. The source / drain electrode 330 may be similar to the source / drain electrode 120 as described above, and for the sake of simplicity, the relevant details will not be repeated.

[0089] In omission Figure 19 In some embodiments of the doping process described herein, the source / drain regions 302SD of the channel material layer 302 may be doped via an oxygen removal process to increase the dopant concentration in the source / drain regions 302SD of the channel material layer 302. The oxygen removal process may be similar to... Figures 6A to 6CThe oxygen removal process described herein. For example, an oxygen removal process is performed to reduce the oxygen atom concentration in the source / drain region 302SD of the channel material layer 302, so as to generate oxygen vacancies in the source / drain region 302SD of the channel material layer 302. In some embodiments, oxygen vacancies may also be considered as dopants in the source / drain region 302SD of the channel material layer 302. In some embodiments, the dopant concentration in the source / drain region 302SD of the channel material layer 302 is higher than the dopant concentration in the channel region 302CH of the channel material layer 302. That is, the oxygen vacancy concentration in the source / drain region 302SD of the channel material layer 302 is higher than the oxygen vacancy concentration in the channel region 302CH of the channel material layer 302. In other words, the oxygen concentration in the source / drain region 302SD of the channel material layer 302 is lower than the oxygen concentration in the channel region 302CH of the channel material layer 302. In some embodiments, the doped source / drain region 302SD of the channel material layer 302 may be referred to as an n-type doped region.

[0090] In some embodiments where the channel material layer 302 comprises an oxide semiconductor material, an oxygen removal process can be used to form source / drain doped regions in the source / drain regions 302SD of the channel material layer 302. The source / drain electrode 330 can be used as an oxygen removal layer for the oxygen removal process. For example, the source / drain electrode 330 may comprise a material having a stronger oxygen affinity than the channel material layer 302 (e.g., TiN, Ti-containing materials, or the like). The oxygen removal process can be performed by an annealing process having a temperature in the range of about 25°C to about 500°C. During the annealing process, oxygen atoms in the source / drain regions 302SD of the channel material layer 302 can be attracted by the source / drain electrode 330, allowing oxygen atoms in the source / drain regions 302SD of the channel material layer 302 to diffuse to the source / drain electrode 330, thereby leaving oxygen vacancies in the source / drain regions 302SD of the channel material layer 302. In some embodiments, when applied... Figure 19 When discussing the doping process, details such as... can be omitted. Figure 20 The oxygen removal process discussed in the article.

[0091] refer to Figure 21An interlayer dielectric layer 340 is formed over the substrate 300 and covers the source / drain electrodes 330. Next, the interlayer dielectric layer 340 is planarized until the dummy gate structure 310 is exposed. In some embodiments, the interlayer dielectric layer 340 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), or polyimide.

[0092] refer to Figure 22 A replacement gate (RPG) process is performed to replace the dummy gate structure 310 with a metal gate structure 350. More specifically, a first etching process is performed to remove the dummy gate structure 310, thereby forming gate trenches between pairs of gate spacers 320. Subsequently, a second etching process is performed to remove a portion of the sacrificial layer 304 via the gate trenches, such that the channel regions 302CH of the channel material layer 302 are suspended above the substrate 300. A metal gate structure 350 is formed surrounding each of the channel regions 302CH of the channel material layer 302.

[0093] In some embodiments, the metal gate structure 350 includes a high-k dielectric layer 352 and a gate metal 354 located above the high-k dielectric layer 352. The materials of the high-k dielectric layer 352 and the gate metal 354 may be similar to those described above regarding the high-k dielectric layer 112 and the first gate metal 114, and for the sake of brevity, the relevant details will not be repeated.

[0094] Based on the foregoing embodiments, it can be seen that the present disclosure provides advantages in the manufacture of integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor are all embodiments required to have a specific advantage. An embodiment of the present disclosure provides a gate all around (GAA) semiconductor device having an oxide semiconductor channel layer. An etching process is performed to release the source / drain regions of the oxide semiconductor channel layer and to form source / drain electrodes surrounding the source / drain regions of the oxide semiconductor channel layer. The source / drain electrodes may contact at least four sides of the source / drain regions of the oxide semiconductor channel layer. The increased contact area will reduce the contact resistance between the source / drain electrodes and the source / drain regions of the oxide semiconductor channel layer and will further increase the on-state current (Ion) of the semiconductor device. ON This disclosure provides a method for forming a gate all-around (GAA) semiconductor device, wherein a sacrificial layer can be retained in the final structure and can be used as an internal spacer on the opposite sidewalls of the gate structure. With this configuration, it is not necessary to form the internal spacer through additional deposition and lithography processes. This disclosure also provides a method for forming doped regions directly in the source / drain regions of an oxide semiconductor channel layer. With this configuration, it is not necessary to regrow source / drain epitaxial regions above the source / drain regions of the oxide semiconductor channel layer to obtain heavily doped regions.

[0095] In some embodiments disclosed herein, a method includes: forming an alternating stack of oxide semiconductor channel layers and sacrificial layers over a substrate; removing a first portion of the sacrificial layer to expose a channel region of the oxide semiconductor channel layer; forming a gate structure surrounding each of the channel regions of the oxide semiconductor channel layer; removing a second portion of the sacrificial layer to expose a source / drain region of the oxide semiconductor channel layer; and forming a source / drain electrode surrounding and contacting each of the source / drain regions of the oxide semiconductor channel layer, wherein the source / drain electrode is made of a metal-containing material.

[0096] In some embodiments, the sacrificial layer is made of a dielectric material.

[0097] In some embodiments, the sacrificial layer is made of a conductive material.

[0098] In some embodiments, after the source / drain electrodes are formed, the sacrificial layer has a portion retained on the sidewall of the gate structure.

[0099] In some embodiments, the method further includes: performing an annealing process after removing a first portion of the sacrificial layer, such that a second portion of the sacrificial layer attracts oxygen atoms from the source / drain region of the oxide semiconductor channel layer to generate oxygen vacancies in the source / drain region of the oxide semiconductor channel layer.

[0100] In some embodiments, the method further includes: performing an annealing process after forming the source / drain electrodes, such that the source / drain electrodes attract oxygen atoms from the source / drain regions of the oxide semiconductor channel layer to generate oxygen vacancies in the source / drain regions of the oxide semiconductor channel layer.

[0101] In some embodiments, the method further includes: transferring a substrate to a plasma chamber; generating ionic plasma and radical plasma via a radio frequency power supply, wherein the ionic plasma and radical plasma comprise the same element; and blocking the ionic plasma from passing through an ion filter while allowing the radical plasma to reach the exposed surfaces of the source / drain regions of the oxide semiconductor channel layer to form doped regions in the source / drain regions of the oxide semiconductor channel layer.

[0102] In some embodiments disclosed herein, a method includes: forming an alternating stack of oxide semiconductor channel layers and sacrificial layers over a substrate; removing a first portion of the sacrificial layer to expose a channel region of the oxide semiconductor channel layer; forming a gate structure surrounding each of the channel regions of the oxide semiconductor channel layer; and forming source / drain electrodes over a source / drain region of the oxide semiconductor channel layer, wherein after forming the source / drain electrodes, a second portion of the sacrificial layer remains on the sidewall of the gate structure.

[0103] In some embodiments, the source / drain electrodes are in contact with a second portion of the topmost sacrificial layer in the sacrificial layer.

[0104] In some embodiments, the method further includes: removing a third portion of the sacrificial layer to expose the source / drain regions of the oxide semiconductor channel layer prior to forming the source / drain electrodes, wherein the source / drain electrodes surround and contact each of the source / drain regions of the oxide semiconductor channel layer.

[0105] In some embodiments, the source / drain electrodes are in contact with a second portion of the sacrificial layer.

[0106] In some embodiments, the sacrificial layer comprises tantan nitride (TiN).

[0107] In some embodiments, the method further includes performing an oxygen removal process, the oxygen removal process including attracting oxygen atoms from the source / drain regions of the oxide semiconductor channel layer using a sacrificial layer to generate oxygen vacancies in the source / drain regions of the oxide semiconductor channel layer.

[0108] In some embodiments, the method further includes performing an oxygen removal process, the oxygen removal process including attracting oxygen atoms from the source / drain regions of the oxide semiconductor channel layer using source / drain electrodes to generate oxygen vacancies in the source / drain regions of the oxide semiconductor channel layer.

[0109] In some embodiments, the method further includes forming a doped region in the source / drain region of the oxide semiconductor channel layer by exposing the source / drain region of the oxide semiconductor channel layer to a radical plasma of a dopant.

[0110] In some embodiments disclosed herein, the semiconductor device includes a substrate, an oxide semiconductor channel layer, a gate structure, a conductive layer, and source / drain electrodes. The oxide semiconductor channel layer is vertically stacked over the substrate. The gate structure surrounds each channel region of the oxide semiconductor channel layer. The conductive layer is vertically stacked over the substrate, wherein the conductive layer is interposed between adjacent oxide semiconductor channel layers. The source / drain electrodes are electrically connected to the source / drain regions of the oxide semiconductor channel layer, wherein the source / drain electrodes are in contact with the conductive layer.

[0111] In some embodiments, the source / drain electrodes surround each of the source / drain regions of the oxide semiconductor channel layer.

[0112] In some embodiments, the source / drain electrodes are separated from the source / drain regions of the oxide semiconductor channel layer via a conductive layer.

[0113] In some embodiments, the conductive layer comprises tantan nitride (TiN).

[0114] In some embodiments, the source / drain electrodes are in contact with the sidewalls of the conductive layer.

[0115] In some embodiments disclosed herein, the semiconductor device includes a substrate, an oxide semiconductor channel layer, a gate structure, a conductive layer, and source / drain electrodes. The oxide semiconductor channel layer is vertically stacked over the substrate. The gate structure surrounds each of the channel regions of the oxide semiconductor channel layer. The conductive layer is vertically stacked over the substrate, wherein the conductive layer is interposed between two adjacent oxide semiconductor channel layers. The source / drain electrodes are electrically connected to the source / drain regions of the oxide semiconductor channel layer, wherein the source / drain electrodes are in contact with the conductive layer, and wherein the source / drain electrodes surround each of the source / drain regions of the oxide semiconductor channel layer.

[0116] In some embodiments, the source / drain electrodes are in contact with the sidewalls of the conductive layer.

[0117] In some embodiments, gate spacers are located on opposite sides of the gate structure.

[0118] In some embodiments disclosed herein, the semiconductor device includes a substrate, an oxide semiconductor channel layer, a gate structure, a conductive layer, and source / drain electrodes. The oxide semiconductor channel layer is vertically stacked over the substrate. The gate structure surrounds each of the channel regions of the oxide semiconductor channel layer. The conductive layer is vertically stacked over the substrate, wherein the conductive layer is interposed between two adjacent oxide semiconductor channel layers. The source / drain electrodes are electrically connected to the source / drain regions of the oxide semiconductor channel layer, wherein the source / drain electrodes are in contact with the conductive layer, and wherein the source / drain electrodes are spaced apart from the source / drain regions of the oxide semiconductor channel layer via the conductive layer.

[0119] In some embodiments, a capping layer surrounds the gate structure, wherein the source / drain electrodes are located within the capping layer.

[0120] In some embodiments, the gate structure includes a high-k dielectric layer and a gate metal.

[0121] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: One substrate; Multiple oxide semiconductor channel layers are vertically stacked on top of the substrate; A gate structure surrounds each of the plurality of channel regions of the plurality of oxide semiconductor channel layers; Multiple conductive layers are vertically stacked above the substrate, wherein the multiple conductive layers are inserted between two adjacent oxide semiconductor channel layers in the multiple oxide semiconductor channel layers; as well as Multiple source / drain electrodes are electrically connected to multiple source / drain regions of the multiple oxide semiconductor channel layers, wherein the multiple source / drain electrodes are in contact with the multiple conductive layers.

2. The semiconductor device as claimed in claim 1, characterized in that, The plurality of source / drain electrodes surround each of the plurality of source / drain regions of the plurality of oxide semiconductor channel layers.

3. The semiconductor device as claimed in claim 1, characterized in that, The plurality of source / drain electrodes are separated from the plurality of source / drain regions of the plurality of oxide semiconductor channel layers via the plurality of conductive layers.

4. The semiconductor device as claimed in claim 1, characterized in that, The plurality of source / drain electrodes are in contact with the plurality of sidewalls of the plurality of conductive layers.

5. A semiconductor device, characterized in that, include: One substrate; Multiple oxide semiconductor channel layers are vertically stacked on top of the substrate; A gate structure surrounds each of the plurality of channel regions of the plurality of oxide semiconductor channel layers; Multiple conductive layers are vertically stacked above the substrate, wherein the multiple conductive layers are inserted between two adjacent oxide semiconductor channel layers in the multiple oxide semiconductor channel layers; as well as A plurality of source / drain electrodes are electrically connected to a plurality of source / drain regions of the plurality of oxide semiconductor channel layers, wherein the plurality of source / drain electrodes are in contact with the plurality of conductive layers, and wherein the plurality of source / drain electrodes surround each of the plurality of source / drain regions of the plurality of oxide semiconductor channel layers.

6. The semiconductor device as claimed in claim 5, characterized in that, The plurality of source / drain electrodes are in contact with the plurality of sidewalls of the plurality of conductive layers.

7. The semiconductor device as claimed in claim 5, characterized in that, It also includes multiple gate spacers located on opposite sides of the gate structure.

8. A semiconductor device, characterized in that, include: One substrate; Multiple oxide semiconductor channel layers are vertically stacked on top of the substrate; A gate structure surrounds each of the plurality of channel regions of the plurality of oxide semiconductor channel layers; Multiple conductive layers are vertically stacked above the substrate, wherein the multiple conductive layers are inserted between two adjacent oxide semiconductor channel layers in the multiple oxide semiconductor channel layers; as well as Multiple source / drain electrodes are electrically connected to multiple source / drain regions of the multiple oxide semiconductor channel layers, wherein the multiple source / drain electrodes are in contact with the multiple conductive layers, and wherein the multiple source / drain electrodes are spaced apart from the multiple source / drain regions of the multiple oxide semiconductor channel layers via the multiple conductive layers.

9. The semiconductor device as claimed in claim 8, characterized in that, It also includes a capping layer surrounding the gate structure, wherein the plurality of source / drain electrodes are located within the capping layer.

10. The semiconductor device as claimed in claim 8, characterized in that, The gate structure includes a high-k dielectric layer and a gate metal.

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