Semiconductor device structure

Abstract

The utility model provides a semiconductor device structure and a forming method thereof. The structure includes a first source / drain region, a second source / drain region disposed adjacent to the first source / drain region in a first direction, a third source / drain region, a fourth source / drain region disposed adjacent to the third source / drain region in the first direction, a first dielectric layer having a first end and a second end opposite the first end, and a conductive contact disposed between the first and third source / drain regions and between the second and fourth source / drain regions, the conductive contact disposed in the first dielectric layer. The structure further includes a conductive feature disposed in the first dielectric layer, and the conductive feature is electrically connected to the conductive contact.

Description

Technical Field

[0001] This utility model relates to a semiconductor device structure. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have resulted in generations of integrated circuits, each generation smaller and more complex than the last. In the evolution of integrated circuits, functional density (the number of interconnects per chip area) generally increases, while geometry (the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down generally benefits production efficiency and reduces associated costs. However, this miniaturization also increases the complexity of the processes and the manufacture of integrated circuits.

[0003] Therefore, it is necessary to improve the process and manufacturing of integrated circuits. Utility Model Content

[0004] This application provides a semiconductor device structure. The structure includes a first source / drain region, a second source / drain region disposed adjacent to the first source / drain region along a first direction, and a third source / drain region. The first source / drain region and the third source / drain region are aligned along a second direction substantially perpendicular to the first direction. The structure further includes a fourth source / drain region disposed adjacent to the third source / drain region along the first direction, and a first dielectric layer having a first end and a second end opposite to the first end. The first and second source / drain regions are disposed on opposite sides of the first end of the first dielectric layer, and the third and fourth source / drain regions are disposed on opposite sides of the second end of the first dielectric layer. The structure further includes conductive contacts disposed between the first and third source / drain regions and between the second and fourth source / drain regions, and the conductive contacts are disposed in the first dielectric layer. The structure further includes conductive features disposed in the first dielectric layer, and the conductive features are electrically connected to the conductive contacts.

[0005] This application provides a semiconductor device structure. The structure includes a first gate electrode layer, a first dielectric layer disposed in the first gate electrode layer, a second dielectric layer disposed in the first gate electrode layer, a conductive feature disposed in the first gate electrode layer between the first and second dielectric layers, a first conductive contact disposed on and in contact with the conductive feature, and a second conductive contact disposed on and in contact with the conductive feature. The first gate electrode layer is disposed between the first and second conductive contacts. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1-6 These are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0008] Figure 7A-10A It is according to some embodiments along Figure 6 The AA section is a cross-sectional side view of the various stages of manufacturing a semiconductor device structure.

[0009] Figure 7B-10B It is according to some embodiments along Figure 6 The BB line is a cross-sectional side view of the various stages of manufacturing a semiconductor device structure.

[0010] Figure 7C-10C It is according to some embodiments along Figure 6 The CC line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0011] Figure 11 According to some embodiments Figure 10A , 10B A top view of the semiconductor device structure shown in Figure 10C.

[0012] Figure 12A-18A It is according to some embodiments along Figure 11 The DD line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0013] Figure 12B-18B It is according to some embodiments along Figure 11 The EE is a cross-sectional side view of the various stages of manufacturing a semiconductor device structure.

[0014] Figure 19 According to some embodiments Figure 18A and 18B A top view of the semiconductor device structure shown.

[0015] Figure 20A , 20B 20C are various views of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0016] Figure 21A , 21B 21C and 21D are various views of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0017] Figure 22A , 22B 22C and 22D are various views of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0018] Figure 23A , 23B 23C is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0019] Figures 24A-26A According to some embodiments, after the semiconductor device structure is flipped, along Figure 21A The FF line cuts through the cross-sectional side view of each stage of the semiconductor device manufacturing structure.

[0020] Figure 24B-26B According to some embodiments, after the semiconductor device structure is flipped, along Figure 21A The GG line is a cross-sectional side view of the various stages of manufacturing a semiconductor device structure.

[0021] Figure 24C-26C According to some embodiments, after the semiconductor device structure is flipped, along Figure 21A The HH line is a cross-sectional side view of the various stages of manufacturing a semiconductor device structure.

[0022] Figure 27 This is a top view of a semiconductor device structure according to some embodiments, showing the location of conductive features.

[0023] Figure 28A-30A According to the alternative embodiments along Figure 6 The cross-sectional side view of each stage of manufacturing a semiconductor device structure, taken by line AA.

[0024] Figure 28B-30B It is according to some embodiments along Figure 6 The BB line is a cross-sectional side view of the various stages of manufacturing a semiconductor device structure.

[0025] Figure 28C-30C According to the alternative embodiments along Figure 6 The CC line is a cross-sectional side view of each stage of the manufacturing process of a semiconductor device structure.

[0026] Figure 31 According to some embodiments Figure 30A , 30B A top view of the semiconductor device structure shown in Figure 30C.

[0027] Figure 32A , 32B 32C and 32D are views of one of the various stages of manufacturing a semiconductor device structure according to an alternative embodiment.

[0028] Figure 33A , 33B 33C and 33D are views of one of the various stages of manufacturing a semiconductor device structure according to an alternative embodiment. Detailed Implementation

[0029] The following disclosure provides numerous different embodiments or instances for implementing various features of this subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," "over," "on," "top," "upper," and similar terms to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

[0031] The embodiments disclosed herein provide a semiconductor device structure having a power network that moves from the front-side to the back-side. Therefore, the wiring resources for both the back-side power supply and the front-side signals are relaxed.

[0032] While the embodiments disclosed herein are discussed in relation to nanostructure channel field-effect transistors (FETs), implementations of some aspects of this disclosure can be used in other processes and / or other devices, such as planar FETs, fin-FETs, horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs, and other suitable devices. Those skilled in the art will readily understand that other modifications that can be made are contemplated within the scope of this disclosure. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography with self-aligned processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A spacer wall is formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacer walls can be used to pattern the GAA structure.

[0033] Figure 1-27 An exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of this disclosure is shown. It should be understood that, for additional embodiments of this method, [further details may be needed]. Figure 1-27 Additional operations are provided before, during, and after the processes shown, and some of the operations described below can be substituted or omitted. The order of operations / processes is unrestricted and can be interchanged.

[0034] Figure 1-6 These are perspective views of various stages in the manufacture of a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a stacked semiconductor layer 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. On one hand, the insulating layer is an oxygen-containing layer.

[0035] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, for example, for an n-type field-effect transistor (NFET), the dopant may be phosphorus; and for a p-type field-effect transistor (PFET), the dopant may be boron.

[0036] The stacked semiconductor layer 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel field-effect transistors. In some embodiments, the stacked semiconductor layer 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stacked semiconductor layer 104 includes alternating first and second semiconductor layers 106, 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon (Si), and the second semiconductor layer 108 may be made of silicon germanium (SiGe). In some instances, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0037] The first and second semiconductor layers 106 and 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the stacked semiconductor layer 104 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0038] The first semiconductor layer 106, or a portion thereof, may form nanostructured channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term "nanostructure" is used herein to refer to any portion of material having a nanoscale or even micrometer-scale size and an extended shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to extended material portions with circular and substantially circular cross-sections, as well as beam-shaped or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0039] Each first semiconductor layer 106 may have a thickness ranging from approximately 5 nm to approximately 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from approximately 2 nm to approximately 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged as follows... Figure 1 The alternating arrangement shown is for illustrative purposes and is not intended to limit the scope of the claims beyond the specific descriptions. It is understood that any number of first and second semiconductor layers 106, 108 may be formed in the stacked semiconductor layer 104, and the number of layers depends on the predetermined number of channels for the semiconductor device structure 100.

[0040] exist Figure 2 In this embodiment, fin structures 112 are formed from stacked semiconductor layers 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the stacked semiconductor layers 104 using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure bake process, and developing the photoresist layer to form a photomask element including the photoresist layer. In some embodiments, an electron beam lithography process can be used to perform patterning of the photoresist layer to form the photomask element. The etching process forms trenches 114 in unprotected areas through the hard mask layer, through the stacked semiconductor layers 104, and into the substrate 101, thus leaving multiple extended fin structures 112. The trench 114 extends along the X direction. The trench 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0041] Figure 3In the process of forming fin structures 112, an insulating material 118 is formed on substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation such as chemical mechanical polishing (CMP) and / or etching-back is performed to expose the top of the fin structures 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric materials, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0042] exist Figure 4 In this configuration, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes a portion of the fin structure 112, such as the stacked semiconductor layer 104. The recess in insulating material 118 exposes a trench 114 between adjacent fin structures 112. Isolation region 120 can be formed using appropriate processes, such as dry etching, wet etching, or a combination thereof. The top surface of insulating material 118 may be at the same height as or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed with substrate 101.

[0043] exist Figure 5 In this embodiment, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning those layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers for the gate spacers 138 and anisotropically etching one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments two or more sacrificial gate structures 130 may be provided along the X direction.

[0044] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0045] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100.

[0046] exist Figure 6 In this configuration, the portion of fin structure 112 not covered by sacrificial gate structure 130 and gate spacer 138 is recessed to a level above, at, or below the top surface of isolation region 120. This partial recess of fin structure 112 can be achieved through an etching process, an isotropic or anisotropic etching process, and the etching process can be selective relative to one or more crystalline planes of substrate 101. The etching process can be dry etching such as RIE, NBE, or similar methods, or wet etching such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0047] Figure 7A , 7B 7C and 7C are respectively along Figure 6 A cross-sectional side view of the semiconductor device structure 100 taken by lines AA, BB and CC.

[0048] Figure 8A , 8B And 8C are respectively along some embodiments Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken from lines AA, BB, and CC. (See attached image.) Figure 8A As shown, the edge portions of each second semiconductor layer 108 of the stacked semiconductor layers 104 are horizontally removed along the X direction. Removing the edge portions of the second semiconductor layers 108 forms a cavity. In some embodiments, portions of the second semiconductor layers 108 are removed by a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0049] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 can be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), and then removing the portion of the conformal dielectric layer except for the dielectric spacers 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 caps the spacers 144 along the X-direction.

[0050] Figure 9A , 9B And 9C are respectively along some embodiments Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken from lines AA, BB, and CC. (See attached image.) Figure 9A and 9C As shown, the source / drain (S / D) region 146 is formed by the well portion 116. In some embodiments, the S / D region 146 can be grown vertically and horizontally to form facets that may correspond to crystal planes of the material used for the well portion 116. In this disclosure, the source region and the drain region are used interchangeably and have substantially the same structure. Furthermore, the source / drain(s) may refer individually or collectively to the source or drain, depending on the context. For an n-channel MOSFET, the S / D region 146 may be made of one or more layers of Si, SiP, SiC, and SiCP, or for a p-channel MOSFET, the S / D region 146 may be made of one or more layers of Si, SiGe, and Ge. For a p-channel MOSFET, a p-type dopant, such as boron (B), may also be included in the S / D region 146. The S / D region 146 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0051] Figure 10A , 10B And 10C are respectively along some embodiments Figure 6 A cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100, taken from lines AA, BB, and CC. Figure 10A , 10BIn the 10C configuration, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. CESL 162 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, or similar materials or combinations thereof. It can be formed using CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 on the semiconductor device structure 100. The material used for the ILD layer 164 may include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the ILD layer 164. The ILD layer 164 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 164 is formed, the semiconductor device structure 100 may be subjected to heat treatment to solidify the ILD layer 164.

[0052] After forming the ILD layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown below. Figure 10A and 10B As shown. In some embodiments, after a planarization process, the ILD layer 164 is recessed, and a dielectric layer 163 is formed on the recessed ILD layer 164. The dielectric layer 163 may include a nitride, such as silicon nitride, to protect the ILD layer 164 during subsequent processes. A second planarization process may be performed to remove a portion of the dielectric layer 163 formed on the sacrificial gate electrode layer 134.

[0053] Figure 11 According to some embodiments Figure 10A , 10B A top view of the semiconductor device structure 100 shown in Figure 10C. For clarity, Figure 11 Some components of the semiconductor device structure 100, such as dielectric layer 163 and CESL 162, are omitted. Figure 11 As shown, the semiconductor device structure 100 includes an S / D region 146 formed on the opposite side of the sacrificial gate electrode layer 134.

[0054] Figure 12A-18A It is according to some embodiments along Figure 11 The DD is a cross-sectional side view of each stage of the semiconductor device structure 100. Figure 12B-18B It is according to some embodiments along Figure 11 The image shows a cross-sectional side view of various stages of the semiconductor device structure 100, taken by line EE. Figure 12A and12B As shown, a mask layer 150 is formed on the dielectric layer 163 and the sacrificial gate electrode layer 134. The mask layer 150 may include a dielectric layer, such as SiN.

[0055] exist Figure 13A and 13B In this structure, a mask structure 152 is formed on a mask layer 150. In some embodiments, the mask structure 152 is a three-layer photoresist. For example, the mask structure 152 may include a bottom layer 154 and a middle layer 156 disposed on the bottom layer 154. The bottom layer 154 and the middle layer 156 are made of different materials, such that the optical properties and / or etching properties of the bottom layer 154 and the middle layer 156 are different from each other. In some embodiments, the bottom layer 154 may be a carbon layer, and the middle layer 156 may be a silicon-rich layer designed to provide etching selectivity between the middle layer 156 and the bottom layer 154. The mask structure 152 further includes a photoresist layer 158, which may be a chemically amplified photoresist layer and may be a positive or negative photoresist. The photoresist layer 158 may comprise a polymer, such as phenolic formaldehyde resin, poly(norbornene)-co-malaic anhydride (COMA) polymer, poly(4-hydroxystyrene) (PHS) polymer, phenolic (bakelite) polymer, polyethylene (PE) polymer, polypropylene (PP) polymer, polycarbonate polymer, polyester polymer, or acrylate-based polymers, such as poly(methyl methacrylate) (PMMA) polymer or poly(methacrylic acid) (PMAA) polymer. The photoresist layer 158 may be formed by spin-on coating. The photoresist layer 158 may be patterned to form openings 160 therein.

[0056] exist Figure 14A and 14B In this configuration, opening 160 extends to the middle layer 156, the bottom layer 154, and the mask layer 150. After opening 160 extends to the mask layer 150, the mask structure 152 can be removed. In some embodiments, a portion of the sacrificial gate electrode layer 134 is exposed in opening 160.

[0057] exist Figure 15A and 15BIn this process, the exposed portion of the sacrificial gate electrode layer 134 is removed. The exposed portion of the sacrificial gate electrode layer 134 can be removed by an etching process, such as a selective etching process that does not substantially affect the mask layer 150 and the sacrificial gate dielectric layer 132. Figure 16A and 16B In the process, the exposed portion of the sacrificial gate dielectric layer 132 is removed, and the exposed portion of the fin structure 112 is also removed.

[0058] exist Figure 17A and 17B In this process, the exposed portion of the fin structure 112 is removed. The exposed portion of the fin structure 112 can be removed by one or more etching processes. In some embodiments, the one or more etching processes can be selective etching processes that do not substantially affect the dielectric material in the mask layer 150, the dielectric spacer 144, and the insulating material 118. In some embodiments, the one or more etching processes can be anisotropic etching processes, and can retain portions of the first semiconductor layer 106 beneath the gate spacer 138 and the dielectric spacer 144, such as... Figure 17A As shown. Figure 17A and 17B As shown, the opening 160 extends into the substrate 101.

[0059] exist Figure 18A and 18B In this configuration, dielectric layer 166 is formed in opening 160. Dielectric layer 166 may include any suitable dielectric material. In some embodiments, dielectric layer 166 includes SiN. Dielectric layer 166 may also be formed on dielectric layer 163, and a planarization process such as CMP may be performed to remove portions of dielectric layer 166 formed on dielectric layer 163. The CMP process may also remove masking layer 150.

[0060] Figure 19 According to some embodiments Figure 18A and 18B A top view of the semiconductor device structure 100 shown. For clarity, Figure 19 Some components of the semiconductor device structure 100, such as dielectric layer 163 and CESL 162, are omitted. Figure 19 As shown, part of the sacrificial gate electrode layer 134 is replaced by a dielectric layer 166. Figures 12A to 18B The process described can be called continuous polysilicon on diffusion (CPODE) process, which forms an isolation region that divides the active area into multiple segments. Figure 19 The area shown can be an isolation zone, a passageway ( Figure 12BThe fin structure 112 shown is illustrated, and a portion of the sacrificial gate electrode layer 134 is removed and replaced with a dielectric layer 166, and the S / D region 146 on the opposite side of the dielectric layer 166 is a dummy S / D region. In some embodiments, the dielectric layers 166 are substantially parallel to each other, such as Figure 19 As shown. The semiconductor device structure 100 may include an active region ( Figure 19 (not shown in the image), for example, located in Figure 19 The active S / D regions 146 above and below the active S / D region 146, and the partially sacrificial gate electrode layer 134 configured across the active S / D region 146, for example Figure 18B The partially sacrificial gate electrode layer 134 is shown. During the formation of the dielectric layer 166, the partially sacrificial gate electrode layer 134 in the active region is covered by the mask layer 150.

[0061] Figure 20A , 20B 20C are various views of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. After forming a dielectric layer 166 in the isolation region, the semiconductor device structure 100 can have, in the active region, as shown in [the following diagram]: Figure 20A , 20B Various views are shown in Figure 20C. Next, the sacrificial gate structure 130 and the second semiconductor layer 108 are replaced with a gate dielectric layer 170 and a gate electrode layer 172. Removing the sacrificial gate structure 130 and the second semiconductor layer 108 forms openings between the gate spacer walls 138 and between the first semiconductor layer 106. The dielectric materials of dielectric layers 163 and 166 are substantially unaffected by the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. First, the sacrificial gate electrode layer 134 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 can be removed, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacer walls 138, dielectric layer 166, dielectric layer 163, and CESL 162.

[0062] A selective wet etching process can be used to remove portions of the second semiconductor layer 108. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe without substantially affecting the dielectric materials of Si, gate spacer 138, dielectric layer 166, dielectric layer 163, and dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using wet etchants such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), dry etchants such as fluorine-based gases (e.g., F2) or chlorine-based gases (e.g., Cl2), or any suitable isotropic etchant.

[0063] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed using CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed using CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed on the ILD layer 164 are then removed using, for example, CMP, until the top surface of the ILD layer 164 is exposed.

[0064] Figure 21A , 21B 21C and 21D are various views of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 21AThis is a top view of the isolation region of the semiconductor device structure 100. Figure 21B , 21C 21D are respectively along Figure 21A The image shows a cross-sectional side view of the semiconductor device structure 100, taken along lines FF, GG, and HH. In some embodiments, after forming the gate structure 174, a diced metal gate (CMG) process may be performed to divide the gate electrode layer 172 in the active region into two or more segments. Each segment of the gate electrode layer 172 serves as the gate electrode layer of an individual transistor. The CMG process may include forming trenches in the gate electrode layer 172 and the gate dielectric layer 170 and filling the trenches with a dielectric layer such as a SiN layer. After filling the trenches with the dielectric layer, a planarization process, such as a CMP process, may be performed to remove portions of the dielectric layer except for those in the trenches. Figure 21A , 21B As shown in Figures 21C and 21D, in some embodiments, dielectric layer 169 is formed at the boundary of the isolation region. Therefore, dielectric layer 166 and gate electrode layer 172 are separated by dielectric layer 169. Next, contact opening 176 is formed in the active region to expose active S / D region 146. Contact opening 176 can also be formed in the isolation region, such as... Figure 21A As shown. A patterned mask layer (not shown) may be formed first on the semiconductor device structure 100, and the pattern is transferred to the dielectric layer 163 and the ILD layer 164. In other words, portions of the dielectric layer 163 and the ILD layer 164 not covered by the patterned mask layer are removed. A portion of CESL 162 located in the active region is also removed to expose the active S / D region 146.

[0065] Figure 22A , 22B 22C and 22D are various views of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 22A This is a top view of the isolation region of the semiconductor device structure 100. Figure 22B , 22C 22D are respectively along Figure 21A A cross-sectional side view of the semiconductor device structure 100, taken from lines FF, GG, and HH. (See attached image.) Figures 22A to 22D As shown, a conductive contact 178 is formed in an opening 176 in the isolation region of the semiconductor device structure 100. The conductive contact 178 may be conductive and may include a material having one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN or TaN, and the conductive contact 178 may be formed by any suitable method, such as electrochemical plating (ECP) or PVD.

[0066] Figure 23A , 23B23C are various views of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. In the active region of the semiconductor device structure 100, contact openings are formed in the dielectric layer 163, the ILD layer 164, and the CESL 162 to expose active S / D regions 146, and conductive contacts 178 are formed in the contact openings. The contact openings and conductive contacts 178 are simultaneously formed in the active region and the isolation region. A silicide layer 179 may be disposed between the conductive contacts 178 and the corresponding S / D regions 146, such as... Figure 23A and 23C As shown. The silicide layer 179 may include one or more materials selected from WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.

[0067] It should be understood that the semiconductor device structure 100 may undergo further processing to form conductive contacts electrically connected to the gate electrode layer 172. Interconnect structures may be formed on the semiconductor device structure 100 to provide electrical paths to devices formed on the substrate 101. In some embodiments, conductive features, such as conductive lines, are formed in the interconnect structure and electrically connect conductive contacts 178 located in isolation regions and one or more conductive contacts 178 located in active regions. After the interconnect structure (including multiple layers of conductive features embedded in the inter-metal dielectric (IMD) layer, such as conductive vias and conductive lines) is completed, the semiconductor device structure 100 is flipped for back-side processing.

[0068] Figures 24A-26A According to some embodiments, after the semiconductor device structure 100 is flipped, along Figure 21A The FF line is a cross-sectional side view of each stage of the semiconductor device structure 100. Figure 24B-26B According to some embodiments, after the semiconductor device structure 100 is flipped, along Figure 21A The side view of the various stages of the semiconductor device structure 100, taken by line GG. Figure 24C-26C According to some embodiments, after the semiconductor device structure 100 is flipped, along Figure 21A The figures above are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100, taken by line HH. For clarity, interconnect structures formed on the semiconductor device structure 100 are omitted in the above figures. Figure 24A , 24B As shown in Figure 24C, the semiconductor device structure 100 is flipped for back-side processing. Next, as... Figure 25A , 25BAs shown in Figure 25C, substrate 101 is thinned to expose insulating material 118, well portion 116, and dielectric material 137. In some embodiments, dielectric layer 166 is also exposed. Thinning of substrate 101 can be performed by any suitable process. In some embodiments, a planarization process such as CMP is performed to thin substrate 101.

[0069] Next, as Figure 26A , 26B As shown in Figure 26C, conductive features 180 are formed in insulating material 118, CESL 162, ILD layer 164, and dielectric layer 166. Conductive features 180 may include conductive materials such as copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, silicon titanium nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, silicon tungsten nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof. Conductive features 180 are formed by any suitable process, such as PVD, CVD, or ECP. In some embodiments, a patterned mask layer (not shown) is first formed on the semiconductor device structure 100, and the patterned mask layer exposes a portion of the insulating material 118. The exposed portion of the insulating material 118 is then removed by one or more etching processes. One or more etching processes may also remove portions of CESL 162, ILD layer 164, and dielectric layer 166 located beneath the exposed portion of insulating material 118 until the conductive contact 178 located in the isolation region is exposed through an opening formed in insulating material 118, CESL 162, ILD layer 164, and dielectric layer 166. In some embodiments, a portion of conductive contact 178 may also be removed by one or more etching processes. Next, conductive features 180 are formed in the openings and electrically connected to conductive contact 178. In some embodiments, conductive features 180 extend into conductive contact 178, such as... Figure 26A , 26B As shown in Figure 26C, conductive feature 180 is electrically connected to conductive contact 178 in the isolation region, and is electrically connected to one or more conductive contacts 178 in the active region through conductive features located in the front interconnect structure. Therefore, power can be supplied from the back side to the active S / D region 146 via conductive feature 180. This improves the efficiency of the metal wiring. A planarization process, such as a CMP process, can be performed to remove a portion of the conductive feature 180 formed on the mask layer. The planarization process can also remove the mask layer, and the conductive feature 180, insulating material 118, and well portion 116 are exposed and have substantially coplanar top surfaces.

[0070] Subsequent processes may include forming interconnect structures on the back side of the semiconductor device structure 100. The interconnect structures may include conductive features, such as conductive lines, electrically connected to the conductive feature 180 to provide power to the conductive feature 180.

[0071] Figure 27 yes Figure 22A The semiconductor device structure 100 shown is a top view after the conductive feature 180 has been formed. The conductive feature 180 is... Figure 27 The conductive feature 180 is shown in dashed lines because it is not visible in the top view (the front is the top after the semiconductor device structure 100 is flipped back). Figure 27 As shown, conductive contact 178 and conductive feature 180 are located in an isolation region with dielectric layer 166 instead of gate electrode layer 172. Therefore, the risk of electrical short circuit between gate electrode layer 172 and conductive feature 180 / conductive contact 178 is reduced. Furthermore, the optical patterning window used to form dielectric layer 169 is enlarged because dielectric layer 169 is not formed in the region of conductive feature 180 and conductive contact 178 to isolate them from gate electrode layer 172. In addition, the CMP dishing effect is reduced during the formation of dielectric layer 169.

[0072] Figure 28A-30A According to the alternative embodiments along Figure 6 The cross-sectional side view of each stage of the semiconductor device structure 100, taken by line AA. Figure 28B-30B It is according to some embodiments along Figure 6 The BB line is a cross-sectional side view of each stage of the semiconductor device structure 100.

[0073] Figure 28C-30C According to the alternative embodiments along Figure 6 A cross-sectional side view of the various stages of the semiconductor device structure 100, taken by line CC. Figure 28A , 28B The semiconductor device structure 100 shown in 28C and Figure 10A , 10B The semiconductor device structure 100 shown in Figure 10C is at the same manufacturing stage. Next, the sacrificial gate structure 130 is replaced with a gate structure 174, which includes a gate dielectric layer 170 and a gate electrode layer 172, as shown... Figure 29A , 29B As shown in Figure 29C. Next, a CMG process is performed to form dielectric layers 169a and 169b in the gate electrode layer 172 and the gate dielectric layer 170. Figure 31 ),like Figure 30B As shown. Dielectric layer 169a also extends to CESL162 between dielectric layer 163, ILD layer 164 and S / D region 146, as... Figure 30C As shown.

[0074] Figure 31 According to some embodiments Figure 30A , 30BA top view of the semiconductor device structure 100 shown in Figure 30C. For clarity, Figure 31 Some components of the semiconductor device structure 100, such as dielectric layer 163 and CESL 162, are omitted. Figure 31 As shown, dielectric layers 169a and 169b are formed to divide the gate electrode layer 172 into multiple segments. Active regions 182 are defined between adjacent dielectric layers 169a and 169b. Each active region 182 may include multiple transistors, and each transistor may include an S / D region 146 and a segment of the gate electrode layer 172. The segments of the gate electrode layer 172 located between dielectric layers 169a are electrically isolated from the active regions 182 through the dielectric layers 169a.

[0075] Figure 32A , 32B 32C and 32D are views of one of the various stages of manufacturing a semiconductor device structure 100 according to an alternative embodiment. Figure 32A This is a top view of the semiconductor device structure 100. Figure 32B , 32C 32D are respectively along Figure 32A A cross-sectional side view of the semiconductor device structure 100, taken from lines LL, JJ, and KK. (See attached image.) Figure 32A , 32B As shown in 32C and 32D, a conductive contact 178 and a silicide layer 179 are formed. In some embodiments, as Figure 32A As shown, a plurality of conductive contacts 178 extend along the Y direction and are relatively transverse to the fin structure 112 (or the S / D region 146 and the first semiconductor layer 106). In some embodiments, the conductive contacts 178 may be continuous (connecting two or more S / D regions 146), such as Figure 32A and 32D As shown. Furthermore, a portion of the dielectric layer 169a located between adjacent gate electrode layers 172 can be removed, and the conductive contact 178 can extend horizontally between the two S / D regions 146, as shown. Figure 32D As shown.

[0076] Figure 33A , 33B 33C and 33D are views of one of the various stages of manufacturing a semiconductor device structure 100 according to an alternative embodiment. Figure 33A This is a top view of the semiconductor device structure 100. Figure 33B , 33C 33D are respectively along Figure 32AThe image shows a cross-sectional side view of the semiconductor device structure 100 taken along lines LL, JJ, and KK. After forming the conductive contacts 178, interconnect structures (not shown) can be formed on the semiconductor device structure 100. The semiconductor device structure 100 is then flipped for back-side processing. Processes can be performed on the semiconductor device structure 100. Figure 24A The processes described in -C, 25A-C, and 26A-C are used to form conductive feature 180. As... Figure 33A , 33B As shown in 33C and 33D, conductive features 180 are formed between dielectric layers 169a. Conductive features 180 can be electrically connected to conductive features, such as conductive lines in interconnect structures (not shown) located on the back side of the semiconductor device structure 100. Power can be supplied from the back side to conductive contacts 178 via conductive features 180. Due to the segment of the gate electrode layer 172 located in the active region 182 ( Figure 31 Electrically isolated from conductive features, such as... Figure 33A and 33C As shown, this eliminates the risk of an electrical short circuit between the conductive feature 180 and the gate electrode layer 172. Furthermore, the optical patterning window used to form the dielectric layers 169a and 169b is enlarged because no dielectric layers 169a and 169b are formed around the conductive feature 180 to isolate it from the gate electrode layer 172. In addition, the CMP depression effect is reduced during the formation of the dielectric layers 169a and 169b.

[0077] The embodiments disclosed herein provide a semiconductor device structure and a method of forming the same. In some embodiments, the semiconductor device structure includes a conductive feature 180 disposed in a dielectric layer 166. The dielectric layer 166 has a first end and a second end opposite to the first end. A first S / D region 146 is located on a first side of the first end of the dielectric layer 166, a second S / D region 146 is located on a second side of the dielectric layer 166 opposite to the first end, a third S / D region 146 is located on a third side of the second end of the dielectric layer 166, and a fourth S / D region 146 is located on a fourth side of the dielectric layer 166 opposite to the third side of the second end. The conductive feature 180 is electrically connected to a conductive contact 178, which is electrically connected to an active S / D region 146. Some embodiments may achieve advantages. For example, by forming the conductive feature 180 in the dielectric layer 166, the risk of an electrical short circuit between the conductive feature 180 and the gate electrode layer 172 is reduced.

[0078] One embodiment is a semiconductor device structure. The structure includes a first source / drain region, a second source / drain region disposed adjacent to the first source / drain region along a first direction, and a third source / drain region. The first and third source / drain regions are aligned along a second direction substantially perpendicular to the first direction. The structure further includes a fourth source / drain region disposed adjacent to the third source / drain region along the first direction, and a first dielectric layer having a first end and a second end opposite to the first end. The first and second source / drain regions are disposed on opposite sides of the first end of the first dielectric layer, and the third and fourth source / drain regions are disposed on opposite sides of the second end of the first dielectric layer. The structure further includes conductive contacts disposed between the first and third source / drain regions and between the second and fourth source / drain regions, and the conductive contacts are disposed in the first dielectric layer. The structure further includes conductive features disposed in the first dielectric layer, and the conductive features are electrically connected to the conductive contacts.

[0079] In some embodiments, the semiconductor device structure further includes a second dielectric layer disposed adjacent to the first dielectric layer, wherein conductive contacts and conductive features are disposed in the second dielectric layer. In some embodiments, the second dielectric layer has a third end and a fourth end opposite to the third end, a first source / drain region disposed adjacent to the third end of the second dielectric layer, and a third source / drain region disposed adjacent to the fourth end of the second dielectric layer. In some embodiments, the semiconductor device structure further includes a third dielectric layer disposed adjacent to the first dielectric layer, wherein conductive contacts and conductive features are disposed in the third dielectric layer. In some embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer are substantially parallel to each other. In some embodiments, the conductive features are disposed between the first source / drain region and the third source / drain region, and between the second source / drain region and the fourth source / drain region.

[0080] Another embodiment is a semiconductor device structure. This structure includes a first gate electrode layer, a first dielectric layer disposed in the first gate electrode layer, a second dielectric layer disposed in the first gate electrode layer, a conductive feature disposed in the first gate electrode layer between the first and second dielectric layers, a first conductive contact disposed on and in contact with the conductive feature, and a second conductive contact disposed on and in contact with the conductive feature. The first gate electrode layer is disposed between the first and second conductive contacts.

[0081] In some embodiments, the semiconductor device structure further includes a second gate electrode layer disposed adjacent to the first conductive contact, wherein the first dielectric layer and the second dielectric layer are disposed in the second gate electrode layer. In some embodiments, the conductive feature is disposed in the second gate electrode layer. In some embodiments, the semiconductor device structure further includes a first source / drain region disposed on a first side of a first end of the first gate electrode layer, a second source / drain region disposed on a second side opposite to the first side of the first end of the first gate electrode layer, a third source / drain region disposed on a third side of the second end opposite to the first end of the first gate electrode layer, and a fourth source / drain region disposed on a fourth side opposite to the third side of the second end of the first gate electrode layer. In some embodiments, the first conductive contact is electrically connected to the first source / drain region and the third source / drain region, and the second conductive contact is electrically connected to the second source / drain region and the fourth source / drain region. In some embodiments, the semiconductor device structure further includes a first silicide layer disposed between the first conductive contact and the first source / drain region, a second silicide layer disposed between the first conductive contact and the third source / drain region, a third silicide layer disposed between the second conductive contact and the second source / drain region, and a fourth silicide layer disposed between the second conductive contact and the fourth source / drain region. In some embodiments, the semiconductor device structure further includes a first plurality of semiconductor layers surrounded by a first gate electrode layer and a second plurality of semiconductor layers surrounded by the first gate electrode layer, wherein the first dielectric layer and the second dielectric layer are disposed between the first plurality of semiconductor layers and the second plurality of semiconductor layers.

[0082] Another embodiment is a method for forming a semiconductor device structure. This method includes forming a first sacrificial gate electrode layer and a second sacrificial gate electrode layer, replacing a portion of the first sacrificial gate electrode layer with a first dielectric layer, replacing a portion of the second sacrificial gate electrode layer with a second dielectric layer, and forming first, second, third, and fourth source / drain regions. The first and second source / drain regions are formed on opposite sides of a first end of the first dielectric layer, and the third and fourth source / drain regions are formed on opposite sides of a second end of the first dielectric layer. This method further includes forming an interlayer dielectric layer on the first, second, third, and fourth source / drain regions, forming conductive contacts in the first and second dielectric layers and the interlayer dielectric layer, flipping the semiconductor device structure, and forming conductive features in the first and second dielectric layers. The conductive features are electrically connected to the conductive contacts.

[0083] In some embodiments, the first and second dielectric layers are formed on an insulating material, and conductive features are formed within the insulating material. In some embodiments, the method further includes forming a first plurality of semiconductor layers and a second plurality of semiconductor layers, wherein a first sacrificial gate electrode layer and a second sacrificial gate electrode layer are formed on the first plurality of semiconductor layers and the second plurality of semiconductor layers. In some embodiments, the method further includes removing portions of the first plurality of semiconductor layers and the second plurality of semiconductor layers after removing portions of the first and second sacrificial gate electrode layers. In some embodiments, the method further includes removing a portion of the substrate located beneath the portions of the first plurality of semiconductor layers and the second plurality of semiconductor layers. In some embodiments, the first and second dielectric layers extend into the substrate. In some embodiments, the method further includes thinning the substrate to expose the insulating material and the first and second dielectric layers.

[0084] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, characterized in that, include: First source / drain region; The second source / drain region is disposed adjacent to the first source / drain region along the first direction; The third source / drain region, wherein the first source / drain region and the third source / drain region are aligned along a second direction substantially perpendicular to the first direction; The fourth source / drain region is disposed adjacent to the third source / drain region along the first direction; A first dielectric layer has a first end and a second end opposite to the first end, wherein a first source / drain region and a second source / drain region are disposed on opposite sides of the first end of the first dielectric layer, and a third source / drain region and a fourth source / drain region are disposed on opposite sides of the second end of the first dielectric layer. A conductive contact is disposed between the first source / drain region and the third source / drain region, and between the second source / drain region and the fourth source / drain region, wherein the conductive contact is disposed in the first dielectric layer; as well as A conductive feature is disposed in the first dielectric layer, wherein the conductive feature is electrically connected to the conductive contact.

2. The semiconductor device structure as described in claim 1, characterized in that, It further includes a second dielectric layer disposed adjacent to the first dielectric layer, wherein the conductive contacts and the conductive features are disposed in the second dielectric layer.

3. The semiconductor device structure as described in claim 2, characterized in that, It further includes a third dielectric layer disposed adjacent to the first dielectric layer, wherein the conductive contacts and the conductive features are disposed in the third dielectric layer.

4. The semiconductor device structure as described in claim 1, characterized in that, The conductive feature is disposed between the first source / drain region and the third source / drain region, and between the second source / drain region and the fourth source / drain region.

5. A semiconductor device structure, characterized in that, include: First gate electrode layer; A first dielectric layer is disposed in the first gate electrode layer; The second dielectric layer is disposed in the first gate electrode layer; A conductive feature is disposed in the first gate electrode layer between the first dielectric layer and the second dielectric layer; A first conductive contact is disposed on the conductive feature and in contact with the conductive feature; as well as A second conductive contact is disposed on and in contact with the conductive feature, wherein the first gate electrode layer is disposed between the first conductive contact and the second conductive contact.

6. The semiconductor device structure as described in claim 5, characterized in that, It further includes a second gate electrode layer disposed adjacent to the first conductive contact, wherein the first dielectric layer and the second dielectric layer are disposed in the second gate electrode layer.

7. The semiconductor device structure as described in claim 5, characterized in that, It further includes a first source / drain region disposed on a first side of a first end of the first gate electrode layer, a second source / drain region disposed on a second side opposite to the first side of the first end of the first gate electrode layer, a third source / drain region disposed on a third side of a second end opposite to the first end of the first gate electrode layer, and a fourth source / drain region disposed on a fourth side opposite to the third side of the second end of the first gate electrode layer.

8. The semiconductor device structure as described in claim 7, characterized in that, The first conductive contact is electrically connected to the first source / drain region and the third source / drain region, and the second conductive contact is electrically connected to the second source / drain region and the fourth source / drain region.

9. The semiconductor device structure as described in claim 8, characterized in that, It further includes a first silicide layer disposed between the first conductive contact and the first source / drain region, a second silicide layer disposed between the first conductive contact and the third source / drain region, a third silicide layer disposed between the second conductive contact and the second source / drain region, and a fourth silicide layer disposed between the second conductive contact and the fourth source / drain region.

10. The semiconductor device structure as claimed in claim 9, characterized in that, It further includes a first plurality of semiconductor layers surrounded by a first gate electrode layer and a second plurality of semiconductor layers surrounded by a first gate electrode layer, wherein the first dielectric layer and the second dielectric layer are disposed between the first plurality of semiconductor layers and the second plurality of semiconductor layers.

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