Harmonic indicating circuit

Abstract

The utility model relates to the technical field of electric power harmonic signal analysis, in particular to a harmonic indicating circuit, the overall structure of the harmonic indicating circuit does not need a processor for operation or Fourier transform, the circuit structure can be realized by adopting an analog device, the hardware resource investment is less, the result is clear at a glance, and the cost is low. According to the utility model, the harmonic display unit completes the latching of harmonic amplitude square and signal fixed period, the resetting of the harmonic signal extraction unit and the display of harmonic data, and because the frequency of a power frequency period is referred, the data refreshing fluency is high, the fundamental wave period is met, and the data is more reliable. According to the embodiment of the utility model, the analog circuit is formed by only depending on common electronic components such as the operational amplifier, the resistor, the capacitor and the triode, signals are operated and filtered, the reliability is high, the replaceability is good, and the maintenance and the precision adjustment of the circuit are facilitated.

Description

TECHNICAL FIELD

[0001] The utility model relates to power harmonic signal analysis technical field especially relates to a harmonic indicating circuit. BACKGROUND

[0002] Harmonic wave, from strict sense, harmonic wave is the electric quantity that the frequency is the integer times of fundamental wave in the current, generally refers to the Fourier series decomposition of the periodic non-sine electric quantity, the electric quantity generated by the current more than the fundamental wave frequency.

[0003] From the broad sense, since the effective component of alternating current network is single frequency, therefore any component different from the frequency of the fundamental wave can be called harmonic, at this time the meaning of the word "harmonic" has become somewhat inconsistent with the original intention. It is because of the broad concept of harmonic that there are "fractional harmonic", "interharmonic", "subharmonic" and so on.

[0004] The main reasons for the generation of harmonics are: due to the sine voltage applied to the nonlinear load, the fundamental current is distorted to generate harmonics. The main nonlinear loads include UPS, switching power supply, rectifier, frequency converter, inverter, etc.

[0005] At present, the main application mode for monitoring harmonics is to use wave recording, through waveform transformation, for example, the way of fast Fourier transform, to complete the monitoring of harmonics. The equipment used in this way usually has strong computing power, and the equipment is relatively large, but for maintenance personnel, they need a harmonic detection device that is easy to operate, the results are self-evident and relatively portable.

[0006] Therefore, it is necessary to develop a harmonic indicating circuit. CONTENT OF THE UTILITY MODEL

[0007] The utility model embodiment provides a kind of harmonic indicating circuit, to solve the problem of complex harmonic indicating device in prior art.

[0008] First, the utility model embodiment provides a kind of harmonic indicating circuit, comprising:

[0009] Harmonic signal extraction unit, periodic signal extraction unit and harmonic display unit;

[0010] The periodic signal extraction unit obtains the fundamental wave by low-pass filtering according to the input target waveform, and generates periodic indicating signal by integrating the fundamental wave and comparing the integral result of the fundamental wave with target voltage;

[0011] The harmonic signal extraction unit obtains a harmonic signal by high-pass filtering the input target waveform, squares the harmonic signal to obtain a square operation result, low-pass filters the square operation result to obtain a harmonic amplitude, and integrates the harmonic amplitude to obtain a harmonic integral indication signal;

[0012] The output end of the harmonic signal extraction unit and the output end of the cycle signal extraction unit are electrically connected to the input end of the harmonic display unit;

[0013] The harmonic display unit latches the harmonic integral indication signal according to the cycle indication signal, resets the integral result of the harmonic amplitude after latching, and displays the latched signal.

[0014] In some possible implementation manners, the cycle signal extraction unit comprises:

[0015] a first low-pass filter, a first voltage stabilizer, a second integral circuit, and a first voltage comparator;

[0016] The output end of the first low-pass filter is electrically connected to the input end of the second integral circuit, and the output end of the first voltage stabilizer and the output end of the second integral circuit are electrically connected to the inverting input end of the first voltage comparator and the non-inverting input end of the first voltage comparator, respectively;

[0017] When the output voltage of the second integral circuit is lower than the output voltage of the first voltage stabilizer, the first voltage comparator outputs a high level;

[0018] The harmonic signal extraction unit comprises a high-pass filter, a square circuit, a second low-pass filter, and a first integral circuit;

[0019] The output end of the high-pass filter is electrically connected to the input end of the square circuit, the output end of the square circuit is electrically connected to the input end of the second low-pass filter, and the output end of the second low-pass filter is electrically connected to the input end of the first integral circuit;

[0020] The reset end of the first integral circuit is electrically connected to the reset signal output end of the harmonic display unit, the harmonic display unit generates a reset signal at the reset signal output end after receiving the cycle indication signal and completing latching of the output voltage of the first integral circuit, and the first integral circuit is reset after receiving the reset signal.

[0021] In some possible implementation manners, the square circuit comprises a first addition module, an exponential module, and two sets of logarithmic modules;

[0022] The output ends of the two sets of logarithm modules are electrically connected with two input ends of the first adding module respectively, and the output end of the first adding module is electrically connected with the input end of the exponential module.

[0023] In some possible implementation manners, the logarithm module comprises:

[0024] a first operational amplifier, a first resistor, a second resistor and a first triode;

[0025] The base and the emitter of the first triode are electrically connected with the ground and the output end of the first operational amplifier respectively, the second end of the first resistor is electrically connected with the collector of the first triode and the inverting input end of the first operational amplifier, and the two ends of the second resistor are electrically connected with the non-inverting input end of the first operational amplifier and the ground respectively.

[0026] In some possible implementation manners, the exponential module comprises:

[0027] a ninth resistor, a tenth resistor, a third triode and a fourth operational amplifier;

[0028] The second end of the ninth resistor is electrically connected with the output end of the fourth operational amplifier, the emitter of the third triode is electrically connected with the first end of the ninth resistor and the inverting input end of the fourth operational amplifier, the two ends of the tenth resistor are electrically connected with the non-inverting input end of the fourth operational amplifier and the ground respectively, and the base of the third triode is electrically connected with the collector of the third triode.

[0029] In some possible implementation manners, the first integral circuit and the second integral circuit respectively comprise a fifth operational amplifier, an eleventh resistor and a fourth capacitor.

[0030] The first end of the fourth capacitor, the second end of the eleventh resistor and the inverting input end of the fifth operational amplifier are electrically connected, the non-inverting input end of the fifth operational amplifier is grounded, and the output end of the fifth operational amplifier is electrically connected with the second end of the fourth capacitor.

[0031] In some possible implementation manners, the harmonic display unit comprises a voltage latch reset circuit and a display circuit.

[0032] The voltage latch reset circuit starts to latch the harmonic integral indication signal when receiving the cycle indication signal and resets the integral result of the harmonic amplitude after successful latching.

[0033] The display circuit displays the latched integral indication signal.

[0034] In some possible implementation, the voltage latch reset circuit comprises a first addition module, a first field effect transistor, a charging module, a differential module, a second voltage comparator, a third voltage comparator, a NAND gate and an AND gate.

[0035] The first addition module sums the received stabilized voltage signal and the harmonic integral indication signal output by the harmonic signal extraction unit to obtain a harmonic integral accumulation indication signal.

[0036] When the first field effect transistor is saturated and turned on, the harmonic integral accumulation indication signal charges the charging module.

[0037] The differential module differentiates the charging voltage of the charging module to obtain a differential indication signal.

[0038] The second voltage comparator compares the stabilized voltage signal with the charging of the charging module to output a charging comparison signal.

[0039] The NAND gate performs NAND operation according to the differential indication signal and the charging comparison signal to obtain a first bit logic operation result.

[0040] The AND gate performs AND operation according to the periodic indication signal and the first bit logic operation result to obtain a second logic operation result.

[0041] The first field effect transistor is saturated and turned on or cut off according to the second logic operation result.

[0042] The output end of the first addition module is electrically connected to the source of the first field effect transistor, the drain of the first field effect transistor is electrically connected to the charging input end of the charging module, the input end of the differential module is electrically connected to the charging part of the charging module, the positive input end of the second voltage comparator is electrically connected to the charging part of the charging module, and the output end of the second voltage comparator and the output end of the differential module are respectively electrically connected to the two input ends of the NAND gate.

[0043] The first input end of the AND gate is electrically connected to the output end of the NAND gate.

[0044] In some possible implementation, the voltage latch reset circuit further comprises a diode, and the anode of the diode is electrically connected to the output end of the NAND gate.

[0045] In some possible implementation, the display circuit comprises an analog-digital conversion chip and an LED numeral tube.

[0046] The analog input end of the analog-digital conversion chip is electrically connected to the charging part of the charging module, and the LED numeral tube is electrically connected to the display output end of the analog-digital conversion chip.

[0047] The utility model embodiment has the beneficial effects compared with prior art that:

[0048] The utility model embodiment discloses a harmonic indicating circuit, and the overall structure does not need a processor to operate, does not need to carry out Fourier transform, the circuit structure can adopt analog device to realize, and the hardware resource is less, and the result is self-evident, and because the circuit adopts conventional non-programming device to realize, when the fault occurs, it is convenient to replace, and the maintenance cost is low

[0049] The utility model discloses a harmonic display unit completes the latching of harmonic amplitude square sum signal fixed period, the reset of harmonic signal extraction unit and the display of harmonic data, because the frequency of reference power frequency period, therefore data refresh fluency is high, and it is in line with the period of fundamental wave, and data is more reliable.

[0050] The utility model embodiment only relies on the operational amplifier, resistance, capacitor and triode common electronic component and constitutes analog circuit, carries out the operation, filter processing to signal, and the reliability is high, and the replaceability is good, and it is convenient to overhaul and precision adjustment of circuit. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical scheme in the utility model embodiment, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description, and obviously, the drawings in the following description are only some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to these drawings without paying the creativity labor.

[0052] Figure 1 It is the functional block diagram of the harmonic indicating circuit provided by the utility model embodiment;

[0053] Figure 2 It is the principle diagram of low pass filter provided by the utility model embodiment;

[0054] Figure 3 It is the principle diagram of high pass filter provided by the utility model embodiment;

[0055] Figure 4 It is the principle diagram of square circuit provided by the utility model embodiment;

[0056] Figure 5 It is the principle diagram of integral circuit provided by the utility model embodiment;

[0057] Figure 6 It is the principle diagram of second filter provided by the utility model embodiment;

[0058] Figure 7It is the voltage latch and reset circuit schematic diagram provided by the embodiment of the utility model.

[0059] Figure 8 It is the harmonic display unit schematic diagram provided by the embodiment of the utility model. Specific implementation

[0060] In the following description, for the purpose of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc., in order to thoroughly disclose the embodiments of the utility model. However, it should be clear to those skilled in the art that the utility model can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices and methods are omitted to avoid unnecessary details that hinder the description of the utility model.

[0061] In order to make the purpose, technical scheme and advantages of the utility model more clear, the following will be explained by specific embodiments in conjunction with the drawings.

[0062] The embodiments of the utility model will be described in detail below, and the present example is implemented on the premise of the technical scheme of the utility model, and detailed implementation and specific operation process are given, but the protection scope of the utility model is not limited to the following embodiments.

[0063] Figure 1 The harmonic indication circuit function block diagram provided by the embodiment of the utility model.

[0064] As shown in Figure 1 The overall structure diagram of the harmonic indication circuit provided by the embodiment of the utility model is shown, and the details are as follows:

[0065] A harmonic indication circuit, comprising: a harmonic signal extraction unit, a periodic signal extraction unit and a harmonic display unit;

[0066] The periodic signal extraction unit obtains the fundamental wave through the low-pass filtering mode according to the input target waveform, generates the periodic indication signal by integrating the fundamental wave and comparing the fundamental wave integral result with the target voltage;

[0067] The harmonic signal extraction unit obtains the harmonic through the high-pass filtering mode according to the input target waveform, obtains the square operation result by square operation on the harmonic, obtains the harmonic amplitude by low-pass filtering the square operation result, and obtains the harmonic integral indication signal by integrating the harmonic amplitude;

[0068] The output end of the harmonic signal extraction unit and the output end of the periodic signal extraction unit are respectively electrically connected with the input end of the harmonic display unit;

[0069] The harmonic display unit latches the harmonic integral indication signal according to the period indication signal, resets the integral result of the harmonic amplitude after latching, and displays the latched signal.

[0070] Exemplarily, in the embodiment of the utility model, the fundamental wave and the harmonic of the measured target waveform are obtained through the low-pass filter and the high-pass filter respectively, the harmonic is integrated after being squared and low-pass filtered again to obtain the integral value of the harmonic (all harmonics), and the fundamental wave obtained by the low-pass filter is compared with the voltage output by the precision stabilized power supply after being integrated to generate the period signal.

[0071] For the harmonic square, the following formula can be seen:

[0072]

[0073] In the above formula, sin(nω0t) is the n-th harmonic, and after squaring operation, the harmonic amplitude square quantity (low frequency) and the 2n-th harmonic component are obtained, and the 2n-th harmonic component can be filtered out through low frequency filtering, and only the harmonic amplitude square quantity remains, when multiple harmonics are squared, the harmonic amplitude square obtained by low-pass filtering is the sum of the square of multiple harmonic amplitudes, in other words, the sum of the square of all harmonic amplitudes is obtained.

[0074] The integral of the sum of the square of all harmonic amplitudes in a period (for example, 50Hz power frequency, the period is 20ms) obtains the sum of the square of harmonic amplitudes in a period.

[0075] In order to obtain the period signal, in the period signal extraction unit, the fundamental wave (obtained by the low-pass filter) is integrated, as we know, when the sine wave is integrated, the integral value is 0 only at the end of the period, this value is compared with the voltage output by a precision stabilized power supply (for example, 0.1v), when the voltage is lower than the voltage, it indicates that the current period is about to end and a new period is about to start, at this time, the sum of the square of harmonic amplitudes in the harmonic signal extraction unit is latched and displayed by the harmonic display unit, when the latching is completed, the integral circuit of the harmonic signal extraction unit is reset to perform a new round of integral operation.

[0076] It can be seen that the overall structure of the utility model does not need a processor to perform operation, nor needs to perform Fourier transform, the circuit structure can be realized by using analog devices, the hardware resource investment is small, the result is self-evident, and since the circuit is realized by using conventional non-programmed devices, when a fault occurs, it is convenient to replace, and the maintenance cost is low.

[0077] The above is the overall structure of the utility model, in order to realize the above structure, the embodiment of the utility model combines Figures 2-8 The following aspects are discussed in detail.

[0078] In some embodiments, the periodic signal extraction unit comprises:

[0079] a first low-pass filter, a first voltage stabilizer, a second integration circuit, and a first voltage comparator;

[0080] An output terminal of the first low-pass filter is electrically connected to an input terminal of the second integration circuit, an output terminal of the first voltage stabilizer and an output terminal of the second integration circuit are respectively electrically connected to an inverting input terminal of the first voltage comparator and a non-inverting input terminal of the first voltage comparator;

[0081] When the output voltage of the second integration circuit is lower than the output voltage of the first voltage stabilizer, the first voltage comparator outputs a high level;

[0082] The harmonic signal extraction unit comprises a high-pass filter, a squaring circuit, a second low-pass filter, and a first integration circuit.

[0083] An output terminal of the high-pass filter is electrically connected to an input terminal of the squaring circuit, an output terminal of the squaring circuit is electrically connected to an input terminal of the second low-pass filter, and an output terminal of the second low-pass filter is electrically connected to an input terminal of the first integration circuit.

[0084] A reset terminal of the first integration circuit is electrically connected to a reset signal output terminal of the harmonic display unit, the harmonic display unit generates a reset signal at the reset signal output terminal after receiving the periodic indication signal and completing the latching of the output voltage of the first integration circuit, and the first integration circuit is reset after receiving the reset signal.

[0085] In some embodiments, the squaring circuit comprises a first addition module, an exponential module, and two sets of logarithmic modules.

[0086] Output terminals of the two sets of logarithmic modules are respectively electrically connected to two input terminals of the first addition module, and an output terminal of the first addition module is electrically connected to an input terminal of the exponential module.

[0087] In some embodiments, the logarithmic module comprises:

[0088] a first operational amplifier, a first resistor, a second resistor, and a first triode;

[0089] A base and an emitter of the first triode are respectively electrically connected to ground and an output terminal of the first operational amplifier, a second terminal of the first resistor is electrically connected to a collector of the first triode and an inverting input terminal of the first operational amplifier, and two terminals of the second resistor are respectively electrically connected to a non-inverting input terminal of the first operational amplifier and ground.

[0090] In some embodiments, the index module comprises:

[0091] a ninth resistor, a tenth resistor, a third transistor, and a fourth operational amplifier;

[0092] The second end of the ninth resistor is electrically connected to the output end of the fourth operational amplifier, the emitter of the third transistor is electrically connected to the first end of the ninth resistor and the inverting input end of the fourth operational amplifier, the two ends of the tenth resistor are respectively electrically connected to the non-inverting input end of the fourth operational amplifier and the ground, and the base of the third transistor is electrically connected to the collector of the third transistor.

[0093] In some possible implementation embodiments, the first integration circuit and the second integration circuit respectively comprise a fifth operational amplifier, an eleventh resistor, and a fourth capacitor.

[0094] The first end of the fourth capacitor, the second end of the eleventh resistor, and the inverting input end of the fifth operational amplifier are electrically connected, the non-inverting input end of the fifth operational amplifier is grounded, and the output end of the fifth operational amplifier is electrically connected to the second end of the fourth capacitor.

[0095] Exemplarily, as shown in Figure 1 , in the period signal extraction unit, the fundamental wave signal obtained by the first low-pass filter is integrated by the second integration circuit, and the integration result and the low voltage output by the first stable voltage source are sent to the first voltage comparator for comparison. When the integration result is lower than the low voltage output by the first stable voltage source, the first voltage comparator outputs a high level, and the signal serves as an indication signal of the period.

[0096] On the other hand, the harmonic wave output by the high-pass filter of the harmonic wave signal extraction unit is squared by the squaring circuit (analog circuit), and then filtered by the second low-pass filter to obtain harmonic amplitude squares, and the squares are sent to the first integration circuit for integration operation.

[0097] In circuit implementation, Figure 2 A high-pass filter is shown, which comprises an input capacitor C21 and a grounding resistor R21 connected in series, one end of the capacitor C21 as an input, the other end as an output, and the end as an output grounded through the grounding resistor R21.

[0098] Figure 3 A low-pass filter is shown, which comprises two resistors R31 and R32 connected in series, the end of R31 grounded through a capacitor C31, the end of R32 grounded through a capacitor C32, the non-grounded end of R31 as an input, and the non-grounded end of R32 as an output. Both the first low-pass filter and the second low-pass filter can adopt this form.

[0099] Figure 4A square circuit is shown, which includes two logarithm circuits 411 and 412, an addition circuit 420 and an exponential module 430, wherein the circuits with Amp41 and Amp42 as the core are two logarithm circuits, the circuit with Amp43 as the core is an addition circuit, and the circuit with Amp44 as the core is an exponential module. The two logarithm circuits are the same in structure, the first logarithm circuit includes an operational amplifier Amp41, resistors R41 and R42, and a transistor Q41, the second logarithm circuit includes an operational amplifier Amp42, resistors R43 and R44, and a transistor Q42, the addition circuit includes an operational amplifier Amp43, resistors R45, R46, R47 and R48, and the exponential module includes an operational amplifier Amp44, resistors R49 and R50, and a transistor Q43.

[0100] Figure 5 An integral circuit (analog circuit) is shown, which is a proportional integral circuit with an operational amplifier Amp51 as the core, and includes an operational amplifier Amp51, a resistor R51 and a capacitor C51. The circuit inputs a smoothed signal smoothed by a low-pass filter, and performs proportional and integral operations on the smoothed signal. The first integral circuit and the second integral circuit can both adopt the circuit.

[0101] Figure 6 A voltage comparator is shown, which is realized with an operational amplifier Amp61 as the core. When applied in a circuit of a periodic signal extraction unit, the inverting input end inputs the output of a first stable voltage supply, and the non-inverting input end inputs the output of a second integral circuit.

[0102] In some possible implementation manners, the harmonic display unit includes a voltage latch reset circuit and a display circuit.

[0103] The voltage latch reset circuit starts to latch the harmonic integral indication signal upon receiving the periodic indication signal, and resets the integral result of the harmonic amplitude after successful latching.

[0104] The display circuit displays the latched integral indication signal.

[0105] In some possible implementation manners, the voltage latch reset circuit includes a first addition module, a first field effect transistor, a charging module, a differential module, a second voltage comparator, a third voltage comparator, a NAND gate and an AND gate.

[0106] The first addition module sums the received stable voltage signal and the harmonic integral indication signal output by the harmonic signal extraction unit to obtain a harmonic integral accumulation indication signal.

[0107] The first field effect transistor is saturated and turned on, the harmonic integral accumulation instruction signal charges the charging module;

[0108] The differential module differentiates the charging voltage of the charging module to obtain a differential instruction signal;

[0109] The second voltage comparator compares the voltage signal with the charging of the charging module to output a charging comparison signal;

[0110] The NAND gate performs NAND operation according to the differential instruction signal and the charging comparison signal to obtain a first bit logical operation result;

[0111] The AND gate performs AND operation according to the period instruction signal and the first bit logical operation result to obtain a second logical operation result;

[0112] The first field effect transistor is saturated and turned on or cut off according to the second logical operation result;

[0113] The output end of the first addition module is electrically connected with the source electrode of the first field effect transistor, the drain electrode of the first field effect transistor is electrically connected with the charging input end of the charging module, the input end of the differential module is electrically connected with the charging part of the charging module, the positive phase input end of the second voltage comparator is electrically connected with the charging part of the charging module, and the output end of the second voltage comparator and the output end of the differential module are respectively electrically connected with the two input ends of the NAND gate;

[0114] The first input end of the AND gate is electrically connected with the output end of the NAND gate.

[0115] In some possible implementation manners, the voltage latch reset circuit further comprises a diode, the anode of the diode is electrically connected with the output end of the NAND gate.

[0116] In some possible implementation manners, the display circuit comprises an analog-digital conversion chip and an LED number tube.

[0117] The analog input end of the analog-digital conversion chip is electrically connected with the charging part of the charging module, and the LED number tube is electrically connected with the display output end of the analog-digital conversion chip.

[0118] Exemplarily, as shown in Figure 1 The harmonic display unit is composed of a voltage latch reset circuit and a display circuit. When the period instruction signal is received, the voltage latch reset circuit opens the latch path, latches the voltage signal from the first integral circuit, and when the latching is completed, the voltage latch reset circuit closes the latch path and resets the first integral circuit. The display circuit displays according to the latched voltage.

[0119] Figure 7 The voltage latch reset circuit schematic diagram is shown, in which the operational amplifier Amp71 is the core, and resistors R71, R72, R73 and R74 constitute an addition circuit, which adds the result of the first integrator with the output of the precision voltage regulator. The latch path is controlled by the field effect transistor Q71. When the field effect transistor is saturated and turned on, the path is opened, and when it is cut off, the path is closed.

[0120] The resistor R75 and the capacitor C71 form a charging module. When the field effect transistor Q71 is saturated and turned on, the operational amplifier Amp71 charges and discharges the capacitor C71 through the resistor R75.

[0121] The timing of the charging and discharging is determined by the output of the differential circuit and the second voltage comparator. When the judgment condition is met, the NAND gate G1 outputs low level, discharges the capacitor C51 of the first integration circuit, and completes the reset.

[0122] The differential circuit includes a differentiator with an operational amplifier Amp73 as the core and a second voltage comparator with an operational amplifier Amp74 as the core. The inverting input of the operational amplifier Amp73 of the differentiator is electrically connected to the charging end of the capacitor C71 through the capacitor C72, the non-inverting input of the operational amplifier Amp73 of the differentiator is grounded, the inverting input of the operational amplifier Amp73 of the differentiator is connected to the output of the first voltage regulator through the resistor R76, and the output of the operational amplifier Amp73 is electrically connected to the inverting input of the operational amplifier Amp74. The non-inverting input of the operational amplifier Amp74 is connected to the output voltage of the first voltage regulator. When the charging voltage rate is very small, the operational amplifier Amp74 outputs high level.

[0123] In addition, the third voltage comparator has an operational amplifier Amp72 as the core, and the inverting input of the operational amplifier Amp74 is connected to the output voltage of the first voltage regulator, and the non-inverting input is electrically connected to the charging end of the capacitor C71.

[0124] In some scenarios, the output end of the NAND gate G1 is provided with a diode D1, the anode of the diode is electrically connected to the output end of the NAND gate G1, and the cathode of the diode is electrically connected to the output of the first integrator. When the NAND gate G1 outputs low level, the reset of the first integrator is completed (so that the output of the first integrator is 0 voltage).

[0125] The output of the NAND gate and the output of the first voltage comparator are respectively taken as two inputs of the AND gate. When the NAND gate outputs high level and the first voltage comparator outputs high level, the AND gate G2 outputs high level, at this time the field effect transistor Q71 is saturated and turned on, otherwise it is cut off.

[0126] As Figure 8As shown, the utility model utilizes ICL7107 to complete the conversion of analog to digital, and carries out data display through LED nixie tube, the non-ground terminal of capacitor C71 is connected to the analog input end (the non-connection chip end of R84, the chip 30 pin is grounded) of the chip, the connection of ICL7107 and LED nixie tube is prior art, can be referenced Figure 8 , also can refer to technical manual, no more.

[0127] The utility model discloses a harmonic display unit completes the latching of harmonic amplitude square and signal fixed period, the reset of harmonic signal extraction unit and the display of harmonic data, because the frequency of reference power frequency period, therefore data refresh fluency is high, and it is in line with the period of fundamental wave, and data is more reliable.

[0128] It should be understood that the size of the serial number of each step in the above-mentioned embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the utility model.

[0129] The following is the device embodiment of the utility model, and the details not described in detail can be referred to the corresponding method embodiment described above.

Claims

1. A harmonic indicator circuit, characterized in that, include: Harmonic signal extraction unit, periodic signal extraction unit, and harmonic display unit; The periodic signal extraction unit obtains the fundamental wave based on the input target waveform by low-pass filtering, and generates a periodic indication signal by integrating the fundamental wave and comparing the integration result with the target voltage. The harmonic signal extraction unit obtains harmonics by high-pass filtering based on the input target waveform, performs a square operation on the harmonics to obtain the square operation result, performs a low-pass filtering on the square operation result to obtain the harmonic amplitude, and integrates the harmonic amplitude to obtain the harmonic integral indication signal; The output terminals of the harmonic signal extraction unit and the periodic signal extraction unit are electrically connected to the input terminal of the harmonic display unit, respectively. The harmonic display unit latches the harmonic integral indicator signal according to the period indicator signal, resets the integral result of the harmonic amplitude after latching, and displays the latched signal.

2. The harmonic indicator circuit according to claim 1, characterized in that, The periodic signal extraction unit includes: A first low-pass filter, a first regulated power supply, a second integrating circuit, and a first voltage comparator; The output terminal of the first low-pass filter is electrically connected to the input terminal of the second integrator circuit, and the output terminal of the first regulated power supply and the output terminal of the second integrator circuit are respectively electrically connected to the inverting input terminal and the non-inverting input terminal of the first voltage comparator. When the output voltage of the second integrator is lower than the output voltage of the first regulated power supply, the first voltage comparator outputs a high level. The harmonic signal extraction unit includes: a high-pass filter, a square circuit, a second low-pass filter, and a first integrating circuit; The output terminal of the high-pass filter is electrically connected to the input terminal of the square circuit, the output terminal of the square circuit is electrically connected to the input terminal of the second low-pass filter, and the output terminal of the second low-pass filter is electrically connected to the input terminal of the first integrator circuit. The reset terminal of the first integrating circuit is electrically connected to the reset signal output terminal of the harmonic display unit. After receiving the period indication signal and completing the latching of the output voltage of the first integrating circuit, the harmonic display unit generates a reset signal at the reset signal output terminal. The first integrating circuit is reset after receiving the reset signal.

3. The harmonic indicator circuit according to claim 2, characterized in that, The square circuit includes: a first addition module, an exponent module, and two sets of logarithmic modules; The outputs of the two logarithmic modules are electrically connected to the two inputs of the first addition module, and the output of the first addition module is electrically connected to the input of the exponential module.

4. The harmonic indicator circuit according to claim 3, characterized in that, The logarithmic module includes: The first operational amplifier, the first resistor, the second resistor, and the first transistor; The base and emitter of the first transistor are electrically connected to ground and the output terminal of the first operational amplifier, respectively. The second end of the first resistor is electrically connected to the collector of the first transistor and the inverting input terminal of the first operational amplifier. The two ends of the second resistor are electrically connected to the non-inverting input terminal of the first operational amplifier and ground, respectively.

5. The harmonic indicator circuit according to claim 3, characterized in that, The index module includes: Ninth resistor, tenth resistor, third transistor, and fourth operational amplifier; The second end of the ninth resistor is electrically connected to the output terminal of the fourth operational amplifier. The emitter of the third transistor is electrically connected to the first end of the ninth resistor and the inverting input terminal of the fourth operational amplifier. The two ends of the tenth resistor are electrically connected to the non-inverting input terminal of the fourth operational amplifier and ground, respectively. The base of the third transistor is electrically connected to the collector of the third transistor.

6. The harmonic indicator circuit according to claim 2, characterized in that, The first integrating circuit and the second integrating circuit each include: a fifth operational amplifier, an eleventh resistor, and a fourth capacitor; The first terminal of the fourth capacitor, the second terminal of the eleventh resistor, and the inverting input terminal of the fifth operational amplifier are electrically connected. The non-inverting input terminal of the fifth operational amplifier is grounded, and the output terminal of the fifth operational amplifier is electrically connected to the second terminal of the fourth capacitor.

7. The harmonic indicator circuit according to any one of claims 1-6, characterized in that, The harmonic display unit includes: a voltage latch reset circuit and a display circuit; The voltage latch-reset circuit starts latching the harmonic integral indicator signal when it receives the period indicator signal and resets the integral result of the harmonic amplitude after successful latching. The display circuit displays the latched integral indication signal.

8. The harmonic indicator circuit according to claim 7, characterized in that, The voltage latch reset circuit includes: a first adder module, a first field-effect transistor, a charging module, a differentiator module, a second voltage comparator, a third voltage comparator, a NAND gate, and an AND gate; The first addition module sums the received regulated voltage signal and the harmonic integral indication signal output by the harmonic signal extraction unit to obtain the harmonic integral accumulation indication signal. When the first field-effect transistor is saturated and turned on, the harmonic integral accumulation indicator signal charges the charging module; The differential module performs differential calculations on the charging voltage of the charging module to obtain a differential indication signal; The second voltage comparator compares the regulated voltage signal with the charging module's charging signal and outputs a charging comparison signal; The NAND gate performs NAND operation based on the differential indication signal and the charging comparison signal to obtain the first logical operation result. The AND gate performs an AND operation based on the period indicator signal and the result of the first bit logic operation to obtain the second logic operation result; The first field-effect transistor is either saturated and turned off according to the result of the second logic operation; The output terminal of the first adder module is electrically connected to the source of the first field-effect transistor, the drain of the first field-effect transistor is electrically connected to the charging input terminal of the charging module, the input terminal of the differentiator module is electrically connected to the charging section of the charging module, the non-inverting input terminal of the second voltage comparator is electrically connected to the charging section of the charging module, and the output terminals of the second voltage comparator and the differentiator module are respectively electrically connected to the two input terminals of the NAND gate. The first input terminal of the AND gate is electrically connected to the output terminal of the NAND gate.

9. The harmonic indicator circuit according to claim 8, characterized in that, The voltage latch reset circuit also includes a diode, the anode of which is electrically connected to the output terminal of the NAND gate.

10. The harmonic indicator circuit according to claim 9, characterized in that, The display circuit includes an analog-to-digital converter chip and an LED digital tube; The analog input terminal of the digital-to-digital converter chip is electrically connected to the charging section of the charging module, and the LED digital tube is electrically connected to the display output terminal of the analog-to-digital converter chip.

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