Bearing device of wafer memory and wafer memory with bearing device

Abstract

The utility model relates to the field of semiconductor production and manufacturing equipment, and provides a bearing device of a wafer memory and the wafer memory with the bearing device. The bearing device comprises a bearing table, a first positioning structure and a second positioning structure. The carrier is configured to support any one of a first wafer cassette and a second wafer cassette, the first wafer cassette and the second wafer cassette having different sizes to store two types of wafers having different sizes, respectively. The first positioning structure is configured to cooperate with a first wafer cassette placed on the bearing table to limit movement of the first wafer cassette on the bearing table. The second positioning structure is configured to cooperate with a second wafer cassette placed on the bearing table to limit movement of the first wafer cassette on the bearing table. According to the bearing device provided by the invention, the bearing table can support the wafer boxes of two sizes, and the two positioning structures of the bearing device can respectively position the wafer boxes of two sizes, so that the bearing device can be suitable for the wafer boxes of two sizes, and the reduction of the manufacturing cost is facilitated.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing equipment, and more specifically to a carrier device for a wafer memory and a wafer memory having the carrier device. Background Technology

[0002] Wafer memory is a common piece of equipment in wafer manufacturing. It typically includes a carrier unit to hold the wafer cassette containing the wafers. Different sized wafer cassettes are used to store wafers of different sizes, and these different sizes require different types of carrier units. A single type of wafer memory usually has only one carrier unit, and therefore can only be used in the manufacturing process of wafers of that size. Consequently, manufacturers need to prepare multiple types of wafer memory to accommodate various wafer sizes, which increases manufacturing costs. Utility Model Content

[0003] In view of this, the present disclosure provides a carrier device for a wafer memory and a wafer memory having the same, to solve the problem of high manufacturing costs caused by the fact that the same carrier device can only carry wafer cassettes of the same size.

[0004] The carrier device includes a carrier stage, a first positioning structure, and a second positioning structure. The carrier stage is configured to support either a first wafer cassette or a second wafer cassette. The first wafer cassette and the second wafer cassette have different dimensions to store two types of wafers of different sizes, respectively. The first positioning structure is configured to cooperate with the first wafer cassette placed on the carrier stage to restrict movement of the first wafer cassette on the carrier stage. The second positioning structure is configured to cooperate with the second wafer cassette placed on the carrier stage to restrict movement of the first wafer cassette on the carrier stage.

[0005] In one possible implementation, the supporting device includes a first positioning portion and a second positioning portion protruding from the upper surface of the supporting platform, the first positioning portion and the second positioning portion being spaced apart in a first direction. The first positioning portion has a first positioning surface facing the second positioning portion. The second positioning portion has a second positioning surface facing the first positioning portion. The first positioning portion has two third positioning surfaces on opposite sides in a second direction perpendicular to the first direction. The first positioning structure includes the first positioning surface, the second positioning surface, and the two third positioning surfaces.

[0006] In one possible implementation, the supporting device includes a third positioning portion protruding from the upper surface of the supporting platform. The third positioning portion and the second positioning portion are spaced apart in a first direction and located on the side of the second positioning portion facing away from the first positioning portion. The second positioning portion has a fourth positioning surface facing the third positioning portion. The third positioning portion has a fifth positioning surface facing the second positioning portion. Two sixth positioning surfaces are also provided on opposite sides of the first positioning portion in a second direction. The two sixth positioning surfaces are located inside the two third positioning surfaces in the second direction and are closer to the second positioning portion in the first direction than the two third positioning surfaces. The second positioning structure includes the fourth positioning surface, the fifth positioning surface, and the two sixth positioning surfaces.

[0007] As one possible implementation, the two sixth positioning surfaces are coplanar with the two end faces of the second positioning part in the second direction, and coplanar with the two end faces of the two third positioning parts in the second direction.

[0008] In one possible implementation, the supporting device includes a positioning element. The positioning element is assembled onto the supporting platform. The positioning element includes a first positioning part, a second positioning part, and a third positioning part.

[0009] In one possible implementation, the upper surface of the support stage is provided with a receiving recess, and the positioning member includes a base plate portion. A first positioning portion, a second positioning portion, and a third positioning portion are provided on the upper surface of the base plate portion. The receiving recess receives the base plate portion such that the upper surface of the support stage is flush with the upper surface of the base plate portion.

[0010] In one possible implementation, the carrier device includes a first sensor. The first sensor includes a first trigger portion. The first trigger portion protrudes beyond the carrier stage so that it is triggered by pressure from a first wafer cassette placed on the carrier stage. One of the two third positioning surfaces has a first notch. The first trigger portion is partially disposed in the first notch.

[0011] In one possible implementation, the carrier device includes a second sensor. The second sensor includes a second trigger portion. The second trigger portion protrudes beyond the carrier stage so that it is triggered by being pressed down by a second wafer cassette placed on the carrier stage. One of the two sixth positioning surfaces has a second recess, and the second trigger portion is partially disposed in the second recess.

[0012] In one possible implementation, the carrier device includes a first sensor and a second sensor. The first sensor is configured to be triggered by a first wafer cassette placed on the carrier stage but not by a second wafer cassette placed on the carrier stage. The second sensor is configured to be triggered by a second wafer cassette placed on the carrier stage but not by a first wafer cassette placed on the carrier stage.

[0013] As one possible implementation, the carrier device also includes a third sensor. The third sensor is configured to be triggered by both a first wafer cassette placed on the carrier stage and a second wafer cassette placed on the carrier stage.

[0014] In another aspect, this disclosure provides a wafer memory that includes the carrier device described above.

[0015] According to the carrier device provided in this disclosure, the carrier stage can support two sizes of wafer cassettes, and the two positioning structures of the carrier device can respectively position the two sizes of wafer cassettes, making the carrier device suitable for both sizes of wafer cassettes. A wafer memory with this carrier device will be able to store two sizes of wafer cassettes, which helps to reduce manufacturing costs. Attached Figure Description

[0016] It should be understood that the following figures only illustrate certain embodiments of this disclosure and should not be construed as limiting the scope.

[0017] It should be understood that the same or similar reference numerals are used in the accompanying drawings to denote the same or similar elements.

[0018] It should be understood that the accompanying drawings are only schematic, and the dimensions and scales of the elements in the drawings are not necessarily precise.

[0019] Figure 1 This is a schematic diagram of a wafer processing system according to an embodiment of the present disclosure.

[0020] Figure 2 This is a schematic diagram of the structure of a chip memory according to an embodiment of the present disclosure.

[0021] Figure 3 To show Figure 2 A schematic diagram of the structure in which the carrier device carries the first wafer cassette.

[0022] Figure 4 To show Figure 2 A schematic diagram of the structure in which the carrier device supports the second wafer cassette.

[0023] Figure 5 for Figure 2 A schematic diagram of the structure of the load-bearing device.

[0024] Figure 6 for Figure 5 A schematic diagram of the supporting device from another perspective.

[0025] Figure 7 To show Figure 2 A schematic diagram of the structure from another perspective of the carrier device supporting the first wafer cassette.

[0026] Figure 8 for Figure 7 Cross-sectional view at point AA.

[0027] Figure 9 for Figure 7 Cross-sectional view at point BB.

[0028] Figure 10 To show Figure 2 A schematic diagram of the structure from another perspective of the carrier device supporting the second wafer cassette.

[0029] Figure 11 for Figure 10 Cross-sectional view at point CC.

[0030] Figure 12 for Figure 10 Cross-sectional view at point DD.

[0031] Figure 13 This is a schematic diagram of the assembly of the positioning component and the support platform.

[0032] Figure 14 This is a schematic diagram of the structure of the carrier device including the second trigger section.

[0033] Explanation of reference numerals in the attached drawings: 1. Carrying device; 2. First wafer cassette; 3. Second wafer cassette; 21. First crossbeam; 31. Second crossbeam; 10. Carrying stage; 101. Receiving recess; 13. Positioning member; 14. Substrate portion; 20. First positioning portion; 30. Second positioning portion; 40. Third positioning portion; 201. First positioning surface; 202. Third positioning surface; 203. Sixth positioning surface; 2031. Second notch; 301. Second positioning surface; 302. Fourth positioning surface; 401. Fifth positioning surface; 50. First sensor; 60. Second sensor; 601. Second trigger portion; 70. Third sensor; X. First direction; Y. Second direction; 1000. Wafer processing system; 1100. Processing unit; 1200. Transmission unit; 1300. Wafer memory; 1310. First window. Detailed Implementation

[0034] Numerous specific details are set forth below to provide an understanding of the structure, function, and use of the embodiments described and illustrated in the specification and figures. It is to be understood that the embodiments described and illustrated herein are non-limiting examples, and thus it will be appreciated that the particular structural and functional details disclosed herein are representative and exemplary. Variations and changes may be made to these embodiments without departing from the scope of the claims.

[0035] With the development of wafer fabrication technology, the degree of automation in wafer fabrication systems is becoming increasingly higher. For example... Figure 1As shown, the wafer processing system 1000 includes processing units 1100, transfer units 1200, and wafer memory 1300. A processing unit 1100 refers to a cluster of related equipment for one or more processes in a wafer processing technology; that is, a wafer can complete the corresponding processing technology after passing through a corresponding processing unit 1100. In a wafer processing system 1000, one or more processing units 1100 can be set up according to actual needs, and wafers can be transferred between multiple processing units 1100 via the transfer unit 1200. Considering that the processing rates of each processing unit 1100 may be different, wafers from the transfer unit 1200 to the processing unit 1100 and wafers from the processing unit 1100 to the transfer unit 1200 can be stored in the wafer memory 1300.

[0036] In the wafer memory 1300, both wafer storage and transfer are inseparable from the wafer cassette. The main function of the wafer cassette is to simplify the wafer transfer process and minimize the risk of wafer contamination. Therefore, the wafer memory 1300 is equipped with a carrier device for carrying the wafer cassette.

[0037] According to relevant standards, chips come in different sizes, such as 6-inch and 8-inch, and chip cassettes also come in different sizes to accommodate chips of corresponding sizes. A single-size chip cassette can only accommodate chips of that single size. For example, a 6-inch chip cassette can only accommodate 6-inch chips, and an 8-inch chip cassette can only accommodate 8-inch chips. Since 8-inch chips are larger than 6-inch chips, the size of the chip cassette used to accommodate 8-inch chips is usually larger than that used to accommodate 6-inch chips. When the chip memory 1300 needs to process chips of different sizes, it needs to be configured with chip cassettes of different sizes accordingly. However, typically one type of carrier device can only accommodate one size of chip cassette, and different sizes of chip cassettes need to be carried by different types of carrier devices. For example, a 6-inch chip cassette needs to be carried by one type of carrier device, while an 8-inch chip cassette needs to be carried by another type of carrier device. A chip memory 1300 typically has only one type of carrier device, and therefore can only participate in the manufacturing process of chip cassettes of the same size. Therefore, the manufacturer needs to prepare multiple types of chip memories 1300 to accommodate multiple sizes of chips, which increases manufacturing costs.

[0038] Therefore, in order to solve the above-mentioned problems, the present disclosure improves the carrier device of the chip memory 1300. The chip memory 1300 and its carrier device 1 according to the present disclosure will be described below with reference to the accompanying drawings.

[0039] like Figure 2As shown, this disclosure provides a wafer memory 1300. A first window 1310 is provided on the sidewall of the wafer memory 1300 near the transfer unit 1200, through which wafer cassettes can be transferred between the wafer memory 1300 and the transfer unit 1200. A second window 1310 is provided on the sidewall of the wafer memory 1300 near the processing unit 1100, through which wafer cassettes can be transferred between the wafer memory 1300 and the processing unit 1100. Inside the wafer memory 1300, a moving mechanism, such as a robotic arm, is provided to handle the wafer cassettes. To support the wafer cassettes, the wafer memory 1300 may include one or more support devices 1 as needed, and the support devices 1 may be positioned at any location within the wafer memory 1300 as required.

[0040] like Figures 3 to 6 As shown, the carrier device 1 provided in this disclosure includes a carrier stage 10, first positioning structures 201, 202, 301, and second positioning structures 203, 302, 401. The carrier stage 10 is configured to support either a first wafer cassette 2 or a second wafer cassette 3, the first wafer cassette 2 and the second wafer cassette 3 having different sizes to store two types of wafers of different sizes respectively. The first positioning structures 201, 202, 301 are configured to cooperate with the first wafer cassette 2 placed on the carrier stage 10 to restrict movement of the first wafer cassette 2 on the carrier stage 10. The second positioning structures 203, 302, 401 are configured to cooperate with the second wafer cassette 3 placed on the carrier stage 10 to restrict movement of the first wafer cassette 2 on the carrier stage 10.

[0041] The wafer cassette can be placed on the upper surface of the support platform 10 of the support device 1. The upper surface of the support platform 10 provides support for the bottom of the wafer cassette, thereby supporting the wafer cassette. The difference between the first wafer cassette 2 and the second wafer cassette 3 is their size; for example, the size of the first wafer cassette 2 is larger than the size of the second wafer cassette 3. The first wafer cassette 2 is, for example, a wafer cassette for storing 8-inch wafers, and the second wafer cassette 3 is, for example, a wafer cassette for storing 6-inch wafers. The support platform 10 is configured to support either the first wafer cassette 2 or the second wafer cassette 3, meaning that the structure of the support platform 10 can accommodate wafer cassettes of different sizes. Whether the first wafer cassette 2 or the second wafer cassette 3 is placed on the support platform 10, the support platform 10 can provide support for it.

[0042] The positioning structure of the carrier device 1 refers to the structure used to restrict the movement of the wafer cassette on the carrier stage 10 when the wafer cassette is placed on the carrier stage 10. The positioning structure is configured to cooperate with the wafer cassette placed on the carrier stage 10, that is, the positioning structure and the wafer cassette cooperate with each other. Through this cooperative configuration, the positioning structure restricts the movement of the wafer cassette on the carrier stage 10. The carrier device 1 provided in this disclosure includes first positioning structures 201, 202, 301 and second positioning structures 203, 302, 401. Figure 3 As shown, the first wafer cassette 2 is placed on the support stage 10, and the first positioning structures 201, 202, and 301 are configured to cooperate with the first wafer cassette 2 placed on the support stage 10 to restrict the movement of the first wafer cassette 2 on the support stage 10. Figure 4 As shown, the second wafer cassette 3 is placed on the support stage 10, and the second positioning structures 203, 302, and 401 are configured to cooperate with the second wafer cassette 3 placed on the support stage 10 to restrict the movement of the first wafer cassette 2 on the support stage 10.

[0043] According to the carrier device 1 provided in this disclosure, the carrier stage 10 of the carrier device 1 can support two sizes of wafer cassettes, and the two positioning structures of the carrier device 1 can respectively position the two sizes of wafer cassettes, which makes the carrier device 1 applicable to both sizes of wafer cassettes. The wafer memory 1300 with such a carrier device 1 will be able to store two sizes of wafer cassettes, which helps to reduce manufacturing costs.

[0044] The relevant standards specify the detailed construction of wafer cassettes for holding wafers of different sizes. Figure 3 and Figure 4 The wafer cassettes mentioned are of two types: the first wafer cassette 2 and the second wafer cassette 3. Besides the wafer cassettes in relevant standards, the first wafer cassette 2 and the second wafer cassette 3 can also be other types of wafer cassettes, such as customized wafer cassettes. This disclosure does not limit the type of wafer cassette, as long as it meets production requirements.

[0045] Regardless of the type of wafer cassette placed on the support stage 10 of the support device 1, the structure of the support device 1 can be coordinated with the structure of the wafer cassette to achieve the purpose of restricting the movement of the wafer cassette on the support stage 10. Figure 5 and Figure 6A specific structure of the support device 1 provided in this disclosure is shown. For ease of description, two directions parallel to the upper surface of the support platform 10 and perpendicular to each other are respectively referred to as the first direction X and the second direction Y. The support device 1 includes a first positioning part 20 and a second positioning part 30 protruding from the upper surface of the support platform 10, and the first positioning part 20 and the second positioning part 30 are spaced apart in the first direction X. The first positioning part 20 has a first positioning surface 201 facing the second positioning part 30. The second positioning part 30 has a second positioning surface 301 facing the first positioning part 20. The first positioning part 20 has two third positioning surfaces 202 on opposite sides in the second direction Y, which is perpendicular to the first direction X. The first positioning structures 201, 202, and 301 include the first positioning surface 201, the second positioning surface 301, and the two third positioning surfaces 202.

[0046] like Figure 8 As shown, a first crossbeam 21 is provided at the bottom of the first wafer cassette 2. When the first wafer cassette 2 is placed on the support stage 10, the first crossbeam 21 is located between the first positioning part 20 and the second positioning part 30 in the first direction X. At this time, the first positioning surface 201 abuts against the first crossbeam 21 on the X1 direction side in the first direction X, and the second positioning surface 301 abuts against the first crossbeam 21 on the X2 direction side in the first direction X. Therefore, when the first wafer cassette 2 tends to move in the X1 direction, the first positioning surface 201 abuts against the first crossbeam 21, thus preventing the first crossbeam 21 from moving in the X1 direction, thereby preventing the first wafer cassette 2 from moving in the X1 direction; when the first wafer cassette 2 tends to move in the X2 direction, the second positioning surface 301 abuts against the first crossbeam 21, thus preventing the second crossbeam 31 from moving in the X2 direction, thereby preventing the first wafer cassette 2 from moving in the X2 direction. Thus, the first positioning surface 201 and the second positioning surface 301 restrict the translational degree of freedom of the first wafer cassette 2 in the X direction on the support stage 10.

[0047] like Figure 9As shown, the first wafer cassette 2 also includes two sidewalls disposed opposite each other in the Y direction, namely, one sidewall on the Y1 direction side of the first wafer cassette 2 and the other sidewall on the Y2 direction side of the first wafer cassette 2. Correspondingly, two third positioning surfaces 202 are located on the Y1 direction side and the Y2 direction side of the first positioning part 20, respectively. When the first wafer cassette 2 is placed on the support stage 10, the two sidewalls are located on the Y1 direction side and the Y2 direction side of the first positioning part 20, respectively. At this time, the two third positioning surfaces 202 abut against the two sidewalls of the first wafer cassette 2 on the Y1 direction side and the Y2 direction side of the first positioning part 20, respectively. Therefore, when the first wafer cassette 2 tends to move in the Y1 direction, the third positioning surface 202 on the Y2 direction side of the first positioning part 20 abuts against the sidewall on the Y2 direction side of the first wafer cassette 2, preventing the sidewall on the Y2 direction side of the first wafer cassette 2 from moving in the Y1 direction, thus preventing the first wafer cassette 2 from moving in the Y1 direction. Similarly, when the first wafer cassette 2 tends to move in the Y2 direction, the third positioning surface 202 on the Y1 direction side of the first positioning part 20 abuts against the sidewall on the Y1 direction side of the first wafer cassette 2, preventing the sidewall on the Y1 direction side of the first wafer cassette 2 from moving in the Y2 direction, thus preventing the first wafer cassette 2 from moving in the Y2 direction. In this way, the two third positioning surfaces 202 of the first positioning part 20, which are positioned opposite each other in the second direction Y, restrict the translational freedom of the first wafer cassette 2 in the Y direction on the support stage 10.

[0048] In addition, when the first wafer cassette 2 tends to rotate in the plane of the upper surface of the support stage 10, the first positioning surface 201 and the second positioning surface 301 can restrict the rotation of the first crossbeam 21 of the first wafer cassette 2, and the two third positioning surfaces 202 can restrict the rotation of the two side walls of the first wafer cassette 2 in the second direction Y, thereby restricting the rotational freedom of the first wafer cassette 2 in the plane of the upper surface of the support stage 10.

[0049] Through the first positioning surface 201, the second positioning surface 301, and the two third positioning surfaces 202, the first positioning structures 201, 202, and 301 restrict the X-direction translational degree of freedom, the Y-direction translational degree of freedom, and the rotational degree of freedom in the plane of the upper surface of the support stage 10 on the support stage 10, thereby achieving the purpose of restricting the movement of the first wafer cassette 2 on the support stage 10. In addition, the first positioning structures 201, 202, and 301 with this structure have the advantages of simple structure, easy processing, and convenient use.

[0050] In some embodiments, such as Figure 5 and Figure 6As shown, the supporting device 1 includes a third positioning portion 40 protruding from the upper surface of the supporting platform 10. The third positioning portion 40 and the second positioning portion 30 are spaced apart in the first direction X and located on the side of the second positioning portion 30 facing away from the first positioning portion 20. The second positioning portion 30 has a fourth positioning surface 302 facing the third positioning portion 40. The third positioning portion 40 has a fifth positioning surface 401 facing the second positioning portion 30. The first positioning portion 20 is also provided with two sixth positioning surfaces 203 on opposite sides in the second direction Y. The two sixth positioning surfaces 203 are located inside the two third positioning surfaces 202 in the second direction Y, and are closer to the second positioning portion 30 in the first direction X than the two third positioning surfaces 202. The second positioning structures 203, 302, and 401 include the fourth positioning surface 302, the fifth positioning surface 401, and the two sixth positioning surfaces 203.

[0051] When the second wafer cassette 3 is placed on the support stage 10, as Figure 11 As shown, the second crossbeam 31 at the bottom of the second wafer cassette 3 is located between the second positioning part 30 and the third positioning part 40 in the first direction X. The fourth positioning surface 302 and the fifth positioning surface 401 restrict the translational freedom of the second wafer cassette 3 in the X direction on the support stage 10. Figure 12 As shown, the two sidewalls of the second wafer cassette 3 in the second direction Y are located on the Y1 and Y2 directions of the first positioning part 20, respectively. The two sixth positioning surfaces 203 restrict the translational degree of freedom of the second wafer cassette 3 in the Y direction on the support stage 10. The principle of the second positioning structures 203, 302, and 401 on the X-direction translational degree of freedom, Y-direction rotational degree of freedom, and in-plane rotational degree of freedom of the second wafer cassette 3 on the support stage 10 through the fourth positioning surface 302, the fifth positioning surface 401, and the two sixth positioning surfaces 203 is the same as the principle of the first positioning structures 201, 202, and 301 on the X-direction translational degree of freedom, Y-direction rotational degree of freedom, and in-plane rotational degree of freedom of the first wafer cassette 2 on the support stage 10, and will not be repeated here.

[0052] By spacing the third positioning part 40 from the second positioning part 30, and positioning the third positioning part 40 on the side of the second positioning part 30 facing away from the first positioning part 20 in the first direction X (i.e., the X2 direction side), the second positioning part 30 can restrict both the X-direction freedom of the first wafer cassette 2 and the second wafer cassette 3 on the carrier stage 10. The first positioning part 20 has two third positioning surfaces 202 and two sixth positioning surfaces 203 on opposite sides in the second direction Y. The two sixth positioning surfaces 203 are located inside the two third positioning surfaces 202 in the second direction Y and are closer to the second positioning part 30 in the first direction X than the two third positioning surfaces 202. This allows the first positioning part 20 to restrict both the Y-direction freedom of the first wafer cassette 2 and the second wafer cassette 3 on the carrier stage 10. The first positioning structure 201, 202, 301 and the second positioning structure 203, 302, 401 share the first positioning part 20 and the second positioning part 30, which reduces the area of ​​the carrier device 1 and thus achieves the effect of reducing the volume of the chip memory 1300.

[0053] In some embodiments, such as Figure 5 and Figure 6 As shown, the two sixth positioning surfaces 203 are coplanar with the two end faces of the second positioning part 30 in the second direction Y, and coplanar with the two end faces of the third positioning part 40 in the second direction Y. When the second wafer cassette 3 is placed on the support stage 10, the two sixth positioning surfaces 203 abut against the two side walls of the second wafer cassette 3 in the second direction Y, thereby positioning the second wafer cassette 3 on the support stage 10. Since the two end faces of the second positioning part 30 in the second direction Y are coplanar with the two sixth positioning surfaces 203, and coplanar with the two end faces of the third positioning part 40 in the second direction Y, the two end faces of the second positioning part 30 and the two end faces of the third positioning part 40 in the second direction Y will also abut against the two side walls of the second wafer cassette 3 in the second direction Y, thereby imposing more constraints on the degree of freedom of the second wafer cassette 3 in the second direction Y on the support stage 10, and enhancing the stability of the second wafer cassette 3 when placed on the support stage 10.

[0054] In some embodiments, such as Figure 13As shown, the carrier device 1 includes a positioning element 13. The positioning element 13 is mounted on the carrier platform 10. The positioning element 13 includes a first positioning part 20, a second positioning part 30, and a third positioning part 40. Since the first positioning part 20, the second positioning part 30, and the third positioning part 40 are used in conjunction with the first wafer cassette 2 and the second wafer cassette 3 to position the first wafer cassette 2 and the second wafer cassette 3, the processing accuracy requirements are relatively high. The carrier platform 10, on the other hand, is used to provide support for the first wafer cassette 2 and the second wafer cassette 3, and therefore the processing accuracy requirements are lower. By mounting the positioning element 13 on the carrier platform 10, the processing accuracy requirements of the carrier device 1 can be reduced, and production efficiency can be improved. The positioning element 13 is connected to the carrier platform 10, for example, by screws. Furthermore, for example, when the positioning element 13 is damaged, since the positioning element 13 is mounted on the carrier platform 10, it is easy to replace the positioning element 13, thereby improving production efficiency.

[0055] In some embodiments, such as Figure 13 As shown, the upper surface of the support platform 10 is provided with a receiving recess 101, and the positioning member 13 includes a base plate portion 14. A first positioning portion 20, a second positioning portion 30, and a third positioning portion 40 are provided on the upper surface of the base plate portion 14. The receiving recess 101 receives the base plate portion 14 such that the upper surface of the support platform 10 is flush with the upper surface of the base plate portion 14. Figure 13 As shown, the upper surface of the support platform 10 is recessed downwards to form a receiving recess 101 to accommodate the positioning member 13. When the positioning member 13 is assembled on the support platform 10, the upper surface of the substrate portion 14 is flush with the upper surface of the support platform 10, so that when the first wafer cassette 2 and the second wafer cassette 3 are placed on the support platform 10, the substrate portion 14 and the upper surface and the upper surface of the support platform 10 can simultaneously provide support for the bottom of the first wafer cassette 2 and the second wafer cassette 3, thereby enhancing the stability of the support device 1 when supporting the first wafer cassette 2 and the second wafer cassette 3.

[0056] In some embodiments, such as Figure 5 and Figure 6As shown, the carrier device 1 includes a first sensor 50 and a second sensor 60. The first sensor 50 is configured to be triggered by a first wafer cassette 2 placed on the carrier stage 10 but not by a second wafer cassette 3 placed on the carrier stage 10. The second sensor 60 is configured to be triggered by a second wafer cassette 3 placed on the carrier stage 10 but not by a first wafer cassette 2 placed on the carrier stage 10. When the first wafer cassette 2 is placed on the carrier stage 10, the first sensor 50 will be triggered but the second sensor 60 will not be triggered. When the second wafer cassette 3 is placed on the carrier stage 10, the second sensor 60 will be triggered but the first sensor 50 will not be triggered. Therefore, the carrier device 1 can accurately sense whether the wafer cassette placed on the carrier stage 10 is the first wafer cassette 2 or the second wafer cassette 3. The sensor triggering state of the carrier device 1 can be received, for example, by a host computer or other device, for subsequent processing of the wafer cassettes on the carrier stage 10, thereby eliminating the need for manual determination of the wafer cassette type on the carrier stage 10 and improving production efficiency.

[0057] In some embodiments, such as Figure 5 and Figure 6 As shown, the carrier device 1 also includes a third sensor 70. The third sensor 70 is configured to be triggered by both the first wafer cassette 2 and the second wafer cassette 3 placed on the carrier stage 10. When the position of the first wafer cassette 2 or the second wafer cassette 3 deviates on the carrier, the sensing status of only the first sensor 50 or the second sensor 60 may not be sufficient to detect it. By configuring the third sensor 70 to be triggered by both the first wafer cassette 2 and the second wafer cassette 3, the first sensor 50 and the third sensor 70 can be triggered when the first wafer cassette 2 is placed on the carrier stage 10, and the second sensor 60 and the third sensor 70 can be triggered when the second wafer cassette 3 is placed on the carrier stage 10. That is, both sensors can be triggered when the first wafer cassette 2 and the second wafer cassette 3 are placed on the carrier stage 10. When one of the two sensors triggered by the first wafer cassette 2 or the second wafer cassette 3 is not triggered, it can be determined that the position of the first wafer cassette 2 or the second wafer cassette 3 has deviated, thus allowing for timely correction of the position of the first wafer cassette 2 or the second wafer cassette 3 and avoiding adverse effects on subsequent processing. Furthermore, the first wafer cassette 2 and the second wafer cassette 3 share the third sensor 70, which can save the number of sensors to be set in the carrier device 1, reduce the area of ​​the carrier device 1, and thus reduce the volume of the wafer memory 1300.

[0058] In some embodiments, the second sensor 60 includes a second trigger portion 601. The second trigger portion 601 protrudes from the upper surface of the support stage 10 so as to be triggered by the pressure of the second wafer cassette 3 placed on the support stage 10. One of the two sixth positioning surfaces 203 is provided with a second recess 2031, and the second trigger portion 601 is partially disposed in the second recess 2031. Figure 14 As shown, the second trigger part 601 is a movable component that can be displaced under pressure, thereby triggering the second sensor 60. A second notch 2031 is provided on the sixth positioning surface 203 on the Y2 direction side, and the second trigger part 601 is also provided on the Y2 direction side of the sixth positioning surface 203, partially placed within the second notch 2031. When the second wafer cassette 3 is placed on the support stage 10, the sidewall on the Y2 direction side of the second wafer cassette 3 abuts against the sixth positioning surface 203 at that location, pressing down the second trigger part 601 and triggering the second sensor 60. However, when the second wafer cassette 3 is placed on the support stage 10, since the sidewall on the Y2 direction side of the second wafer cassette 3 does not abut against the sixth positioning surface 203 at that location, the second trigger part 601 is not pressed down, and the second sensor 60 is not triggered. By partially placing the second trigger part 601 in the second recess 2031, not only can the effect of the second sensor 60 being triggered only by the second chip box 3 and not by the first chip box 2 be achieved, but the position of the sensor can also be made closer to the first positioning member 13, thereby reducing the area of ​​the support device 1.

[0059] In some embodiments, the first sensor 50 includes a first trigger portion. The first trigger portion protrudes from the upper surface of the support stage 10 to be triggered by the first wafer cassette 2 placed on the support stage 10. One of the two third positioning surfaces 202 is provided with a first recess, and the first trigger portion is partially placed in the first recess. The principle that the first trigger portion can only be pressed by the first wafer cassette 2 and not by the second wafer cassette 3 is the same as above, and will not be repeated here. By partially placing the first trigger portion in the first recess, not only can the effect of the first sensor 50 being triggered only by the first wafer cassette 2 and not by the second wafer cassette 3 be achieved, but the position of the sensor can also be made closer to the second positioning member 13, thereby reducing the area of ​​the support device 1.

[0060] In some embodiments, the first sensor 50 includes a first trigger portion, and the second sensor 60 includes a second trigger portion 601. The first trigger portion protrudes from the upper surface of the support stage 10 to be triggered by the first wafer cassette 2 placed on the support stage 10. One of the two third positioning surfaces 202 has a first recess, and the first trigger portion is partially placed in the first recess. The second trigger portion 601 protrudes from the upper surface of the support stage 10 to be triggered by the second wafer cassette 3 placed on the support stage 10. One of the two sixth positioning surfaces 203 has a second recess 2031, and the second trigger portion is partially placed in the second recess 2031. Thus, the positions of the first sensor 50 and the second sensor 60 are both close to the first positioning member 13, thereby reducing the area of ​​the support device 1.

[0061] The first sensor 50, the second sensor 60, and the third sensor 70 can be of the same type or different types. They can be contact sensors or non-contact sensors. By way of example only, they can be implemented as microswitches.

[0062] It should be noted that the elements described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0063] It should be understood that multiple components and / or parts can be provided by a single integrated component or part. Alternatively, a single integrated component or part can be divided into multiple separate components and / or parts. The use of the public designation "a" or "an" to describe a component or part is not intended to exclude other components or parts.

[0064] It should be understood that although terms such as “first” or “second” may be used in this disclosure to describe various elements, these elements are not defined by these terms, which are only used to distinguish one element from another.

[0065] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0066] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A carrier device for a chip memory, characterized in that, The supporting device includes: A support platform, the support platform being configured to support either a first wafer cassette or a second wafer cassette, the first wafer cassette and the second wafer cassette having different sizes to store two types of wafers of different sizes respectively; A first positioning structure, configured to cooperate with a first wafer cassette placed on the carrier stage to restrict movement of the first wafer cassette on the carrier stage; and A second positioning structure is configured to cooperate with the second wafer cassette placed on the carrier platform to restrict movement of the first wafer cassette on the carrier platform.

2. The bearing device according to claim 1, characterized in that, The supporting device includes a first positioning part and a second positioning part protruding from the upper surface of the supporting platform. The first positioning part and the second positioning part are spaced apart in a first direction. The first positioning part has a first positioning surface facing the second positioning part, and the second positioning part has a second positioning surface facing the first positioning part. The first positioning part is provided with two third positioning surfaces on opposite sides in a second direction perpendicular to the first direction. The first positioning structure includes the first positioning surface, the second positioning surface and the two third positioning surfaces.

3. The bearing device according to claim 2, characterized in that, The supporting device includes a third positioning part protruding from the upper surface of the supporting platform. The third positioning part and the second positioning part are spaced apart in the first direction and located on the side of the second positioning part away from the first positioning part. The second positioning part has a fourth positioning surface facing the third positioning part and a fifth positioning surface facing the second positioning part. The first positioning part is also provided with two sixth positioning surfaces on opposite sides in the second direction. The two sixth positioning surfaces are located inside the two third positioning surfaces in the second direction and are closer to the second positioning part in the first direction than the two third positioning surfaces. The positioning structure includes the fourth positioning surface, the fifth positioning surface, and the two sixth positioning surfaces.

4. The bearing device according to claim 3, characterized in that, The two sixth positioning surfaces are coplanar with the two end faces of the second positioning part in the second direction, and are also coplanar with the two end faces of the two third positioning parts in the second direction.

5. The bearing device according to claim 3, characterized in that, The supporting device includes a positioning component, which is assembled on the supporting platform. The positioning component includes a first positioning part, a second positioning part, and a third positioning part.

6. The bearing device according to claim 5, characterized in that, The upper surface of the support platform is provided with a receiving recess. The positioning member includes a base plate portion. The first positioning portion, the second positioning portion, and the third positioning portion are disposed on the upper surface of the base plate portion. The receiving recess receives the base plate portion so that the upper surface of the support platform is flush with the upper surface of the base plate portion.

7. The bearing device according to claim 3, characterized in that, The carrier device includes a first sensor, the first sensor includes a first trigger part, the first trigger part protrudes beyond the carrier stage so that it is triggered by being pressed down by a first wafer cassette placed on the carrier stage, and one of the two third positioning surfaces is provided with a first notch, the first trigger part being partially placed in the first notch; and / or The carrier device includes a second sensor, which includes a second trigger portion that protrudes beyond the carrier stage to be triggered by a second wafer cassette placed on the carrier stage. One of the two sixth positioning surfaces has a second recess, and the second trigger portion is partially placed in the second recess.

8. The bearing device according to claim 1, characterized in that, The carrier device includes a first sensor and a second sensor, the first sensor being configured to be triggered by a first wafer cassette placed on the carrier stage but not by a second wafer cassette placed on the carrier stage, and the second sensor being configured to be triggered by a second wafer cassette placed on the carrier stage but not by a first wafer cassette placed on the carrier stage.

9. The bearing device according to claim 8, characterized in that, The carrier device further includes a third sensor configured to be triggered by both the first wafer cassette placed on the carrier stage and the second wafer cassette placed on the carrier stage.

10. A chip memory, characterized in that, The chip memory includes a carrier device according to any one of claims 1 to 9.

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