Load ground end compensation circuit, digital sampler and testing machine

Abstract

The utility model relates to a load ground end compensation circuit, a digital sampler and a testing machine, and the load ground end compensation circuit comprises a near-end buffer circuit which is connected with a load ground end of a tested device, receives a signal of the load ground end, and outputs a buffer signal; and the ground pressure difference compensation circuit is connected with the near-end buffer circuit and the tested device, and the ground pressure difference compensation circuit performs difference on the single-end signal and the buffer signal output by the tested device and then outputs the difference, so that ground pressure difference compensation is realized, and meanwhile, the anti-interference capability of the ground pressure difference compensation is also improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a load ground compensation circuit, a digital sampler, and a testing machine. Background Technology

[0002] One type of device under test (DUT) in a digital test chamber (DBT) is a hybrid chip, such as an audio ADC or DAC chip. The digital sampler (DGT) on the test chamber acts as a receiving device, acquiring analog signal waveforms such as sinusoidal signals emitted by the DUT. Precision DBTs require the DGT to have sufficient performance specifications; otherwise, the test results will be limited by the sampler. In a common-ground system, due to the impedance of the signal ground AGND and the presence of ground current, a ground voltage difference inevitably exists between the DGT and the DUT. To eliminate the influence of this ground voltage difference on precise signal measurements referenced to ground, a load ground terminal DUTGND needs to be led out from the DUT nearby, ensuring that there is no shared current path between the load ground terminal DUTGND and the signal ground AGND. Furthermore, the load ground terminal DUTGND is introduced into the signal conditioning circuit of the DGT to compensate for the ground voltage difference and ensure the measurement accuracy and dynamic performance of the test chamber. However, this compensation method has weak anti-interference capability; therefore, improving the anti-interference capability of ground voltage difference compensation is a problem that urgently needs to be solved. Utility Model Content

[0003] Therefore, it is necessary to provide a load grounding compensation circuit, a digital sampler, and a tester that can improve the anti-interference capability of ground pressure differential compensation to address the above problems.

[0004] The first aspect of this application provides a load ground compensation circuit, comprising:

[0005] The near-end buffer circuit is connected to the load ground terminal of the device under test, receives the signal from the load ground terminal, and outputs a buffer signal.

[0006] The ground pressure difference compensation circuit is connected to the near-end buffer circuit and the device under test. The ground pressure difference compensation circuit outputs the difference between the single-ended signal output by the device under test and the buffer signal.

[0007] In one embodiment, the ground pressure differential compensation circuit includes:

[0008] A filtering circuit, connected to the near-end buffer circuit, filters the received buffer signal;

[0009] The operational circuit is connected to the filter circuit and the bias signal source. The operational circuit applies a gain to the differential signal output by the device under test and performs differential-to-single-ended conversion. Then, it applies a bias according to the bias signal output by the bias signal source. Alternatively, the operational circuit applies a gain to the single-ended signal output by the device under test and the filtered buffer signal, then performs differential conversion. Then, it applies a bias according to the bias signal output by the bias signal source.

[0010] In one embodiment, the filtering circuit is also connected to the device under test (DUT) and transmits the signal output by the DUT to the computing circuit.

[0011] In one embodiment, the filtering circuit includes a first gating filter unit and a second gating filter unit, wherein the first gating filter unit is connected to the near-end buffer circuit, the operational circuit and the device under test, and the second gating filter unit is connected to the near-end buffer circuit, the operational circuit and the device under test;

[0012] When the operational circuit performs differential signal gain processing, the first gating filter unit sends the first signal output by the device under test to the operational circuit, and the second gating filter unit sends the second signal output by the device under test to the operational circuit.

[0013] When the operational circuit performs single-ended signal gain processing, the first gating filter unit sends the first signal output by the device under test to the operational circuit, and the second gating filter unit filters the received buffer signal and outputs it to the operational circuit; or, the first gating filter unit filters the received buffer signal and outputs it to the operational circuit, and the second gating filter unit sends the second signal output by the device under test to the operational circuit.

[0014] In one embodiment, the first gating filter unit includes a resistor R17, a capacitor C5, a switch S3, and a switch S5. The first end of the resistor R17 is connected to the near-end buffer circuit, the second end of the resistor R17 is connected to the first end of the capacitor C5 and the first end of the switch S5, the second end of the capacitor C5 is connected to signal ground, the second end of the switch S5 is connected to the first end of the switch S3 and the operational circuit, and the second end of the switch S3 is connected to the device under test.

[0015] In one embodiment, the second gating filter unit includes a resistor R18, a capacitor C6, a switch S4, and a switch S6. The first end of the resistor R18 is connected to the near-end buffer circuit, the second end of the resistor R18 is connected to the first end of the capacitor C6 and the first end of the switch S6, the second end of the capacitor C6 is connected to signal ground, the second end of the switch S6 is connected to the first end of the switch S4 and the operational circuit, and the second end of the switch S4 is connected to the device under test.

[0016] In one embodiment, the operational circuit includes operational amplifier U7, operational amplifier U8, operational amplifier U9, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, resistor R25, resistor R26, resistor R27, resistor R28 and resistor R29.

[0017] The first end of resistor R21 is connected to the filter circuit and connected to signal ground through resistor R19. The second end of resistor R21 is connected to the non-inverting input of operational amplifier U7. The first end of resistor R22 is connected to the filter circuit and connected to signal ground through resistor R20. The second end of resistor R22 is connected to the non-inverting input of operational amplifier U8. The inverting input of operational amplifier U7 is connected to the first ends of resistor R23 and R24. The second end of resistor R23 is connected to the first end of resistor R25 and the inverting input of operational amplifier U8. The second end of resistor R24 ​​is connected to the output of operational amplifier U7. The second end of resistor R25 is connected to the output of operational amplifier U8.

[0018] The first end of resistor R26 is connected to the output of operational amplifier U7, the second end of resistor R26 is connected to the inverting input of operational amplifier U9 and the first end of resistor R28, the second end of resistor R28 is connected to the output of operational amplifier U9 and the analog-to-digital converter; the first end of resistor R27 is connected to the output of operational amplifier U8, the second end of resistor R27 is connected to the non-inverting input of operational amplifier U9 and the first end of resistor R29, and the second end of resistor R29 is connected to a bias signal source.

[0019] In one embodiment, the near-end buffer circuit includes an operational amplifier U10, resistors R30 and R31, capacitors C7 and C8. The first end of resistor R30 is connected to the load ground. The second end of resistor R30 is connected to the first end of resistor R31 and the first end of capacitor C7. The second end of resistor R31 is connected to the non-inverting input of operational amplifier U10 and the first end of capacitor C8. The second end of capacitor C7 is connected to the inverting input and output of operational amplifier U10. The second end of capacitor C8 is connected to signal ground. The output of operational amplifier U10 is connected to the ground voltage compensation circuit.

[0020] A second aspect of this application provides a digital sampler, including an FPGA, an analog-to-digital converter, and the aforementioned load-to-ground compensation circuit, wherein the FPGA is connected to the load-to-ground compensation circuit via the analog-to-digital converter.

[0021] A third aspect of this application provides a test machine including the aforementioned digital sampler.

[0022] The aforementioned load ground compensation circuit, digital sampler, and tester include a near-end buffer circuit and a ground voltage difference compensation circuit. The near-end buffer circuit receives the signal from the load ground and outputs a buffered signal. The ground voltage difference compensation circuit connects the near-end buffer circuit and the device under test (DUT). The ground voltage difference compensation circuit outputs the difference between the single-ended signal and the buffered signal from the DUT, thus achieving ground voltage difference compensation while suppressing noise interference introduced by the traces, thereby improving the anti-interference capability of ground voltage difference compensation. Attached Figure Description

[0023] Figure 1 This is a block diagram of the load ground compensation circuit in one embodiment;

[0024] Figure 2 This is a schematic diagram of the load ground compensation circuit in one embodiment. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0027] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0028] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof.

[0029] In one embodiment, such as Figure 1 As shown, a load ground compensation circuit is provided, including a near-end buffer circuit 110 and a ground voltage difference compensation circuit 120. The near-end buffer circuit 110 is connected to the load ground terminal of the device under test (DUT), receives the signal from the load ground terminal, and outputs a buffered signal. The ground voltage difference compensation circuit 120 is connected to the near-end buffer circuit 110 and the DUT, and outputs the difference between the single-ended signal output by the DUT and the buffered signal.

[0030] The device under test (DUT) can be a semiconductor chip or other similar device. For example... Figure 2 As shown, the device under test (DUT) can be mounted on a load board (DUT Board). The load ground terminal (DUTGND) of the DUT is led out from the load board and the signal is output to the near-end buffer circuit 110. The near-end buffer circuit 110 buffers and filters the incoming signal (e.g., low-pass filtering) to suppress interference from the load ground terminal (DUTGND) and outputs a buffered signal (DUTGND_BUFF) to the ground voltage difference compensation circuit 120. The ground voltage difference compensation circuit 120 can also low-pass filter the received buffered signal (DUTGND_BUFF) to suppress noise and other interference introduced by the wiring between the near-end buffer circuit 110 and the ground voltage difference compensation circuit 120. Then, the difference between the filtered buffered signal and the single-ended signal output by the DUT is calculated.

[0031] The specific structure of the near-end buffer circuit 110 is not unique; in one embodiment, such as... Figure 2As shown, the near-end buffer circuit 110 includes an operational amplifier U10, resistors R30 and R31, capacitors C7 and C8. The first end of resistor R30 is connected to the load ground DUTGND. The second end of resistor R30 is connected to the first end of resistor R31 and the first end of capacitor C7. The second end of resistor R31 is connected to the non-inverting input of operational amplifier U10 and the first end of capacitor C8. The second end of capacitor C7 is connected to the inverting input and output of operational amplifier U10. The second end of capacitor C8 is connected to signal ground AGND. The output of operational amplifier U10 is connected to the ground voltage difference compensation circuit 120.

[0032] In the near-end buffer circuit 110, resistors R30 and R31, and capacitors C7 and C8 provide the circuit with two poles, functioning as a low-pass filter to suppress interference above 1kHz on the load ground terminal DUTGND. Operational amplifier U10 provides tens of milliamps of drive capability for the buffer output. The near-end buffer circuit 110 can be placed at the edge of the digital sampler board, specifically within 20cm of the edge. Only one near-end buffer circuit 110 is needed per digital sampler board. The operational amplifier U10, resistors R30 and R31, and capacitors C7 and C8 form a second-order active filter, preventing the spread and deterioration of DUTGND interference within the board.

[0033] In one embodiment, the ground pressure differential compensation circuit 120 includes a filter circuit 122 and an arithmetic circuit 124. The filter circuit 122 is connected to the near-end buffer circuit 110 and filters the received buffered signal. The arithmetic circuit 124 is connected to the filter circuit 122 and the bias signal source DGT offset source. The arithmetic circuit 124 applies gain to the differential signal output by the device under test (DUT) and performs differential-to-single-ended conversion. Then, it applies a bias according to the bias signal output by the bias signal source DGT offset source to output a single-ended signal DGT. Alternatively, the arithmetic circuit 124 applies gain to both the single-ended signal output by the DUT and the filtered buffered signal, performs differential conversion, and then applies a bias according to the bias signal output by the bias signal source DGT offset source to output a single-ended signal DGT. The arithmetic circuit 124 can be directly or indirectly (e.g., through the filter circuit 122) connected to the DUT to receive the signal output by the DUT. The operational circuit 124 performs gain processing on differential signals, as well as on single-ended signals and filtered buffered signals, which can be either amplification or attenuation.

[0034] Furthermore, the filter circuit 122 is also connected to the device under test (DUT) and transmits the signal output by the DUT to the arithmetic circuit 124. Depending on the actual testing requirements, the filter circuit 122 can transmit the differential signal output by the DUT to the arithmetic circuit 124; alternatively, the filter circuit 122 can transmit one of the differential signals output by the DUT as a single-ended signal to the arithmetic circuit 124, or filter the buffer signal DUTGND_BUFF before transmitting it to the arithmetic circuit 124.

[0035] In one embodiment, such as Figure 2 As shown, the filter circuit 122 includes a first gating filter unit 1222 and a second gating filter unit 1224. The first gating filter unit 1222 is connected to the near-end buffer circuit 110, the operation circuit 124 and the device under test (DUT), and the second gating filter unit 1224 is connected to the near-end buffer circuit 110, the operation circuit 124 and the DUT. When the operational circuit 124 performs differential signal gain processing, the first gating filter unit 1222 sends the first signal DUT_P output by the device under test (DUT) to the operational circuit 124, and the second gating filter unit 1224 sends the second signal DUT_N output by the DUT to the operational circuit 124. When the operational circuit 124 performs single-ended signal gain processing, the first gating filter unit 1222 sends the first signal DUT_P output by the DUT to the operational circuit 124, and the second gating filter unit 1224 filters the received buffer signal DUTGND_BUFF and outputs it to the operational circuit 124. Alternatively, the first gating filter unit 1222 filters the received buffer signal DUTGND_BUFF and outputs it to the operational circuit 124, and the second gating filter unit 1224 sends the second signal DUT_N output by the DUT to the operational circuit 124.

[0036] The first gating and filtering unit 1222 may include a resistor R17, a capacitor C5, a switch S3, and a switch S5. The first end of the resistor R17 is connected to the near-end buffer circuit 110, specifically to the output of the operational amplifier U10. The second end of the resistor R17 is connected to the first end of the capacitor C5 and the first end of the switch S5. The second end of the capacitor C5 is connected to the signal ground AGND. The second end of the switch S5 is connected to the first end of the switch S3 and the operational circuit 124. The second end of the switch S3 is connected to the device under test (DUT). When switch S3 is closed and switch S5 is open, the first gating and filtering unit 1222 sends the first signal DUT_P to the operational circuit 124. When switch S5 is closed and switch S3 is open, the first gating and filtering unit 1222 filters the buffer signal DUTGND_BUFF and outputs it to the operational circuit 124.

[0037] The second gating and filtering unit 1224 may include a resistor R18, a capacitor C6, a switch S4, and a switch S5. The first end of resistor R18 is connected to the near-end buffer circuit 110, specifically to the output of operational amplifier U10. The second end of resistor R18 is connected to the first end of capacitor C6 and the first end of switch S6. The second end of capacitor C6 is connected to signal ground AGND. The second end of switch S6 is connected to the first end of switch S4 and the operational circuit 124. The second end of switch S4 is connected to the device under test (DUT). When switch S4 is closed and switch S6 is open, the second gating and filtering unit 1224 sends the second signal DUT_N to the operational circuit 124. When switch S6 is closed and switch S4 is open, the second gating and filtering unit 1224 filters the buffer signal DUTGND_BUFF and outputs it to the operational circuit 124.

[0038] The specific structure of the operational circuit 124 is not unique; please refer to [reference needed]. Figure 2 The operational circuit 124 may include operational amplifiers U7, U8, and U9, resistors R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, and R29.

[0039] The first end of resistor R21 is connected to filter circuit 122, specifically to the second end of switch S5 and the first end of switch S3 in the first gating filter unit 1222. The first end of resistor R21 is also connected to signal ground AGND through resistor R19. The second end of resistor R21 is connected to the non-inverting input of operational amplifier U7. The first end of resistor R22 is connected to filter circuit 122, specifically to the second end of switch S6 and the first end of switch S4 in the second gating filter unit 1224. The first end of resistor R22 is also connected to signal ground AGND through resistor R20. The second end of resistor R22 is connected to the non-inverting input of operational amplifier U8. The inverting input of operational amplifier U7 is connected to the first end of resistor R23 and the first end of resistor R24. The second end of resistor R23 is connected to the first end of resistor R25 and the inverting input of operational amplifier U8. The second end of resistor R24 ​​is connected to the output of operational amplifier U7. The second end of resistor R25 is connected to the output of operational amplifier U8.

[0040] The first end of resistor R26 is connected to the output of operational amplifier U7. The second end of resistor R26 is connected to the inverting input of operational amplifier U9 and the first end of resistor R28. The second end of resistor R28 is connected to the output of operational amplifier U9 and the analog-to-digital converter (DGT). The first end of resistor R27 is connected to the output of operational amplifier U8. The second end of resistor R27 is connected to the non-inverting input of operational amplifier U9 and the first end of resistor R29. The second end of resistor R29 is connected to the bias signal source (DGToffset source).

[0041] Specifically, the first signal DUT_P and the second signal DUT_N output by the device under test (DUT), as well as the offset signal offset output by the offset source DGT, serve as the inputs to the ground voltage difference compensation circuit 120. The ground voltage difference compensation circuit 120 outputs a single-ended signal DGT to the analog-to-digital converter (ADC). The DUT outputs a differential signal consisting of the first signal DUT_P and the second signal DUT_N, or a single-ended signal using only one of them. Switches S3, S4, S5, and S6 determine the input configuration of the circuit. When switches S3 and S4 are closed and switches S5 and S6 are open, the differential signal of the device under test (DUT) is input. This indicates that when the DUT inputs a differential signal, switches S5 and S6 are both open to block the buffer signal DUTGND_BUFF from entering the operational circuit 124. When switches S3 and S6 are closed and switches S4 and S5 are open, the first signal DUT_P (single-ended) and the signal of the reference load ground DUTGND are input. When switches S4 and S5 are closed and switches S3 and S6 are open, the second signal DUT_N (single-ended) and the signal of the load ground DUTGND are input. Therefore, this differential voltage compensation circuit 120 is compatible with both differential and single-ended inputs. Resistors R19 and R20 provide a defined input impedance for this circuit. To balance the differential and single-ended input impedances, R19 = R20 is designed to be equal to R20. Resistors R21 and R22 provide transient current protection for the downstream circuit. Resistors R17 and R18, and capacitors C5 and C6 respectively constitute a first-order low-pass filter (far-end filtering of the load ground DUTGND), which suppresses noise and other interference coupled on the buffer signal DUTGND_BUFF trace. Resistors R17 and C5 are placed within 20cm of operational amplifier U7, and resistors R18 and C6 are placed within 20cm of operational amplifier U8.

[0042] Operational amplifiers U7, U8, and U9, along with resistors R23 and R29, constitute an instrumentation amplifier circuit that performs gain-before-difference processing. Operational amplifier U7 provides gain for the buffer signal DUTGND_BUFF and the first signal DUT_P, while operational amplifier U8 provides gain for the buffer signal DUTGND_BUFF and the second signal DUT_N. Operational amplifier U9 first sums the bias signal offset and the buffer signal DUTGND_BUFF, then subtracts the first signal DUT_P, outputting the compensated single-ended signal DGT; or operational amplifier U9 first sums the bias signal offset and the second signal DUT_N, then subtracts the buffer signal DUTGND_BUFF, outputting the compensated single-ended signal DGT. By controlling the input of the first signal, the second signal, or the filtered buffer signal DUTGND_BUFF from the device under test (DUT), the instrumentation amplifier circuit calculates the difference between the inverting and non-inverting inputs, accommodating both differential and single-ended signal formats. To ensure balanced gain at the two inputs of the digital sampler, R24 = R25, R26 = R27, and R28 = R29 are designed as follows: The input-output relationship of the circuit is shown in Table 1.

[0043] Table 1

[0044]

[0045]

[0046] As can be seen from the above expression, the single-ended signal DGT input to the digital sampler offsets the voltage difference V between the load ground DUTGND and the digital ground AGND. DUTGND This achieves a compensatory function. Through V DUTP -V DUTGND To achieve compensation, V DUTP and V DUTGND Synchronous gain This does not affect compensation. It should be noted that k can be greater than or equal to 1 or less than 1, allowing for the design of appropriate resistor values ​​to provide gain amplification or gain reduction. The bias signal offset of the bias signal source provides a DC component to the input of the digital sampler to cancel the DC signal output by the device under test (DUT) in the test application.

[0047] The load ground compensation circuit provided in this application includes a near-end buffer circuit 110 that receives the load ground signal and outputs a buffered signal. A filter circuit 122 filters the received buffered signal and uses it to calculate the difference between the single-ended signal output by the operational circuit 124 and the device under test (DUT). This effectively suppresses noise and other interference introduced by the traces between the near-end buffer circuit 110 and the filter circuit 122. Furthermore, the compensation circuit for the load ground DUTGND is optimized to reduce the negative impacts of NSD, THD, and SFDR on large-size multi-channel DGT boards. The operational circuit 124 is also improved, controlling the input of the DUT to either in-phase or inverted output via a switch. The difference between the in-phase and inverted inputs is calculated by an instrumentation amplifier circuit, making it compatible with both single-ended and differential signal formats.

[0048] In one embodiment, such as Figure 2 As shown, a digital sampler is also provided, including an FPGA, an analog-to-digital converter (DGT) ADC, and the aforementioned load ground compensation circuit. The FPGA is connected to the load ground compensation circuit via the DGT ADC. The single-ended signal DGT output from the arithmetic circuit 124 is converted from analog to digital by the DGT ADC, and a digital signal is output to the FPGA for parameter analysis of the device under test (DUT). Furthermore, the digital sampler may also include a bias signal source (DGT offset source).

[0049] In one embodiment, a test machine is also provided, including the digital sampler described above, and the test machine may be a digital test machine.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A load ground compensation circuit, characterized in that, include: The near-end buffer circuit is connected to the load ground terminal of the device under test, receives the signal from the load ground terminal, and outputs a buffer signal. The ground pressure difference compensation circuit is connected to the near-end buffer circuit and the device under test. The ground pressure difference compensation circuit outputs the difference between the single-ended signal output by the device under test and the buffer signal.

2. The circuit according to claim 1, characterized in that, The ground pressure differential compensation circuit includes: A filtering circuit, connected to the near-end buffer circuit, filters the received buffer signal; The operational circuit is connected to the filter circuit and the bias signal source. The operational circuit applies a gain to the differential signal output by the device under test and performs differential-to-single-ended conversion. Then, it applies a bias according to the bias signal output by the bias signal source. Alternatively, the operational circuit applies a gain to the single-ended signal output by the device under test and the filtered buffer signal, then performs differential conversion. Then, it applies a bias according to the bias signal output by the bias signal source.

3. The circuit according to claim 2, characterized in that, The filtering circuit is also connected to the device under test (DUT) and transmits the signal output by the DUT to the computing circuit.

4. The circuit according to claim 3, characterized in that, The filtering circuit includes a first gating filtering unit and a second gating filtering unit. The first gating filtering unit is connected to the near-end buffer circuit, the operational circuit, and the device under test. The second gating filtering unit is connected to the near-end buffer circuit, the operational circuit, and the device under test. When the operational circuit performs differential signal gain processing, the first gating filter unit sends the first signal output by the device under test to the operational circuit, and the second gating filter unit sends the second signal output by the device under test to the operational circuit. When the operational circuit performs single-ended signal gain processing, the first gating filter unit sends the first signal output by the device under test to the operational circuit, and the second gating filter unit filters the received buffer signal and outputs it to the operational circuit; or, the first gating filter unit filters the received buffer signal and outputs it to the operational circuit, and the second gating filter unit sends the second signal output by the device under test to the operational circuit.

5. The circuit according to claim 4, characterized in that, The first gating filter unit includes a resistor R17, a capacitor C5, a switch S3, and a switch S5. The first end of the resistor R17 is connected to the near-end buffer circuit. The second end of the resistor R17 is connected to the first end of the capacitor C5 and the first end of the switch S5. The second end of the capacitor C5 is connected to signal ground. The second end of the switch S5 is connected to the first end of the switch S3 and the operational circuit. The second end of the switch S3 is connected to the device under test.

6. The circuit according to claim 4, characterized in that, The second gating filter unit includes a resistor R18, a capacitor C6, a switch S4, and a switch S6. The first end of the resistor R18 is connected to the near-end buffer circuit. The second end of the resistor R18 is connected to the first end of the capacitor C6 and the first end of the switch S6. The second end of the capacitor C6 is connected to signal ground. The second end of the switch S6 is connected to the first end of the switch S4 and the operational circuit. The second end of the switch S4 is connected to the device under test.

7. The circuit according to claim 2, characterized in that, The operational circuit includes operational amplifier U7, operational amplifier U8, operational amplifier U9, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, resistor R25, resistor R26, resistor R27, resistor R28 and resistor R29. The first end of resistor R21 is connected to the filter circuit and connected to signal ground through resistor R19. The second end of resistor R21 is connected to the non-inverting input of operational amplifier U7. The first end of resistor R22 is connected to the filter circuit and connected to signal ground through resistor R20. The second end of resistor R22 is connected to the non-inverting input of operational amplifier U8. The inverting input of operational amplifier U7 is connected to the first ends of resistor R23 and R24. The second end of resistor R23 is connected to the first end of resistor R25 and the inverting input of operational amplifier U8. The second end of resistor R24 ​​is connected to the output of operational amplifier U7. The second end of resistor R25 is connected to the output of operational amplifier U8. The first end of resistor R26 is connected to the output of operational amplifier U7. The second end of resistor R26 is connected to the inverting input of operational amplifier U9 and the first end of resistor R28. The second end of resistor R28 is connected to the output of operational amplifier U9 and the analog-to-digital converter. The first end of resistor R27 is connected to the output of operational amplifier U8. The second end of resistor R27 is connected to the non-inverting input of operational amplifier U9 and the first end of resistor R29. The second end of resistor R29 is connected to a bias signal source.

8. The circuit according to any one of claims 1-7, characterized in that, The near-end buffer circuit includes an operational amplifier U10, resistors R30 and R31, capacitors C7 and C8. The first end of resistor R30 is connected to the load ground. The second end of resistor R30 is connected to the first end of resistor R31 and the first end of capacitor C7. The second end of resistor R31 is connected to the non-inverting input of operational amplifier U10 and the first end of capacitor C8. The second end of capacitor C7 is connected to the inverting input and output of operational amplifier U10. The second end of capacitor C8 is connected to signal ground. The output of operational amplifier U10 is connected to the ground voltage difference compensation circuit.

9. A digital sampler, characterized in that, The device includes an FPGA, an analog-to-digital converter, and a load ground compensation circuit as described in any one of claims 1-8, wherein the FPGA is connected to the load ground compensation circuit via the analog-to-digital converter.

10. A testing machine, characterized in that, Includes the digital sampler as described in claim 9.

Images