Semiconductor device

Abstract

The utility model discloses a semiconductor device, comprising a substrate, a plurality of first lower electrodes arranged on the substrate, the plurality of first lower electrodes being arranged in an array in a first direction, a second direction and a third direction which are not perpendicular to each other, the outer contour of each first lower electrode being circular, a plurality of second lower electrodes arranged on the substrate, and a plurality of third lower electrodes arranged on the substrate, the outer contour of the second lower electrode comprises a main body and three protruding parts, the main body is circular, and the three protruding parts are arc-shaped and extend outwards from the center of the main body in the fourth direction, the fifth direction and the sixth direction respectively.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of semiconductor devices, in particular to a kind of semiconductor storage device. BACKGROUND

[0002] With the development trend of various electronic products towards miniaturization, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, so it has gradually replaced dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally, dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array region to store information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from the word line (WL) and bit line (BL). In response to product demand, the density of memory cells in the array region must continue to increase, causing the difficulty and complexity of related manufacturing processes and designs to increase continuously. Therefore, the existing technology or structure still needs to be further improved to effectively improve the performance and reliability of related memory devices. SUMMARY

[0003] The utility model provides a kind of semiconductor devices, including substrate, multiple first lower electrode is located on the substrate, the multiple first lower electrode is arranged into array in first direction, second direction and third direction not perpendicular to each other, the outer contour of each first lower electrode is circular, multiple second lower electrode is located on the substrate, the outer contour of the second lower electrode includes a main body and three protruding parts, wherein the main body is circular, the three protruding parts are circular arc, respectively from the center of the main body along the fourth direction, fifth direction and sixth direction extend outward.

[0004] The utility model further provides a kind of semiconductor devices, including substrate, multiple first lower electrode and second lower electrode are located on the substrate, the multiple first lower electrode is arranged into array adjacent to each other, wherein from section view, each first lower electrode presents I-shaped contour, and each second lower electrode presents U-shaped contour.

[0005] The utility model discloses a feature lies in, from the upper view, the second capacitance via hole OP2 is located in the second area A2, and the second lower electrode BE2 in the second capacitance via hole OP2 is surrounded in the periphery of the first lower electrode BE1 of a plurality of first capacitance via holes OP1, and the shape of second lower electrode BE2 is different from first lower electrode BE1. Because in the manufacturing process, the second area A2 is adjacent to the blank area (that is, the third area A3) without forming the element, therefore the element density difference of the two areas is larger, and the capacitance structure in the second area A2 is easily influenced by the load effect and is damaged. The utility model in the second area A2, with the method of overlapping first recess R1 and second recess R2, manufacture has the second capacitance via hole OP2 of larger area and special shape, therefore compared with the plurality of first capacitance via holes OP1 in the first area A1, the second capacitance via hole OP2 has larger coverage area, and the second capacitance via hole OP2 is composed of three first capacitance via holes OP1 and a center via hole, and its structure is stable and is not easily influenced by the load effect and is damaged. Therefore, the utility model is helpful to improve the quality of the capacitance structure in the edge area. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings provide a further understanding of embodiments of the present application and are incorporated in and constitute a part of this specification. The drawings along with the description are to explain some principles of the embodiments. It should be noted that all the drawings are schematic diagrams, and the relative size and proportion are adjusted for the purpose of illustration and drawing. The same symbols represent corresponding or similar features in different embodiments.

[0007] Figures 1-14 The drawing illustrates the step schematic diagram of the manufacturing method of the semiconductor device in the first embodiment of the utility model, wherein

[0008] Figure 1 It is the upper view after forming the first recess in the utility model;

[0009] Figure 2 It is Figure 1 The sectional view along the section line I-I' in the utility model;

[0010] Figure 3 It is the upper view after forming the second recess in the utility model;

[0011] Figure 4 It is Figure 3 The sectional view along the section line II-II' in the utility model;

[0012] Figure 5 It is the upper view after forming the third recess in the utility model;

[0013] Figure 6 It is Figure 5a cross-sectional view taken along the section line III-III';

[0014] Figure 7 an upper view after forming the first and second capacitor via holes in the utility model;

[0015] Figure 8 an upper view after forming the first and second capacitor via holes in the utility model; Figure 7 a cross-sectional view taken along the section line IV-IV';

[0016] Figure 9 an upper view after forming the first and second lower electrodes in the utility model;

[0017] Figure 10 an upper view after forming the first and second lower electrodes in the utility model; Figure 9 a cross-sectional view taken along the section line V-V';

[0018] Figure 11 an upper view after forming the support opening in the utility model;

[0019] Figure 12 an upper view after forming the support opening in the utility model; Figure 11 a cross-sectional view taken along the section line VI-VI';

[0020] Figure 13 an upper view after forming the capacitor dielectric layer and the upper electrode layer in the utility model;

[0021] Figure 14 an upper view after forming the capacitor dielectric layer and the upper electrode layer in the utility model; Figure 13 a cross-sectional view taken along the section line VII-VII';

[0022] Figure 15 an upper view after forming the capacitor dielectric layer and the upper electrode layer in the utility model; Figure 11 a local enlarged schematic view;

[0023] Figure 16 a cross-sectional structure schematic view of another semiconductor device in the utility model;

[0024] Figure 17 a cross-sectional structure schematic view of another semiconductor device in the utility model.

[0025] Wherein, the figure mark explanation is as follows:

[0026] 100: substrate

[0027] 110: support stack layer

[0028] 111: first support layer

[0029] 112: second support layer

[0030] 113: third support layer

[0031] 114: fourth support layer

[0032] 115: fifth support layer

[0033] 122: polysilicon layer

[0034] 124: oxide layer

[0035] 126: bottom antireflective coating

[0036] 128: photoresist layer

[0037] 130: capacitor dielectric layer

[0038] 140: protrusion

[0039] 142: body

[0040] 200: range

[0041] 210: recess (void)

[0042] 211: fully filled structure

[0043] 212: partially filled structure

[0044] A1: first region

[0045] A2: second region

[0046] A3: third region

[0047] AE1, AE2, AE3, AE4, AE5, AE6, AE7, AE8, AE9, AE10, AE11, AE12: arc-shaped boundary

[0048] BE1: first lower electrode

[0049] BE2: second lower electrode

[0050] C1: first capacitor structure

[0051] C2: second capacitor structure

[0052] D1: first direction

[0053] D2: second direction

[0054] D3: third direction

[0055] D4: fourth direction

[0056] D5: fifth direction

[0057] D6: sixth direction

[0058] O: center point

[0059] OP1: first capacitor via

[0060] OP2: second capacitor via

[0061] P: first pitch

[0062] R1: first recess

[0063] R2: second recess

[0064] R3: third recess

[0065] SOP1: first support opening

[0066] SOP2: second support opening

[0067] SNP: contact pad (storage node pad)

[0068] SNISO: insulating side wall

[0069] TE: top electrode layer

[0070] W1: first dimension

[0071] W2: second dimension

[0072] W3: third dimension

[0073] W4: fourth dimension DETAILED DESCRIPTION

[0074] While specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the relevant art that the present disclosure can also be employed in a variety of other applications.

[0075] Reference will now be made to the drawings, wherein Figures 1-14 the illustrated is a step schematic diagram of the method for manufacturing the semiconductor device in the first embodiment of the present application. Among them Figure 1 , Figure 3 , Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 are the top view of the semiconductor device, and Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 are the corresponding cross-sectional view of the semiconductor device. First, Figure 1 is the top view of the semiconductor device, Figure 2is a cross-sectional view taken along the cross-sectional line I-I'. As shown in Figure 1 and Figure 2 A substrate 100, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), a silicon-on-insulator (SOI) substrate, etc., or other suitable material layer, is provided. At least one shallow trench isolation (STI, not shown) is formed in the substrate 100, and a plurality of active areas (AA, not shown) are defined in the substrate 100. In addition, a plurality of gates, such as buried gates, can be formed in the substrate 100, where the buried gates can serve as buried word lines (BWL, not shown) for semiconductor devices. Since the formation of active areas, STI, buried gates, etc. are well known in the art, they are not repeated here. Instead, Figure 1 and Figure 2 The substrate 100 represents a structure layer including the above-mentioned elements.

[0076] In addition, a plurality of bit lines (not shown, BL) and a plurality of storage node pads (SNP) are formed on the substrate 100. Although the bit lines are not specifically shown in the drawings of the present embodiment, it is understood by those skilled in the art that the bit lines extend parallel to each other, are electrically isolated from the buried gates in the substrate 100 by an insulating layer (not shown, e.g., including a silicon oxide-silicon nitride-silicon oxide structure) covering the top surface of the substrate 100, and are electrically connected to the substrate 100 through bit line contacts (not shown, BLC) formed below the bit lines and extending into the active areas.

[0077] The storage node pads SNP are electrically connected to the substrate 100 to receive and deliver voltage signals from the substrate 100 (e.g., transistor components in the substrate 100). In one embodiment, the storage node pads SNP include a low-resistance metal material, such as aluminum (Al), titanium (Ti), copper (Cu), tungsten (W), etc., but are not limited thereto.

[0078] Again as shown in Figure 1 and Figure 2As shown, a support stack layer 110 continues to be formed on the substrate 100. Specifically, the support stack layer 110 includes, for example, alternating layers of multiple materials. In this embodiment, the support stack layer 110 may include, for example, a first support layer 111 (e.g., silicon nitride or silicon carbonitride), a second support layer 112 (e.g., borosilicate glass (BPSG)), a third support layer 113 (e.g., silicon nitride or silicon carbonitride), a fourth support layer 114 (e.g., silicon oxide), and a fifth support layer 115 (e.g., silicon nitride or silicon carbonitride) stacked sequentially from bottom to top, but is not limited thereto. Preferably, the second support layer 112 and the fourth support layer 114 may have a relatively large thickness, for example, approximately 5 to 10 times the thickness of the nitride layer (e.g., including the first support layer 111, the third support layer 113, or the fifth support layer 115). Thus, the overall thickness of the support layer structure 110 reaches approximately 1600 to 2000 angstroms, but is not limited thereto. Those skilled in the art will understand that the specific number of oxide layers and nitride layers stacked is not limited to this. Figure 1 and Figure 2 The number of layers shown is for reference only and can be adjusted to other numbers based on actual needs.

[0079] like Figure 1 and Figure 2 As shown, a polysilicon layer 122 serving as a mask layer and an oxide layer 124 are also formed on the support stack layer 110. Among them, in Figure 1 and Figure 2 In this process, the oxide layer 124 has undergone a patterning step (e.g., a photolithography process, but not limited to this) to form multiple first grooves R1 located within the oxide layer 124. See also... Figure 1 and Figure 2 A plurality of first grooves R1 are arranged in an array on a plane. More specifically, the plurality of first grooves R1 are arranged along a first direction D1, a second direction D2, and a third direction D3, respectively. The first direction D1, the second direction D2, and the third direction D3 are neither parallel nor perpendicular to each other. Preferably, Figure 1 and Figure 3 The four adjacent first grooves R1 can be arranged in a rhombus shape. That is, the distance from any first groove R1 along the second direction D2 to the adjacent first groove R1 can be equal to the distance from the first groove R1 along the third direction D3 to another adjacent first groove R1, but the present invention is not limited thereto.

[0080] For ease of explanation, let's first... Figure 4The first region A1, the second region A2 and the third region A3 are defined. The first recesses R1 are located in the first region A1 and the second region A2, and the third region A3 does not contain the first recesses R1. The second region A2 is located at the edge of the first region A1 and surrounds or encloses the first region A1, and the third region A3 surrounds or encloses the second region A2. That is, the range near the edge of the array of the first recesses R1 is defined as the second region A2, and the region outside the second region A2 which does not contain the first recesses R1 is defined as the third region A3. In the embodiment, the width of the second region A2 contains about 1 to 2 first recesses R1, but the present application is not limited thereto.

[0081] Figure 3 is a top view of a semiconductor device, Figure 4 is a cross-sectional view along the section line II-II'. As shown in Figure 3 and Figure 3 The bottom anti-reflective coating layer 126 and the photoresist layer 128 are formed to cover the polysilicon layer 122 and the patterned oxide layer 124. Then, a photoetching process is performed to pattern the photoresist layer 128, and a plurality of second recesses R2 are formed in the photoresist layer 128. It can be referred to Figure 5 The second recesses R2 are located in the second region A2, and the shape of the second recesses R2 can be rectangular, circular, polygonal or other shapes, and the present application is not limited thereto. Preferably, the shape of the second recesses R2 in the embodiment is circular, because according to the applicant's experiment, the structure of the circular second recesses R2 is more stable, which is beneficial to improve the structural strength of the subsequently formed capacitor structure. It is worth noting that, from the top view of Figure 6 , each second recess R2 overlaps with a plurality of first recesses R1. More specifically, each second recess R2 is located between three adjacent first recesses R1 and overlaps with the three first recesses R1.

[0082] Figure 5 is a top view of a semiconductor device, Figure 6 is a cross-sectional view along the section line III-III'. As shown in Figure 7 and Figure 8As shown, the etching step is then continued to transfer the pattern of the second recesses R2 into the underlying material layer. Specifically, the pattern of the second recesses R2 is transferred into the underlying oxide layer 124, and the excess bottom anti-reflective coating 126 and photoresist layer 128 are removed. As mentioned above, since the first recesses R1 partially overlap with the second recesses R2, the overlapping portions of the first recesses R1 and the second recesses R2 are defined as third recesses R3. That is, at this time, the oxide layer 124 contains a plurality of the first recesses R1 and a plurality of the third recesses R3 located therein. From the top view, the third recesses R3 are located within the second region A2, i.e., outside the periphery of the array of the first recesses R1. In addition, the third recesses R3 have a special shape, in which three protrusions in the form of circular arcs extend outwardly from a center point O of the third recess R3 toward three different directions D4, D5, D6. Here, the directions D4, D5, D6 are different from the first direction D1, the second direction D2, and the third direction D3 mentioned above. Specifically, the directions of the center points of the second recesses R2 toward the center points of the three first recesses R1 overlapping therewith are defined as the directions D4, D5, D6, but are not limited thereto.

[0083] Figure 7 a top view of the semiconductor device, Figure 8 a cross-sectional view taken along the cross-sectional line IV-IV'. As Figure 9 and Figure 10 As shown, the pattern transfer step, e.g., the etching step, is continued to transfer the patterns of the first recesses R1 and the third recesses R3 into the underlying support stack 110 using the oxide layer 124 as a mask. For example, a dry etching fabrication process is performed to sequentially pass through the fifth support layer 115, the fourth support layer 114, the third support layer 113, the second support layer 112, and the first support layer 111 to form a plurality of first capacitor vias OP1 and a plurality of second capacitor vias OP2 in the support stack 110. Each first capacitor via OP1 corresponds to the position of the first recess R1, and each second capacitor via OP2 corresponds to the position of the third recess R3. In addition, the bottom of each first capacitor via OP1 exposes one storage node pad SNP below, and the area of each second capacitor via OP2 is larger than that of the first capacitor via OP1, so that the bottom of each second capacitor via OP2 exposes a plurality (more than two) of storage node pads SNP below.

[0084] The positions of the first and second capacitor via OP1 and OP2 formed here will be used to form a plurality of capacitor structures in the subsequent steps. The first capacitor via OP1 is arranged in an array, and the second capacitor via OP2 is located at the periphery of the array of the first capacitor via OP1. The second capacitor via OP2 has the same shape as the third recess R3 described above, and has a larger area than the first capacitor via OP1. Therefore, the capacitor structure formed in the second capacitor via OP2 in the subsequent steps is more stable. In this embodiment, the second capacitor via OP2 can protect the first capacitor via OP1 located near the edge.

[0085] Figure 9 is a top view of the semiconductor device, Figure 10 is a cross-sectional view taken along the section line V-V'. As shown in Figure 9 and Figure 9 , a deposition and etch-back process is performed to form a plurality of lower electrodes BE1 in the first capacitor via OP1 and a second lower electrode BE2 in the second capacitor via OP2. In one embodiment, the process of forming the first lower electrode BE1 and the second lower electrode BE2 includes, but is not limited to, the following steps. First, an electrode material layer is formed in the first capacitor via OP1 and the second capacitor via OP2, which includes a low-resistance metal material such as titanium nitride, aluminum, titanium, copper, or tungsten, and preferably titanium nitride. The electrode material layer can fill the first capacitor via OP1 and cover the inner side surface and the bottom surface of the second capacitor via OP2, but does not fill the second capacitor via OP2. Then, the electrode material layer outside the first capacitor via OP1 and the second capacitor via OP2 is removed to form the first lower electrode BE1 with a I-shaped cross-section in the first capacitor via OP1 and the second lower electrode BE2 with a U-shaped cross-section in the second capacitor via OP2. It can be understood that the first lower electrode BE1 and the second lower electrode BE2 have the same material (both are made of the electrode material layer). The bottom of the second lower electrode BE2 spans at least two storage node contact pads SNP.

[0086] In addition, as shown in Figure 10 , since the first lower electrode BE1 fills the first capacitor via OP1 and the first capacitor via OP1 has a circular profile, the first lower electrode BE1 also has a circular profile. In addition, since the second lower electrode BE2 does not fill the second capacitor via OP2 but covers the side surface of the second capacitor via OP2, from the top view, there is still a gap in the middle of the second capacitor via OP2 that is not filled by the second lower electrode BE2. The U-shaped second lower electrode BE2 formed in the second capacitor via OP2 is formed on the inner side surface of the second capacitor via OP2, and the outer boundary of the second lower electrode BE2 has three arc-shaped protrusions corresponding to the three vertices of the triangle, respectively. (For details, please refer toFigure 11 and Figure 12 as shown.

[0087] Figure 11 is a top view of the semiconductor device, Figure 12 is a cross-sectional view taken along the section line VI-VI'. As Figure 13 and Figure 14 shown, a wet etching process can then be performed, such as by introducing an etchant, such as tetramethylammonium hydroxide (TMAH), to remove the remaining portions of the fourth support layer 114 and the second support material layer 112. At this point, the first support material layer 111, the third support material layer 113, and the fifth support material layer 115 remain in the support stack 110 between each of the first lower electrodes BE1 and / or the second lower electrodes BE2, which can serve as a structure to stabilize the lower electrodes.

[0088] Furthermore, to further increase the support effect between the first lower electrodes BE1 and / or the second lower electrodes BE2, an etching process can be performed after the wet etching process described above, using a mask (not shown) to form support openings in the remaining support material layers of the support stack 110. The support openings can include openings between the first lower electrodes BE1 and adjacent first lower electrodes BE1, which are defined as first support openings SOP1, and openings between the first lower electrodes BE1 and the second lower electrodes BE2, which are defined as second support openings SOP2. In the present embodiment, the first support openings SOP1 and the second support openings SOP2 have different shapes, and preferably, the first support openings SOP1 have a larger area than the second support openings SOP2. The first support openings SOP1 are circular or polygonal, and the outer periphery of the first support openings SOP1 extends through adjacent first lower electrodes BE1 and partially exposes the sidewalls of the adjacent first lower electrodes BE1. The second support openings SOP2 extend through a first lower electrode BE1 and an adjacent second lower electrode BE2, and partially expose the sidewalls of the first lower electrode BE1 and the second lower electrode BE2. In subsequent steps, the first support openings SOP1 and the second support openings SOP2 are filled with a capacitor dielectric layer and an upper electrode layer, and serve as support structures between the electrodes, thereby further stabilizing the structure.

[0089] Figure 13 is a top view of the semiconductor device, Figure 14 is a cross-sectional view taken along the section line VI-VI'. As Figure 13 and Figure 14As shown, at least one deposition fabrication process is performed to sequentially form the capacitor dielectric layer 130 and the upper electrode layer TE. The capacitor dielectric layer 130 is conformally deposited on the exposed surfaces of the first lower electrode BE1 and the second lower electrode BE2, the fifth support layer 115, and the first support opening SOP1 and the second support opening SOP2, while the upper electrode layer TE is deposited on the capacitor dielectric layer 130 and fills the remaining space between the second lower electrode BE2 and the first support opening SOP1 and the second support opening SOP2. In one embodiment, the capacitor dielectric layer 130 includes a high dielectric constant dielectric material, such as zirconium-aluminum-zirconium oxide (ZAZ), and the upper electrode layer TE includes a low resistance metal material, such as titanium nitride, aluminum, titanium, copper, tungsten, a semiconductor material, such as SiGe, or a combination thereof, such as a multi-layer structure of titanium nitride and SiGe, but the present application is not limited thereto. It is noted that Figure 13 and Figure 15 The upper electrode layer TE covers all device surfaces in Figure 15 , but for the convenience of viewing the structural features of the present embodiment from the top view,

[0090] At this step, a plurality of capacitor structures have been formed, each of which is composed of the first bottom electrode BE1 and / or the second bottom electrode BE2, the capacitor dielectric layer 130 and the top electrode layer TE stacked in sequence. More specifically, the capacitor structure composed of the first bottom electrode BE1, the capacitor dielectric layer 130 and the top electrode layer TE can be defined as a first capacitor structure C1, and the capacitor structure composed of the second bottom electrode BE2, the capacitor dielectric layer 130 and the top electrode layer TE can be defined as a second capacitor structure C2. The second capacitor structure C2 is located at the periphery of the array of the first capacitor structures C1 and can protect the peripheral structure of the array of the first capacitor structures C1. In other words, the second capacitor structure C2 can be regarded as a dummy capacitor structure. The first capacitor structure C1 and the capacitor structure C2 serve as a storage node (SN) of the semiconductor device, wherein each capacitor is electrically connected to a transistor component (not shown) in the substrate 100 through a storage node pad SNP. In this arrangement, the semiconductor device of the present embodiment can form a dynamic random access memory (DRAM) device, which is composed of at least one transistor component and at least one first capacitor structure C1 to form a memory cell in a DRAM array.

[0091] Before forming the capacitor structure, a contact plug can be formed to electrically connect the capacitor structure. The contact plug is formed by forming an interlayer dielectric layer on the previous semiconductor structure, and then forming the contact plug composed of a conductive material in the interlayer dielectric layer. The contact plug includes, but is not limited to, aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper and the like, and preferably includes tungsten. The above feature is known in the art and will not be described in detail.

[0092] In addition, the shapes of the first support opening SOP1 and the second support opening SOP2, and the shape of the second bottom electrode BE2 also have features. Please refer to Figure 15 , Figure 11 A partial enlarged top view of the first support opening SOP1, the second support opening SOP2, the first bottom electrode BE1 and the second bottom electrode BE2 of the semiconductor device of the present embodiment is shown. Figure 11 A partial enlarged top view of the first support opening SOP1, the second support opening SOP2, the first bottom electrode BE1 and the second bottom electrode BE2 of the semiconductor device of the present embodiment is shown. Figure 15 A partial enlarged top view of the first support opening SOP1, the second support opening SOP2, the first bottom electrode BE1 and the second bottom electrode BE2 of the semiconductor device of the present embodiment is shown. Figure 15 A partial enlarged top view of the first support opening SOP1, the second support opening SOP2, the first bottom electrode BE1 and the second bottom electrode BE2 of the semiconductor device of the present embodiment is shown. Figure 15As shown, the first support opening SOP1 is located between the three first lower electrodes BE1 from the upper view, each first lower electrode BE1 presents a circular profile, part of the boundary of the first support opening SOP1 contacts the sidewall of the first lower electrode BE1, and the other boundary of the first support opening SOP1 which does not contact the sidewall of the first lower electrode BE1 can be connected to a circle approximately. That is, the boundary of the first support opening SOP1 can be composed of six arc boundaries connected to each other, which are respectively defined as arc boundaries AE1, AE2, AE3, AE4, AE5 and AE6. Among them, the arc boundaries AE1, AE3 and AE5 have the same radius of curvature, and the arc boundaries AE2, AE4 and AE6 have the same radius of curvature, and in addition, the radius of curvature of the arc boundary AE1 is greater than that of the arc boundary AE2.

[0093] Please continue to refer to Figure 15 From the upper view, the second support opening SOP2 is located between the first lower electrode BE1 and the second lower electrode BE2, wherein the second lower electrode BE2 can include a main body 142 located in the middle and three protruding portions 140 located on the side, wherein the main body 142 presents a circular profile approximately, and the protruding portions 140 present a circular arc shape, and the three protruding portions 140 extend outward from the center point O of the main body 142 along directions D4, D5 and D6 respectively.

[0094] As for the second support opening SOP2 located between the first lower electrode BE1 and the second lower electrode BE2. The shape of the second support opening SOP2 can be a plurality of shapes composed of circular arcs. For example, in this embodiment, the boundary of the second support opening SOP2 can be composed of six arc boundaries connected to each other, which are respectively defined as arc boundaries AE7, AE8, AE9, AE10, AE11 and AE12. Among them, the arc boundaries AE7 and AE11 have the same radius of curvature, and the arc boundaries AE8, AE10 and AE12 have the same radius of curvature, and in addition, the radius of curvature of the arc boundary AE7 is greater than that of the arc boundary AE8, and the radius of curvature of the arc boundary AE9 is greater than that of the arc boundary AE7, but not limited to this. In addition, the radius of curvature of the arc boundary AE7 can be equal to the radius of curvature of the arc boundary AE1 of the first support opening SOP1, and the radius of curvature of the arc boundary AE8 can be equal to the radius of curvature of the arc boundary AE8 of the first support opening SOP1, but the present application is not limited to this.

[0095] The boundaries of the first support opening SOP1 and the second support opening SOP2 are composed of a plurality of arc boundaries. According to the applicant's experiment, the shape composed of arc boundaries has a relatively stable structure. Therefore, it is beneficial to improve the support effect of the capacitor structure. However, the present application is not limited to this, and the shape of the first support opening SOP1 and the second support opening SOP2 can be adjusted according to requirements.

[0096] In addition, as shown in Figure 16 , the first lower electrode BE1 has a first size (i.e. the diameter of the first lower electrode BE1), the second lower electrode BE2 has a second size W2, a third size W3 and a fourth size W4 in the first direction D1, the second direction D2 and the third direction D3 respectively, and the shortest distance between any two first lower electrodes BE1 is defined as a first pitch P, wherein at least one of the second size W2, the third size W3 and the fourth size W4 is not less than twice the sum of the first size W1 and the first pitch P, that is, taking the second size W2 as an example, the condition W2≥2W1+P is met. The rest of the third size W3 and the fourth size W4 are also the same.

[0097] The rest of the features of the first lower electrode BE1, the second lower electrode BE2, the first support opening SOP1 and the second support opening SOP2 can be referred to Figure 17 , which will not be described in detail here. It is worth noting that in other embodiments of the present application, the size, shape and arrangement of each element can be adjusted according to actual needs, and the present application is not limited in this way.

[0098] Figure 16 With Figure 17 , respectively, the cross-sectional structure of the semiconductor device according to two other different embodiments of the present application is shown. The semiconductor device according to Figure 14 , and Figure 16 , compared with the semiconductor device of the first embodiment shown in Figure 17 , to highlight the differences between the embodiments. For simplicity, the following description mainly describes the differences between the embodiments, and the same parts are not repeated. In addition, the same elements in each embodiment of the present application are marked with the same reference numerals for easy comparison between the embodiments. As shown in Figure 16 , and Figure 17 , when forming the first lower electrode BE1, the process parameters can be adjusted so that the first lower electrode BE1 does not fill the first capacitor via OP1, so that a recess 210 is left in the first lower electrode BE1. The recess 210 can be a void, and the capacitor dielectric layer 130 formed later can fill the recess 210 to form a fully filled structure 211 (as shown in Figure 16 ), or the capacitor dielectric layer 130 only partially fills the recess 210 to form a partially filled structure 212 (as shown in Figure 16 ), or the capacitor dielectric layer 130 does not fill the recess 210, but covers above the recess 210, so that the recess 210 is retained to form an air hole (as shown in Figure 17 ). It can be understood that different shapes of the first lower electrode BE1 can also be combined with each other by adjusting the process parameters, for example, the first lower electrode BE1 can beFigures 1-15 With Figures 1-17 The above various changes are all within the scope of the present application.

[0099] In combination with the above description and drawings, referring to the top view of Figure 16 The present application provides a semiconductor device, comprising a substrate 100, a plurality of first lower electrodes BE1 located on the substrate 100, the plurality of first lower electrodes BE1 arranged in an array in a first direction D1, a second direction D2 and a third direction D3 which are not perpendicular to each other, the outer contour of each first lower electrode BE1 being circular, a plurality of second lower electrodes BE2 located on the substrate 100, the outer contour of the second lower electrode BE2 comprising a main body 142 and three protruding portions 140, wherein the main body 142 is circular, and the three protruding portions 140 are circular arcs, respectively extending outward from the center O of the main body 142 along a fourth direction D4, a fifth direction D5 and a sixth direction D6.

[0100] In some embodiments of the present application, the plurality of second lower electrodes BE2 surround the array of the first lower electrodes.

[0101] In some embodiments of the present application, further comprising a capacitor dielectric layer 130 located on the first lower electrode BE1 and the second lower electrode BE2, and an upper electrode layer TE located on the capacitor dielectric layer 130.

[0102] In some embodiments of the present application, further comprising an opening (i.e. a second capacitor via OP2) located in each second lower electrode BE2, and the opening OP2 is filled with the capacitor dielectric layer 130 or / and the upper electrode layer TE.

[0103] In some embodiments of the present application, further comprising a recess 210 located in at least one first lower electrode BE1, and the recess 210 can comprise a void 210, a void partially filled with the capacitor dielectric layer (i.e. a partially filled structure 212) or a capacitor dielectric layer completely filled (i.e. a completely filled structure 211).

[0104] In some embodiments of the present application, the first lower electrode BE1 has a first size W1, the second lower electrode BE2 has a second size W2, a third size W3 and a fourth size W4 in the first direction D1, the second direction D2 and the third direction D3 respectively, and the shortest distance between any two first lower electrodes BE1 is defined as a first pitch P, wherein at least one of the second size W2, the third size W3 and the fourth size W4 is not less than twice the sum of the first size W1 and the first pitch P.

[0105] In some embodiments of the present application, the semiconductor device further comprises a support layer (supporting stack 110) surrounding the first lower electrodes BE1 and the second lower electrodes BE2, the support layer 110 comprises first support openings SOP1 between the plurality of first lower electrodes BE1, and second support openings SOP2 between the first lower electrodes BE1 and the second lower electrodes BE2.

[0106] In some embodiments of the present application, the area of the second support opening SOP2 is smaller than the area of the first support opening SOP1.

[0107] In some embodiments of the present application, the shape of the second support opening SOP2 is different from the shape of the first support opening SOP1.

[0108] In some embodiments of the present application, the first support opening SOP1 is circular or polygonal, and the outer contour of the first support opening SOP1 extends through the plurality of adjacent first lower electrodes BE1 and partially exposes the sidewall of the adjacent first lower electrodes BE1.

[0109] In some embodiments of the present application, the second support opening SOP2 is circular or polygonal, and the outer contour of the second support opening SOP2 extends through the at least one first lower electrode BE1 and the adjacent second lower electrode BE2, and partially exposes the sidewall of the first lower electrode BE1 and the second lower electrode BE2.

[0110] In some embodiments of the present application, the second support opening SOP2 partially exposes the sidewall of the main body 142 of the second lower electrode BE2 and the sidewall of the at least one protrusion 140.

[0111] In some embodiments of the present application, the outer contour of the second lower electrode BE2 is composed of three first circular arcs with a first radius of curvature and three second circular arcs with a second radius of curvature, and the first radius of curvature is smaller than the second radius of curvature.

[0112] Please refer to Figures 1-14 The present application further provides a semiconductor device, comprising a substrate 100, a plurality of first lower electrodes BE1 and second lower electrodes BE2 located on the substrate 100, and the plurality of first lower electrodes BE1 are arranged in an array adjacent to each other, wherein from the cross-sectional view, each first lower electrode BE1 presents an I-shaped contour, and each second lower electrode BE2 presents a U-shaped contour.

[0113] In some embodiments of the present application, from the cross-sectional view, the second lower electrode BE2 is located on one side of the array arranged by the first lower electrodes BE1.

[0114] In some embodiments of the present application, the capacitor further comprises a capacitor dielectric layer 130 on the first bottom electrode BE1 and the second bottom electrode BE2, and a top electrode layer TE on the capacitor dielectric layer 130.

[0115] In some embodiments of the present application, the second bottom electrode BE2 forms an opening OP2 from a cross-sectional view, and the opening OP2 is filled with the capacitor dielectric layer 130 and / or the top electrode layer TE.

[0116] In some embodiments of the present application, the capacitor further comprises a recess 210 in at least one of the first bottom electrodes BE1 from a cross-sectional view, and the recess 210 can comprise a gap 210, a gap partially filled with the capacitor dielectric layer (i.e., a partially filled structure 212), or a gap completely filled with the capacitor dielectric layer (i.e., a completely filled structure 211).

[0117] In some embodiments of the present application, the first bottom electrode BE1 has a first dimension W1 in a first direction (X direction) parallel to the substrate, the second bottom electrode BE2 has a second dimension W2 in the first direction, and the shortest distance between any two first bottom electrodes BE1 in the first direction is defined as a first pitch P, wherein the second dimension W2 is not less than twice the sum of the first dimension W1 and the first pitch P. Figure 1

[0118] In some embodiments of the present application, the capacitor further comprises a plurality of contact pads SNP on the substrate 100, and the contact pads SNP are between the second bottom electrode BE2 and the substrate 100, wherein the second bottom electrode BE2 contacts the plurality of contact pads SNP (the second bottom electrode BE2 spans at least two contact pads SNP).

[0119] According to the present application, a semiconductor device is provided, which comprises a substrate 100, a support stack 110 on the substrate 100, a mask layer (comprising a polysilicon layer 122, an oxide layer 124, a bottom anti-reflective coating layer 126, and a photoresist layer 128) on the support stack 110, a plurality of first recesses R1 in the mask layer formed by a first patterning step, a plurality of second recesses R2 in the mask layer formed by a second patterning step, a plurality of third recesses R3 defined by the overlapping portions of the first recesses R1 and the second recesses R2, a plurality of first capacitor vias OP1 and a plurality of second capacitor vias OP2 in the support stack 110 formed by an etching step using the patterned mask layer as a mask. Figure 2 Figure 3 Figure 4 ​ ​ ​​​​​​

[0120] In some embodiments of the utility model, each first capacitor via OP1 corresponds to each first recess R1, and each second capacitor via OP2 corresponds to each third recess R3.

[0121] In some embodiments of the utility model, the subsequent process further includes filling the lower electrode layer into each first capacitor via OP1 and second capacitor via OP2 to form the first lower electrode BE1 and the second lower electrode BE2.

[0122] In some embodiments of the utility model, as viewed from the top, each first capacitor via OP1 is circular, and each second capacitor via OP2 includes a main body 142 and three protruding parts 140, wherein the main body 142 is circular, and the three protruding parts 140 are circular arcs and are distributed on the fourth direction D4, the fifth direction D5 and the sixth direction D6 which are not perpendicular to each other.

[0123] In some embodiments of the utility model, the area of the second capacitor via OP2 is greater than three times the area of the first capacitor via OP1.

[0124] In some embodiments of the utility model, in addition to forming the first lower electrode BE1 and the second lower electrode BE2, the support opening is formed in the support stack layer 110, including the first support opening SOP1 between the plurality of first lower electrodes BE1 and the second support opening SOP2 between the first lower electrode BE1 and the second lower electrode BE2, and the area of the first support opening SOP1 is greater than the area of the second support opening SOP2.

[0125] In some embodiments of the utility model, the plurality of contact pads SNP are formed on the substrate 100, and each first capacitor via OP1 corresponds to one contact pad SNP, and each second capacitor via OP2 corresponds to a plurality of contact pads SNP.

[0126] The utility model discloses a feature lies in, from the upper view, second capacitance through -hole OP2 is located in second area A2, and the second lower electrode BE2 in second capacitance through -hole OP2 is surrounded in the periphery of a plurality of first capacitance through -hole OP1's first lower electrode BE1, and the shape of second lower electrode BE2 is different with first lower electrode BE1. Because in the manufacturing process, second area A2 is adjacent to the blank area (that is, third area A3) that does not form the component, therefore the component density difference of two regions is big, is easily affected by the load effect and leads to the damage of the capacitance structure in second area A2. The utility model in second area A2, with the method of overlapping first recess R1 and second recess R2, manufacture has the second capacitance through -hole OP2 of larger area and special shape, therefore compared with a plurality of first capacitance through -hole OP1 in first area A1, the second capacitance through -hole OP2's coverage area is larger, and the second capacitance through -hole OP2 is commonly composed of three first capacitance through -holes OP1 and a center through -hole, and its structure is stable and is not easily affected by the load effect and leads to damage. Therefore, the utility model is helpful to improve the quality of the capacitance structure in the edge area.

[0127] The above is only the preferred embodiment of the utility model, and does not limit the utility model, and for the person skilled in the art, the utility model can have various changes and changes. Any modification, equivalent replacement, improvement etc. that is made in the spirit and principle of the utility model should be included in the protection scope of the utility model.

Claims

1. A semiconductor device, characterized by, The substrate; a plurality of first lower electrodes on the substrate, the plurality of first lower electrodes arranged in an array in a first direction, a second direction and a third direction, each of the first lower electrodes having a circular outer profile; a plurality of second lower electrodes on the substrate, the second lower electrodes having an outer profile comprising a main body and three protrusions, wherein the main body is circular and the three protrusions are circular arcs extending outwardly from the center of the main body along a fourth direction, a fifth direction and a sixth direction, respectively. The plurality of second lower electrodes surround the array of the first lower electrodes.

2. The semiconductor device according to claim 1, wherein Further comprising:

3. The semiconductor device of claim 1, wherein a capacitor dielectric layer on the first lower electrodes and the second lower electrodes; an upper electrode layer on the capacitor dielectric layer. Further comprising an opening in each of the second lower electrodes, the opening filled with the capacitor dielectric layer or / and the upper electrode layer.

4. The semiconductor device according to claim 3, wherein Further comprising a recess in at least one of the first lower electrodes, the recess comprising a void, a void partially filled with the capacitor dielectric layer or a void completely filled with the capacitor dielectric layer.

5. The semiconductor device of claim 3, wherein The first lower electrodes have a first size, the second lower electrodes have a second size, a third size and a fourth size in the first direction, the second direction and the third direction, respectively, and the shortest distance between any two of the first lower electrodes defines a first pitch, wherein at least one of the second size, the third size and the fourth size is not less than twice the sum of the first size and the first pitch.

6. The semiconductor device of claim 1, wherein Further comprising:

7. The semiconductor device of claim 1, wherein a support layer surrounding the first lower electrodes and the second lower electrodes, the support layer comprising first support openings between the plurality of first lower electrodes and second support openings between the first lower electrodes and the second lower electrodes. Wherein the second support openings have an area smaller than the area of the first support openings.

8. The semiconductor device of claim 7, wherein, Wherein the second support openings have a shape different from the shape of the first support openings.

9. The semiconductor device of claim 7, wherein, The first support openings are circular or polygonal, and the outer profile of the first support openings extends through adjacent first lower electrodes and partially exposes the sidewalls of the adjacent first lower electrodes.

10. The semiconductor device of claim 7, wherein, The second support openings are circular or polygonal, and the outer profile of the second support openings extends through at least one first lower electrode and an adjacent second lower electrode and partially exposes the sidewalls of the first lower electrode and the second lower electrode.

11. The semiconductor device of claim 7, wherein, The second support openings partially expose the sidewalls of the main body of the second lower electrodes and the sidewalls of at least one of the protrusions.

12. The semiconductor device of claim 11, wherein, The outer profile of the second lower electrodes is composed of three first circular arcs having a first radius of curvature and three second circular arcs having a second radius of curvature, wherein the first radius of curvature is smaller than the second radius of curvature.

13. The semiconductor device of claim 1, wherein The substrate; 14. A semiconductor device, characterized by comprising: a plurality of first lower electrodes and second lower electrodes on the substrate, the plurality of first lower electrodes arranged adjacent to each other in an array, wherein each of the first lower electrodes has an I-shaped profile and each of the second lower electrodes has a U-shaped profile as viewed in a cross-sectional view; ​ ​ a plurality of contact pads on the substrate, the contact pads being between the first lower electrodes and the substrate and between the second lower electrodes and the substrate, while the bottom of the first lower electrodes and the bottom of the second lower electrodes directly contact the contact pads.

15. The semiconductor device of claim 14, wherein, The second lower electrodes are on one side of the array of the first lower electrodes in a cross-sectional view.

16. The semiconductor device of claim 14, wherein, Further comprising: a capacitor dielectric layer on the first lower electrodes and the second lower electrodes; an upper electrode layer on the capacitor dielectric layer.

17. The semiconductor device of claim 16, wherein, The second lower electrodes enclose an opening in a cross-sectional view, the opening being filled with the capacitor dielectric layer or / and the upper electrode layer.

18. The semiconductor device of claim 16, wherein, Further comprising a recess in at least one of the first lower electrodes in a cross-sectional view, the recess comprising a void, a void partially filled with the capacitor dielectric layer, or a void completely filled with the capacitor dielectric layer.

19. The semiconductor device of claim 14, wherein, The first lower electrodes have a first dimension in a first direction parallel to the substrate, the second lower electrodes have a second dimension in the first direction, and the shortest distance between any two of the first lower electrodes in the first direction defines a first pitch, wherein the second dimension is not less than twice the sum of the first dimension and the first pitch.

20. The semiconductor device of claim 14, wherein, The second lower electrodes contact the plurality of contact pads.

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