Test circuit

Abstract

The test circuit includes: a metal pattern disposed in the first region; a test gate driver disposed in a second region adjacent to the first region and including a plurality of test stages, each of the plurality of test stages outputting a test gate signal; and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each including a first metal line and a second metal line connected in series with the first metal line, and receiving a test gate signal.

Description

TECHNICAL FIELD

[0001] Embodiments generally provide a display apparatus. More particularly, embodiments relate to a test circuit for evaluating driving capability of a gate driver and a display apparatus including the test circuit. BACKGROUND

[0002] With the development of information technology, the importance of a display apparatus as a communication medium between a user and information is being highlighted. Accordingly, the use of display apparatuses such as liquid crystal display apparatuses, organic light emitting display apparatuses, and plasma display apparatuses is increasing.

[0003] Meanwhile, at least one test circuit can be disposed in a non-display area of the display apparatus. The driving capability of the gate driver disposed in the non-display area can be evaluated through the test circuit. The test circuit can be removed without being left in a final product, or the test circuit can not be removed and left in the final product. SUMMARY

[0004] Embodiments provide a test circuit capable of realizing a waveform substantially identical to a gate signal applied to a pixel.

[0005] Embodiments provide a display apparatus including the test circuit.

[0006] The test circuit according to an embodiment of the disclosure includes a metal pattern disposed in a first area, a test gate driver disposed in a second area adjacent to the first area and including a plurality of test stages each outputting a test gate signal, and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each including a first metal line and a second metal line connected in series to the first metal line, and receiving the test gate signal.

[0007] In an embodiment, the second metal line can have a resistance greater than a resistance of the first metal line.

[0008] In an embodiment, the first metal line can include a relatively low-resistance metal material compared to the second metal line.

[0009] In an embodiment, the second metal line can include a metal-oxide semiconductor.

[0010] In an embodiment, the first metal line can be directly connected to a corresponding one of the plurality of test stages.

[0011] In an embodiment, the second metal line can include a metal-oxide semiconductor doped with an N-type impurity.

[0012] In an embodiment, the first metal line can be connected to the second metal line through a contact hole.

[0013] In an embodiment, the first metal line can be adjacent to the second metal line in a first direction, a first width of the portion of the first metal line overlapping the metal pattern can be the same as a second width of the second metal line, and the first width and the second width can be measured in a second direction crossing the first direction.

[0014] In an embodiment, a first length of the portion of the first metal line overlapping the metal pattern can be different from a second length of the second metal line, and the first length and the second length can be measured in the first direction.

[0015] In an embodiment, the first length can be longer than the second length.

[0016] In an embodiment, the first length can be shorter than the second length.

[0017] In an embodiment, the metal pattern can include a plurality of sub-patterns connected to each other and overlapping the plurality of test gate lines in a plan view, respectively.

[0018] In an embodiment, the metal pattern can include a plurality of sub-patterns connected to each other, overlapping the plurality of test gate lines in a plan view, respectively, and arranged along a first direction. In the plan view, a plurality of openings arranged along a second direction crossing the first direction can be defined in each of the plurality of sub-patterns.

[0019] A test circuit according to an embodiment of the disclosure includes a metal pattern disposed in a first area, a test gate driver disposed in a second area adjacent to the first area and including a plurality of test stages each outputting a test gate signal, and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each having a zigzag shape in the plan view, and receiving the test gate signal.

[0020] In an embodiment, the metal pattern can include a plurality of sub-patterns connected to each other and overlapping the plurality of test gate lines in a plan view, respectively.

[0021] In an embodiment, the metal pattern can include a plurality of sub-patterns connected to each other, overlapping the plurality of test gate lines in a plan view, respectively, and arranged along a first direction. In the plan view, a plurality of openings arranged along a second direction crossing the first direction can be defined in each of the plurality of sub-patterns.

[0022] A display device according to an embodiment of the disclosure includes a display panel including a display area in which a plurality of pixels are disposed and a non-display area surrounding at least a portion of the display area and including a first test area; a gate driver disposed in the non-display area and applying a gate signal to the plurality of pixels; and a first test circuit disposed in the first test area and including a first metal pattern disposed in a first area of the first test area, a first test gate driver disposed in a second area of the first test area adjacent to the first area and including a plurality of test stages, each of the plurality of test stages outputting a first test gate signal, and a plurality of test gate lines overlapping the first metal pattern in a plan view, respectively connected to the plurality of test stages, each including a first metal line and a second metal line connected in series to the first metal line, and receiving the first test gate signal.

[0023] In an embodiment, the first metal line can be directly connected to a corresponding one of the plurality of test stages, and the second metal line can include a metal oxide semiconductor.

[0024] In an embodiment, the first metal line can be connected to the second metal line through a contact hole.

[0025] In an embodiment, the display device can further include a second test circuit disposed in a second test area located in the non-display area and including a third area and a fourth area, and including a second metal pattern disposed in the third area of the second test area, a second test gate driver disposed in the fourth area of the second test area adjacent to the third area and including a plurality of test stages, each of the plurality of test stages outputting a second test gate signal, and a plurality of test gate lines overlapping the second metal pattern in a plan view, respectively connected to the plurality of test stages of the second test gate driver, each having a zigzag shape in the plan view, and receiving the second test gate signal.

[0026] A test circuit according to an embodiment of the disclosure can include a plurality of test gate lines connected to a test gate driver and receiving a test gate signal and each including a first metal line and a second metal line connected in series to the first metal line. Alternatively, each of the plurality of test gate lines can have a zigzag shape in a plan view. Accordingly, a load corresponding to a resistance and a capacitance substantially identical to those of the display area can be reflected in the test circuit. In this case, a waveform of the test gate signal substantially identical to a gate signal applied to the pixel can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0027] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description with reference to the drawings, in which:

[0028] Figure 1is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a circuit diagram illustrating one pixel included in Figure 1 a display device.

[0030] Figure 3 is a view illustrating Figure 1 a gate driver.

[0031] Figure 4 is a cross-sectional view taken along line I-I' of Figure 1 a display device.

[0032] Figure 5 is a plan view illustrating an example of a test circuit provided in a test area of Figure 1 a display device.

[0033] Figure 6 is a view illustrating Figure 5 a test gate driver.

[0034] Figure 7 is a graph illustrating a waveform of a test gate signal applied to each of a first test gate pad and a second test gate pad of Figure 5 a display device.

[0035] Figure 8 is a cross-sectional view illustrating an example of a cross section taken along line II-II' of Figure 5 a display device.

[0036] Figure 9 is a cross-sectional view illustrating another example of a cross section taken along line II-II' of Figure 5 a display device.

[0037] Figure 10 is a plan view illustrating another example of a test circuit provided in a test area of Figure 1 a display device.

[0038] Figure 11 is a plan view illustrating still another example of a test circuit provided in a test area of Figure 1 a display device.

[0039] Figure 12 is a plan view for explaining a test gate line of Figure 11 a display device.

[0040] Figure 13 is a plan view illustrating still another example of a test circuit provided in a test area of Figure 1 a display device.

[0041] Figure 14 is a block diagram schematically illustrating a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, "a," "an," and "the" are not intended to refer to a quantity of one, but rather to one or more than one, unless the context clearly dictates otherwise. For example, "a" component has the same meaning as "at least one" of the component. "At least one" should not be construed as limiting "one" to a single entity. "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c," indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. It will be further understood that the terms "comprises" or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0043] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

[0044] It will be understood that when an element is referred to as being "on" another element, or "connected to" another element, it can be directly on the other element or directly connected to the other element, or an intervening element can be present. In contrast, when an element is referred to as being "directly on" another element, then there is no intervening element.

[0045] Hereinafter, a test circuit according to an embodiment of the disclosure and a display device including the test circuit will be explained in detail with reference to the accompanying drawings. The same reference numbers are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0046] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the disclosure.

[0047] Reference Figure 1The display device DD according to an embodiment of the disclosure can include a display panel DP, a plurality of data pads DDP, a plurality of data lines DL1 to DLm, a gate driver GDV, a plurality of gate lines GL1 to GLn, and a plurality of pixels PX (where each of n and m is a natural number greater than 1).

[0048] The display panel DP can include a display area DA and a non-display area NDA. The display area DA can be an area in which an image can be displayed by generating light or adjusting the transmittance of light provided from an external light source. The non-display area NDA can be an area in which an image is not displayed. The non-display area NDA can be located around the display area DA. For example, the non-display area NDA can completely surround the display area DA.

[0049] The plurality of pixels PX can be arranged in the display area DA. Each of the plurality of pixels PX can emit light to the outside of the display device DD through a light emitting element. For example, the plurality of pixels PX can be disposed in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1.

[0050] Each of the plurality of pixels PX can emit light having one preset color. For example, the plurality of pixels PX can include a first pixel emitting a first light, a second pixel emitting a second light, and a third pixel emitting a third light. For example, the first light can be red light, the second light can be green light, and the third light can be blue light. However, embodiments of the disclosure are not limited thereto. For example, the first pixel, the second pixel, and the third pixel can be combined to emit yellow light, cyan light, and magenta light.

[0051] The first pixel, the second pixel, and the third pixel can emit light of four or more colors. For example, the first pixel to the third pixel can be combined to emit at least one of yellow light, cyan light, and magenta light, in addition to red light, green light, and blue light. In addition, the first pixel, the second pixel, and the third pixel can be combined to further emit white light.

[0052] The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm can be disposed in the display area DA. The plurality of gate lines GL1 to GLn can be electrically connected to the plurality of pixels PX, respectively, and can provide a gate signal to the plurality of pixels PX. The plurality of data lines DL1 to DLm can be electrically connected to the plurality of pixels PX, respectively, and can provide a data voltage to the plurality of pixels PX. In addition, a plurality of power lines providing power to the plurality of pixels PX can be further disposed in the display area DA.

[0053] The plurality of gate lines GL1 to GLn can be sequentially arranged along the second direction DR2. Also, each of the plurality of gate lines GL1 to GLn can extend in the first direction DR1. The plurality of data lines DL1 to DLm can be sequentially arranged along the first direction DR1. Also, each of the plurality of data lines DL1 to DLm can extend in the second direction DR2.

[0054] A driver for generating a driving signal can be disposed in the non-display area NDA. For example, the driver can include a gate driver GDV generating a gate signal. The plurality of gate lines GL1 to GLn can be electrically connected to the gate driver GDV. Accordingly, the gate driver GDV can apply the gate signal to the plurality of gate lines GL1 to GLn. A detailed description of the gate driver GDV will be provided later.

[0055] The non-display area NDA can include a pad area PDA. The pad area PDA can be positioned away from one side of the display area DA. For example, the pad area PDA can have a shape extending in the first direction DR1.

[0056] A plurality of data pads DDP can be disposed in the pad area PDA. Specifically, the plurality of data pads DDP can be disposed along the first direction DR1. The plurality of data pads DDP can be electrically connected to the plurality of data lines DL1 to DLm, respectively. Accordingly, the plurality of data pads DDP can provide data voltages to the plurality of pixels PX through the plurality of data lines DL1 to DLm, respectively. For example, each of the plurality of data pads DDP can include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material, etc. These can be used alone or in combination with each other.

[0057] A driving device can be incorporated into the plurality of data pads DDP. As such, the plurality of data lines DL1 to DLm can receive driving signals (e.g., data voltages, etc.) from the driving device. For example, the driving device can be a rigid printed circuit board (PCB) or a flexible printed circuit board (FPCB) on which a driving chip is mounted. Alternatively, the driving device can be electrically connected to the pad area PDA and the data pads DDP through a connection member such as a flexible circuit film.

[0058] The non-display area NDA can further include at least one test area TA. The test area TA can be positioned away from one side of the display area DA. Figure 1 The position of the test area TA illustrated in FIG. 13 is illustrative, and embodiments of the present disclosure are not limited thereto. A test circuit (e.g., a test circuit TC of FIG. 14) for evaluating a driving capability of the gate driver GDV can be disposed in the test area TA. A detailed description of the test circuit will be provided later. As Figure 5 Figure 1 ​As illustrated in FIG. 1A, there can be one test area TA. Alternatively, there can be a plurality of test areas TA.

[0059] After a manufacturing process of the display device DD, the test circuit provided in the test area TA can be removed from the display device DD. Alternatively, after the manufacturing process of the display device DD, the test circuit provided in the test area TA can remain in the display device DD without being removed from the display device DD.

[0060] Figure 2 is a circuit diagram illustrating one pixel included in a display device of Figure 1 FIG. 1B.

[0061] Referring to Figure 2 The pixel PX can include a pixel circuit PC and a light emitting element LED electrically connected to the pixel circuit PC. Here, the pixel circuit PC can include a first transistor T1, a second transistor T2, and a third transistor T3, a storage capacitor CST, and a light emitting capacitor CLED.

[0062] The first transistor T1 can include a first electrode, a gate electrode, and a second electrode. The gate electrode of the first transistor T1 can be connected to a first node N1. A driving voltage ELVDD can be applied to the first electrode of the first transistor T1. The second electrode of the first transistor T1 can be connected to a second node N2. The first transistor T1 can receive the driving voltage ELVDD from a driving voltage line in response to a voltage of the first node N1 and supply a driving current to the light emitting element LED. For example, the first transistor T1 can be a driving transistor for driving the light emitting element LED.

[0063] The second transistor T2 can include a first electrode, a gate electrode, and a second electrode. A first gate signal SC can be applied to the gate electrode of the second transistor T2. A data voltage VDATA can be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 can be connected to the first node N1. The second transistor T2 can be turned on by the first gate signal SC to electrically connect a data line providing the data voltage VDATA to the first node N1. For example, the second transistor T2 can be a switching transistor.

[0064] The third transistor T3 can include a first electrode, a gate electrode, and a second electrode. A second gate signal SS can be applied to the gate electrode of the third transistor T3. An initialization voltage VINT can be applied to the first electrode of the third transistor T3. The second electrode of the third transistor T3 can be connected to the second node N2. The third transistor T3 can be turned on by the second gate signal SS to electrically connect an initialization voltage line providing the initialization voltage VINT to the second node N2. For example, the third transistor T3 can be an initialization transistor.

[0065] The storage capacitor CST can include a first electrode and a second electrode. The first electrode of the storage capacitor CST can be connected to the first node N1. The second electrode of the storage capacitor CST can be connected to the second node N2. The storage capacitor CST can store a voltage difference between the gate voltage and the source voltage of the first transistor T1.

[0066] The light emitting capacitor CLED can include a first electrode and a second electrode. The first electrode of the light emitting capacitor CLED can be connected to the second node N2. The second electrode of the light emitting capacitor CLED can be connected to the second electrode of the light emitting element LED. The light emitting capacitor CLED can maintain a voltage across the light emitting element LED constant, thereby allowing the light emitting element LED to display a constant brightness. Alternatively, the light emitting capacitor CLED can be omitted.

[0067] The light emitting element LED can include a first electrode (e.g., an anode electrode) and a second electrode (e.g., a cathode electrode). The first electrode of the light emitting element LED can be connected to the second node N2. The common voltage ELVSS can be applied to the second electrode of the light emitting element LED. The light emitting element LED can emit light having a brightness corresponding to a driving current supplied from the pixel circuit PC.

[0068] In Figure 2 , one pixel PX is shown to include three transistors T1, T2, and T3, one storage capacitor CST, and one light emitting capacitor CLED, but embodiments of the present disclosure are not limited thereto.

[0069] In addition, in Figure 2 , one pixel PX is shown to include one light emitting element LED, but embodiments of the present disclosure are not limited thereto. For example, one pixel PX can include two or more light emitting elements.

[0070] Figure 3 is a view illustrating Figure 1 a gate driver.

[0071] Referring to Figure 3 , the gate driver GDV can include a plurality of stages ST1 to STn. For example, the plurality of stages ST1 to STn can be connected to a plurality of gate lines GL1 to GLn, respectively (where n is a natural number greater than 1).

[0072] The plurality of stages ST1 to STn can output a plurality of gate signals in response to a first voltage VGL, a second voltage VGH, at least one clock signal CLK1 and CLK2, and a gate start signal FLM. The plurality of gate signals can be applied to the plurality of gate lines GL1 to GLn, respectively. The gate start signal FLM can be applied to the first stage ST1.

[0073] Figure 4 is a cross-sectional view taken along Figure 1 line I-I' of FIG. 1A. For example, Figure 4 is a view illustrating a cross-section of one pixel PX of FIG. 1A. Figure 1

[0074] Referring to Figure 4 , the display device DD can include a substrate SUB, a lower metal layer BML, a first conductive pattern CP1, a buffer layer BUF, a transistor TR, a second conductive pattern CP2, first to third insulating layers IL1, IL2, and IL3, a pixel definition layer PDL, a light emitting element EL, and an encapsulation layer ENC.

[0075] Here, the transistor TR can include an active layer ACT, a gate electrode GAT, a first electrode CE1, and a second electrode CE2, and the light emitting element EL can include a pixel electrode PE, a light emitting layer EML, and a common electrode CME.

[0076] The substrate SUB can include a transparent material or an opaque material. The substrate SUB can be made of a transparent resin substrate. Examples of the transparent resin substrate can include a polyimide substrate. In this case, the polyimide substrate can include a first organic layer, a first barrier layer, and a second organic layer, etc. Alternatively, the substrate SUB can include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda lime glass substrate, and an alkali-free glass substrate, etc. These can be used alone or in combination with each other.

[0077] The lower metal layer BML can be disposed on the substrate SUB. In a plan view, the lower metal layer BML can overlap the active layer ACT. The lower metal layer BML can prevent light from being incident on the active layer ACT, or can be electrically connected to the active layer ACT to stabilize the electrical characteristics of the transistor TR. For example, the lower metal layer BML can include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material, etc. Examples of the metal can include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and scandium (Sc), etc. Examples of the conductive metal oxide can include indium tin oxide and indium zinc oxide, etc. In addition, examples of the metal nitride can include aluminum nitride (AlN x ), tungsten nitride (WN x ), and chromium nitride (CrN x ), etc. These can be used alone or in combination with each other.

[0078] ​The first conductive pattern CP1 can be disposed on the substrate SUB. The first conductive pattern CP1 can be disposed in the same layer as the lower metal layer BML. That is, the first conductive pattern CP1 can be formed using the same material as the lower metal layer BML and by the same process as the lower metal layer BML.

[0079] The buffer layer BUF can be disposed on the substrate SUB. Also, the buffer layer BUF can cover the lower metal layer BML and the first conductive pattern CP1. The buffer layer BUF can prevent diffusion of metal atoms or impurities from the substrate SUB to the transistor (e.g., the transistor TR). Also, when the surface of the substrate SUB is not uniform, the buffer layer BUF can improve the flatness of the surface of the substrate SUB. For example, the buffer layer BUF can include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride. These can be used alone or in combination with each other.

[0080] The active layer ACT can be disposed on the buffer layer BUF. The active layer ACT can include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polysilicon), or an organic semiconductor. The active layer ACT can include a source region, a drain region, and a channel region between the source region and the drain region.

[0081] The metal oxide semiconductor can include a binary compound (AB x ), a ternary compound (AB x C y ), and a quaternary compound (AB x C y D z , etc. For example, the metal oxide semiconductor can include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), and indium gallium zinc oxide (IGZO), etc. These can be used alone or in combination with each other.

[0082] The first insulating layer IL1 can be disposed on the buffer layer BUF. Also, the first insulating layer IL1 can cover the active layer ACT. For example, the first insulating layer IL1 can include a material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO x N y ), and silicon oxycarbide (SiOx C y ) and the like. These can be used alone or in combination with each other.

[0083] The gate electrode GAT can be disposed on the first insulating layer IL1. In a plan view, the gate electrode GAT can overlap the channel region of the active layer ACT. For example, the gate electrode GAT can include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material, and the like. These can be used alone or in combination with each other.

[0084] The second conductive pattern CP2 can be disposed on the first insulating layer IL1. Also, in a plan view, the second conductive pattern CP2 can overlap the first conductive pattern CP1. The second conductive pattern CP2 can form the storage capacitor CST together with the first conductive pattern CP1. Figure 4 The storage capacitor CST of the active layer ACT can correspond to the storage capacitor CST of the gate electrode GAT. The second conductive pattern CP2 can be disposed in the same layer as the gate electrode GAT. That is, the second conductive pattern CP2 can use the same material as the gate electrode GAT and be formed through the same process as the gate electrode GAT. Figure 2

[0085] The second insulating layer IL2 can be disposed on the first insulating layer IL1 and the gate electrode GAT. The second insulating layer IL2 can cover the gate electrode GAT. For example, the second insulating layer IL2 can include an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO x N y ), and silicon oxycarbide (SiO x C y ) and the like. These can be used alone or in combination with each other.

[0086] The first electrode CE1 and the second electrode CE2 can be disposed on the second insulating layer IL2. The first electrode CE1 can be connected to the source region of the active layer ACT through a first contact hole penetrating the first insulating layer IL1 and the second insulating layer IL2. Also, the first electrode CE1 can be connected to the lower metal layer BML through a second contact hole penetrating the first insulating layer IL1, the second insulating layer IL2, and the buffer layer BUF. Accordingly, the transistor TR can be electrically connected to the lower metal layer BML. The second electrode CE2 can be connected to the drain region of the active layer ACT through a third contact hole penetrating the first insulating layer IL1 and the second insulating layer IL2.

[0087] ​For example, each of the first and second electrodes CE1 and CE2 can include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material, or the like. These can be used alone or in combination with each other.

[0088] A third insulating layer IL3 can be provided on the second insulating layer IL2. The third insulating layer IL3 can sufficiently cover the first and second electrodes CE1 and CE2. In addition, the third insulating layer IL3 can have a substantially flat upper surface. The third insulating layer IL3 can include an inorganic material or an organic material. In an embodiment, the third insulating layer IL3 can include an organic material. For example, the third insulating layer IL3 can include an organic material such as a phenol resin, a polyacrylate resin, a polyimide resin, a polyamide resin, a siloxane resin, and an epoxy resin, or the like. These can be used alone or in combination with each other.

[0089] Accordingly, a transistor TR including the active layer ACT, the gate electrode GAT, the first electrode CE1, and the second electrode CE2 can be formed on the substrate SUB. Figure 4 The transistor TR can correspond to a first transistor T1 of Figure 2 The transistor TR can correspond to a first transistor T1 of

[0090] A pixel electrode PE can be provided on the third insulating layer IL3. The pixel electrode PE can be connected to the first electrode CE1 through a contact hole penetrating a portion of the third insulating layer IL3. The pixel electrode PE can be a reflective, semi-transmissive, or transmissive electrode. For example, the pixel electrode PE can include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material, or the like. These can be used alone or in combination with each other.

[0091] A pixel definition layer PDL can be provided on the third insulating layer IL3. The pixel definition layer PDL can cover edges of the pixel electrode PE. In addition, an opening exposing a portion of the upper surface of the pixel electrode PE can be defined in the pixel definition layer PDL. For example, the pixel definition layer PDL can include an inorganic material or an organic material. In an embodiment, the pixel definition layer PDL can include an organic material such as an epoxy resin and a siloxane resin, or the like. These can be used alone or in combination with each other. In another embodiment, the pixel definition layer PDL can include an organic material including a light-blocking material such as a black pigment and a black dye.

[0092] An emission layer EML can be provided on the pixel electrode PE. The emission layer EML can include an organic material that emits light of a preset color. For example, the emission layer EML can include an organic material that emits at least one of red light, green light, and blue light.

[0093] A common electrode CME can be provided on the pixel definition layer PDL and the emission layer EML. The common electrode CME can be provided on a display area (e.g.,Figure 1 The common electrode CME can be a reflective, semi-transmissive, or transmissive electrode. For example, the common electrode CME can include a metal, an alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material, etc. These can be used alone or in combination with each other.

[0094] Accordingly, the light emitting element EL including the pixel electrode PE, the light emitting layer EML, and the common electrode CME can be formed in the display area on the substrate SUB. Figure 4 The light emitting element EL can correspond to the light emitting element LED. Figure 2 The light emitting element LED can correspond to the light emitting element EL.

[0095] An encapsulation layer ENC can be disposed on the common electrode CME. The encapsulation layer ENC can prevent impurities, moisture, external air, etc. from penetrating into the light emitting element EL from the outside. The encapsulation layer ENC can include at least one inorganic layer and at least one organic layer. For example, the inorganic layer can include silicon oxide, silicon nitride, and silicon oxynitride, etc. These can be used alone or in combination with each other. The organic layer can include a cured polymer such as polyacrylate, etc.

[0096] Figure 5 is a plan view illustrating an example of a test circuit disposed in a test area of Figure 1

[0097] Referring to Figure 1 and Figure 5 , a test circuit TC can be disposed in a test area TA. The test circuit TC can include a test gate driver GDV_T, a metal pattern MP, a plurality of test gate lines GL1_T to GLn_T, a first test gate pad TGP1, and a second test gate pad TGP2 (where n is a natural number greater than 1).

[0098] The test area TA can include a first area A1 and a second area A2. The second area A2 can be positioned adjacent to the first area A1.

[0099] The test gate driver GDV_T can be disposed in the second area A2. The plurality of test gate lines GL1_T to GLn_T can be electrically connected to the test gate driver GDV_T. Accordingly, the test gate driver GDV_T can apply a test gate signal to the plurality of test gate lines GL1_T to GLn_T. Detailed descriptions of the test gate driver GDV_T will be described later.

[0100] The metal pattern MP can be disposed in the first area A1. In the plan view, the metal pattern MP can overlap the plurality of test gate lines GL1_T to GLn_T. Accordingly, each of the plurality of test gate lines GL1_T to GLn_T can form a capacitor together with the metal pattern MP. ​

[0101] In an embodiment, in a plan view, the metal pattern MP can include a plurality of sub-patterns S-MP connected to each other and respectively overlapping a plurality of test gate lines GL1_T to GLn_T. Each of the plurality of sub-patterns S-MP can extend along the first direction DR1, and the plurality of sub-patterns S-MP can be arranged along the second direction DR2. In another embodiment, the metal pattern MP can be disposed as a plate.

[0102] In an embodiment, the metal pattern MP can be disposed in the same layer as a lower metal layer BML of Figure 4 . That is, the metal pattern MP can be formed with the lower metal layer BML of Figure 4 using the same material and by the same process. However, embodiments of the present disclosure are not limited thereto. Figure 4

[0103] Each of the plurality of test gate lines GL1_T to GLn_T can include a first metal line ML1 and a second metal line ML2 connected to the first metal line ML1. The second metal line ML2 can be adjacent to the first metal line ML1 in the first direction DR1. In an embodiment, the first metal line ML1 can be connected in series to the second metal line ML2. Specifically, the first metal line ML1 can be connected to the second metal line ML2 through a contact hole CNT.

[0104] In an embodiment, the first metal line ML1 can be directly connected to the test gate driver GDV_T. Specifically, the first metal line ML1 can be directly connected to a corresponding one of a plurality of test stages ST1_T to STn_T included in the test gate driver GDV_T (where n is a natural number greater than 1).

[0105] The first metal line ML1 can be disposed in the same layer as a gate electrode GAT of Figure 4 . That is, the first metal line ML1 can be formed with the gate electrode GAT of Figure 4 by the same process using the same material. However, embodiments of the present disclosure are not limited thereto. In an embodiment, the first metal line ML1 can include a relatively low-resistance metal material compared to the second metal line ML2.

[0106] The second metal line ML2 can be disposed in the same layer as an active layer ACT of Figure 4 . That is, the second metal line ML2 can be formed with the active layer ACT of Figure 4 by the same process and using the same material. However, embodiments of the present disclosure are not limited thereto. Figure 4 ​The active layer ACT is formed using the same material. However, embodiments of the present disclosure are not limited thereto. In an embodiment, the second metal line ML2 can include a metal-oxide semiconductor. For example, the second metal line ML2 can include a metal-oxide semiconductor doped with an N-type impurity. Alternatively, the second metal line ML2 can include a metal-oxide semiconductor doped with a P-type impurity.

[0107] As a result, the resistance of the second metal line ML2 can be greater than the resistance of the first metal line ML1. Since the first metal line ML1 is connected in series with the second metal line ML2, the resistance of each of the plurality of test gate lines GL1_T to GLn_T can be calculated as the sum of the resistance of the first metal line ML1 and the resistance of the second metal line ML2.

[0108] In this case, by adjusting the length L2 of the second metal line ML2 in the first direction DR1, the plurality of test gate lines GL1_T to GLn_T can have substantially the same resistance as the resistance of the plurality of gate lines GL1 to GLn of the active layer ACT. Even if the second length L2 of the second metal line ML2 is adjusted, the sum of the first length L1 of the portion of the first metal line ML1 overlapping the metal pattern MP in the plan view and the second length L2 of the second metal line ML2 can be constant. Figure 1

[0109] The width of each of the plurality of test gate lines GL1_T to GTn_T can be constant in the first direction DR1. That is, in an embodiment, the first width W1 of the first metal line ML1 in the second direction DR2 can be the same as the second width W2 of the second metal line ML2 in the second direction DR2. However, embodiments of the present disclosure are not limited thereto.

[0110] The first length L1 of the portion of the first metal line ML1 in the first direction DR1 can be different from the second length L2 of the portion of the second metal line ML2 in the first direction DR1. In an embodiment, the first length L1 of the portion of the first metal line ML1 in the first direction DR1 can be longer than the second length L2 of the portion of the second metal line ML2 in the first direction DR1. In another embodiment (not shown), the first length L1 of the portion of the first metal line ML1 in the first direction DR1 can be shorter than the second length L2 of the portion of the second metal line ML2 in the first direction DR1.

[0111] ​The first test gate pad TGP1 can be connected to at least one first metal line ML1 among the plurality of test gate lines GL1_T to GTn_T, and the second test gate pad TGP2 can be connected to at least one second metal line ML2 among the plurality of test gate lines GL1_T to GTn_T. For example, the first test gate pad TGP1 can be connected to the first metal line ML1 of the nth test gate line GLn_T, and the second test gate pad TGP2 can be connected to the second metal line ML2 of the nth test gate line GLn_T.

[0112] The test gate signal can be applied to the first test gate pad TGP1 before the test gate signal is applied to the first metal line ML1, and the test gate signal passing through the second metal line ML2 can be applied to the second test gate pad TGP2.

[0113] Figure 6 is a view illustrating Figure 5 a test gate driver.

[0114] Referring to Figure 6 , the test gate driver GDV_T can include a plurality of test stages ST1_T to STn_T. For example, the plurality of test stages ST1_T to STn_T can be connected to the plurality of test gate lines GL1_T to GLn_T, respectively (where n is a natural number greater than 1).

[0115] The plurality of test stages ST1_T to STn_T can output a plurality of test gate signals in response to a first voltage VGL', a second voltage VGH', at least one clock signal CLK1' and CLK2', and a test gate start signal FLM', the plurality of test gate signals can be applied to the plurality of test gate lines GL1_T to GLn_T, respectively. The test gate start signal FLM' can be applied to the first test stage ST1_T.

[0116] That is, the test gate driver GDV_T can be substantially the same as or similar to the gate driver GDV of Figure 3 .

[0117] Figure 7 is a graph illustrating a waveform of a test gate signal applied to each of the first test gate pad and the second test gate pad of Figure 5 . For example, Figure 7 the first signal waveform SW1 is a waveform of a test gate signal applied to the first test gate pad TGP1, and the second signal waveform SW2 is a waveform of a test gate signal applied to the second test gate pad TGP2.

[0118] Referring to Figure 5 and Figure 7Due to signal delay (RC delay), the test gate signal applied to the second test gate pad TGP2 can be delayed by τ compared to the test gate signal applied to the first test gate pad TGP1. The signal delay can be represented by Equation 1 below.

[0119] [Equation 1]

[0120] τ=R×C

[0121] Here, T is the signal delay, R is the resistance of a test gate line, and C is the capacitance of a capacitor consisting of a metal pattern MP and a test gate line.

[0122] In Equation 1, R can be represented by Equation 2 below.

[0123] [Equation 2]

[0124] R = R1 + R2

[0125] =R S1 ×(L1 / W)+R S2 ×(L2 / W)

[0126] =(R S1 ×(m×h-L2)+R S2 ×L2) / W

[0127] =L2×(R) S2 ×R S1 )+R S1 ×m×h

[0128] Here, R1 is the resistance of the first metal line ML1, R2 is the resistance of the second metal line ML2, and W is the width of the test gate (e.g., Figure 5 The first width W1 or the second width W2), L1 is the first length of the first metal wire ML1 (e.g., the first width W1 or the second width W2), L1 is the first length of the first metal wire ML1 (e.g., Figure 5 The first length L1), L2 is the second length of the second metal wire ML2 (e.g., Figure 5 The second length L2), R S1 It is the thin-film resistor of the first metal line ML1, R S2 It is the thin-film resistor of the second metal line ML2, and m is connected to a gate line (e.g., Figure 1 Multiple pixels (e.g., a metal pattern MP with a gate line GL1 to GLn) Figure 1 The number of pixels PX, each with a width W_P equal to the width of the other pixels and spaced apart from each other, and h is the width of each of the multiple pixels (e.g., ...). Figure 1 The width W_P). Furthermore, the sum of L1 and L2 is equal to the product of m and h (or similar).

[0129] In Equation 1, C can be represented by Equation 3 below.

[0130] [Equation 3]

[0131] C = W x (ε1 / d1 x L1 + ε2 / d2 x L2) = W x (ε1 / d1 x (m x h - L2) + ε2 / d2 x L2)

[0132] = ε / d x W x m x h

[0133] Here, W is a width of a test gate line (e.g., a first width W1 or a second width W2 of the test gate line 100), ε1 is a dielectric constant of a first portion of an insulating film, ε2 is a dielectric constant of a second portion of the insulating film, d1 is a thickness of the first portion of the insulating film, and d2 is a thickness of the second portion of the insulating film. The thickness of each of the first portion and the second portion is a thickness in a third direction (i.e., a third direction DR3 of the test gate line 100). The third direction can be perpendicular to a plane defined by a first direction DR1 and a second direction DR2 of the test gate line 100. Figure 5 Figure 4 Figure 1

[0134] The first portion is a portion of a buffer layer BUF and a first insulating layer IL1 of the test gate line 100 between a metal pattern MP and a first metal line ML1, and the second portion is a portion of the buffer layer BUF of the test gate line 100 between the metal pattern MP and a second metal line ML2. In addition, ε1 / d1 and ε2 / d2 are the same (or similar). A sum of L1 and L2 is equal to (or similar to) a product of m and h. ε / d is ε1 / d1 or ε2 / d2. Figure 8 Figure 8

[0135] Figure 8 is a cross-sectional view illustrating an example of a cross section taken along a line II-II' of the test gate line 100. Figure 5

[0136] Referring to FIG. 10A, in an embodiment, the first metal line ML1 can be directly connected to the second metal line ML2 through a contact hole that penetrates a portion of the first insulating layer IL1. Figure 8

[0137] Figure 9 is a cross-sectional view illustrating another example of a cross section taken along a line II-II' of the test gate line 100. Figure 5

[0138] Referring to FIG. 11A, in an embodiment, the first metal line ML1 can be directly connected to the second metal line ML2 through a contact hole that penetrates a portion of the first insulating layer IL1. Figure 9 ​​​​​​​​In an embodiment, the first metal line ML1 can be directly connected to the connection pattern CNP through a second contact hole CNT2 that penetrates a portion of the second insulating layer IL2, and the connection pattern CNP can be directly connected to the second metal line ML2 through a first contact hole CNT1 that penetrates a portion of the first insulating layer IL1. That is, in this case, the first metal line ML1 can be connected to the second metal line ML2 through the connection pattern CNP.

[0139] The connection pattern CNP can be disposed in the same layer as the gate electrode GAT of the test circuit TC. That is, the connection pattern CNP can be formed using the same material as the gate electrode GAT of the test circuit TC and through the same process. Figure 4 The first metal line ML1 can be disposed in the same layer as the first and second electrodes CE1 and CE2 of the test circuit TC. That is, the first metal line ML1 can be formed using the same material as the first and second electrodes CE1 and CE2 of the test circuit TC and through the same process. Figure 4 Figure 4 Figure 4

[0140] Figure 10 is a plan view illustrating another example of a test circuit disposed in a test area of a display device. Figure 1 Referring to

[0141] and Figure 1 , a test circuit TC' can be disposed in a test area TA. The test circuit TC' can include a test gate driver GDV_T, a metal pattern MP', a plurality of test gate lines GL1_T to GLn_T, a first test gate pad TGP1, and a second test gate pad TGP2 (where n is a natural number greater than 1). However, the test circuit TC' described with reference to Figure 10 may be substantially the same as or similar to the test circuit TC described with reference to Figure 10 . Hereinafter, repetitive descriptions are omitted or simplified. Figure 5 The test area TA can include a first area A1 and a second area A2. The second area A2 can be positioned adjacent to the first area A1.

[0142] The metal pattern MP' can be disposed in the first area A1. In a plan view, the metal pattern MP' can include a plurality of sub-patterns S-MP' connected to each other and respectively overlapping the plurality of test gate lines GL1_T to GLn_T. Each of the plurality of sub-patterns S-MP' can extend along a first direction DR1, and the plurality of sub-patterns S-MP' can be arranged along a second direction DR2.

[0143]

[0144] ​​​​In an embodiment, a plurality of openings OP arranged along the first direction DR1 can be defined in each of the plurality of sub-patterns S-MP'. Here, a width W_M of a portion of the metal pattern MP' located between two adjacent openings OP can be substantially the same as a width W_P of one pixel PX. Figure 1

[0145] Figure 11 is a plan view illustrating yet another example of a test circuit provided in a test region of Figure 1 Figure 12 is a plan view for explaining a test gate line of Figure 11 Figure 12 A test gate line GL_T of Figure 11 may correspond to any one of a plurality of test gate lines GL1_T' to GLn_T' of

[0146] With reference to Figure 1 , Figure 11 and Figure 12 , a test circuit TC" can be provided in a test region TA. The test circuit TC" can include a test gate driver GDV_T, a metal pattern MP, a plurality of test gate lines GL1_T' to GLn_T' (where n is a natural number greater than 1), a first test gate pad TGP1, and a second test gate pad TGP2. However, except for the plurality of test gate lines GL1_T' to GLn_T', the test circuit TC" described with reference to Figure 11 and 12 may be substantially the same as or similar to the test circuit TC described with reference to Figure 5 . Hereinafter, a repeated description is omitted or simplified.

[0147] The test region TA can include a first region A1 and a second region A2. The second region A2 can be located adjacent to the first region A1.

[0148] The test gate driver GDV_T can be provided in the second region A2. The plurality of test gate lines GL1_T' to GLn_T' can be electrically connected to the test gate driver GDV_T. Specifically, the plurality of test gate lines GL1_T' to GLn_T' can be connected to a plurality of test stages ST1_T to STn_T included in the test gate driver GDV_T, respectively. The plurality of test gate lines GL1_T' to GLn_T' can each receive a test gate signal through a corresponding one of the plurality of test stages ST1_T to STn_T.

[0149] The metal pattern MP can be provided in the first region A1. In a plan view, the metal pattern MP can overlap the plurality of test gate lines GL1_T' to GLn_T'. Accordingly, each of the plurality of test gate lines GL1_T' to GLn_T' can form a capacitor together with the metal pattern MP.​​​

[0150] In an embodiment, the metal pattern MP can include a plurality of sub-patterns S-MP connected to each other and respectively overlapping a plurality of test gate lines GL1_T' to GLn_T' in a plan view. Each of the plurality of sub-patterns S-MP can extend along the first direction DR1, and the plurality of sub-patterns S-MP can be arranged along the second direction DR2. In another embodiment, the metal pattern MP can be disposed as a plate.

[0151] In an embodiment, each of the plurality of test gate lines GL1_T' to GLn_T' can have a zigzag shape in a plan view. That is, each of the plurality of test gate lines GL1_T' to GLn_T' has a shape repeatedly passing through the first area A1 in the first direction DR1 and in a direction opposite to the first direction DR1 in a plan view.

[0152] A width W_G of each of the plurality of test gate lines GL1_T' to GLn_T' in the second direction DR2 can have a constant value. In addition, a gap S_G between adjacent portions of each of the plurality of test gate lines GL1_T' to GLn_T' in the second direction DR2 can have a constant value.

[0153] Each of the plurality of test gate lines GL1_T' to GLn_T' can be disposed in the same layer as a gate electrode GAT of Figure 4 . That is, each of the plurality of test gate lines GL1_T' to GLn_T' can be formed using the same material as the gate electrode GAT of Figure 4 , by the same process. However, embodiments of the disclosure are not limited thereto.

[0154] The first test gate pad TGP1 can be connected to at least one of the plurality of test gate lines GL1_T' to GLn_T', and the second test gate pad TGP2 can be connected to at least one of the plurality of test gate lines GL1_T' to GLn_T'. For example, the first test gate pad TGP1 can be connected to one end of the nth test gate line GLn_T', and the second test gate pad TGP2 can be connected to the other end of the nth test gate line GLn_T'.

[0155] In a case where each of the plurality of test gate lines GL1_T' to GLn_T' has a zigzag shape in a plan view, as Figure 7 indicated in FIG. 2B, due to signal delay, a test gate signal applied to the second test gate pad TGP2 can be delayed τ compared to a test gate signal applied to the first test gate pad TGP1.

[0156] The signal delay τ can be represented by Equation 4 below.

[0157] [Equation 4]

[0158] τ=R×C

[0159] Here, T is the signal delay, R is the resistance of a test gate line, and C is the capacitance of a capacitor consisting of a metal pattern MP and a test gate line.

[0160] In equation 4, R can be represented by equation 5 below.

[0161] [Equation 5]

[0162] R = R S ×L / W

[0163] =R S ×(m×h×r) / W

[0164] Here, R S It is the sheet resistance of a test gate line, L is the length of a test gate line in the first direction DR1, and W is the width of a test gate line (e.g., Figure 12 The width W_G). Additionally, m is connected to a gate line (e.g., Figure 1 Multiple pixels (e.g., a metal pattern MP with a gate line GL1 to GLn) Figure 1 The number of pixels PX, each with a width W_P equal to the width of the other pixels and spaced apart from each other, where h is the width of each pixel (e.g., ...). Figure 1 The width of the test gate is W_P), and r is the number of times a test gate line is repeated.

[0165] For example, in Figure 12 In this case, the repetition count of each of the multiple test gate lines GL1_T′ to GLn_T′ is 9. That is, the repetition count of each of the multiple test gate lines GL1_T′ to GLn_T′ refers to the number of patterns in which each of the multiple test gate lines GL1_T′ to GLn_T′ overlaps with the metal pattern MP in the planar diagram and extends in the first direction DR1.

[0166] In equation 4, C can be represented by equation 6 below.

[0167] [Equation 6]

[0168] C=ε / d×W×L

[0169] = ε / d × W × (m × h × r)

[0170] Here, ε is the dielectric constant of the insulating film, d is the thickness of the insulating film, and L is the length of a test gate line in the first direction DR1. The insulating film is a buffer layer (e.g., Figure 8a portion of the buffer layer BUF between the metal pattern MP and one of the test gate lines. In addition, m is the number of the plurality of pixels connected to one of the gate lines (e.g., GL1 to GLn of the test area TA), h is the width of each of the plurality of pixels (e.g., W_P of the metal pattern MP), and r is the number of repetitions of one of the test gate lines. Figure 1 a portion of the buffer layer BUF between the metal pattern MP and one of the test gate lines. In addition, m is the number of the plurality of pixels connected to one of the gate lines (e.g., GL1 to GLn of the test area TA), h is the width of each of the plurality of pixels (e.g., W_P of the metal pattern MP), and r is the number of repetitions of one of the test gate lines. Figure 1 a portion of the buffer layer BUF between the metal pattern MP and one of the test gate lines. In addition, m is the number of the plurality of pixels connected to one of the gate lines (e.g., GL1 to GLn of the test area TA), h is the width of each of the plurality of pixels (e.g., W_P of the metal pattern MP), and r is the number of repetitions of one of the test gate lines. Figure 1 a portion of the buffer layer BUF between the metal pattern MP and one of the test gate lines. In addition, m is the number of the plurality of pixels connected to one of the gate lines (e.g., GL1 to GLn of the test area TA), h is the width of each of the plurality of pixels (e.g., W_P of the metal pattern MP), and r is the number of repetitions of one of the test gate lines.

[0171] Figure 13 is a plan view illustrating another example of a test circuit provided in a test area of a display panel. Figure 1

[0172] Referring to Figure 1 and Figure 13 , a test circuit TC''' can be provided in the test area TA. The test circuit TC''' can include a test gate driver GDV_T, a metal pattern MP', a plurality of test gate lines GL1_T' to GLn_T' (where n is a natural number greater than 1), a first test gate pad TGP1, and a second test gate pad TGP2. However, the test circuit TC''' described with reference to Figure 13 may be substantially the same as or similar to the test circuit TC" described with reference to Figure 11 . Hereinafter, repeated descriptions are omitted or simplified.

[0173] The test area TA can include a first area A1 and a second area A2. The second area A2 can be positioned adjacent to the first area A1.

[0174] In the plan view, the metal pattern MP' can include a plurality of sub-patterns S-MP' connected to each other and respectively overlapping the plurality of test gate lines GL1_T' to GLn_T'. Each of the plurality of sub-patterns S-MP' can extend along the first direction DR1, and the plurality of sub-patterns S-MP' can be arranged along the second direction DR2.

[0175] In an embodiment, a plurality of openings OP arranged along the first direction DR1 can be defined in each of the plurality of sub-patterns S-MP'. Here, a width W_M of a portion of the metal pattern MP' located between two adjacent openings OP can be substantially the same as a width W_P of one of the pixels PX of the test area TA. Figure 1

[0176] Referring again to Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 ,​​Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 The test circuit TC, TC', TC", and TC'" according to the embodiment of the disclosure can include a plurality of test gate lines GL1_T to GLn_T and GL1_T' to GLn_T' connected to the test gate driver GDV_T and receiving the test gate signal and each including the first metal line ML1 and the second metal line ML2 connected in series with the first metal line ML1. Alternatively, each of the plurality of test gate lines GL1_T' to GLn_T' can have a zigzag shape in a plan view. Accordingly, a load corresponding to the resistance and the capacitance substantially identical to those of the display area DA can be reflected in the test circuit TC, TC', TC", and TC'". In this case, a waveform of the test gate signal substantially identical to the gate signal applied to the pixel PX can be implemented.

[0177] Figure 14 is a block diagram schematically illustrating a display apparatus according to another embodiment of the disclosure.

[0178] Referring to Figure 14 The display apparatus DD' according to the embodiment of the disclosure can include a display panel DP, a plurality of data pads DDP, a plurality of data lines DL1 to DLm, a gate driver GDV, a plurality of gate lines GL1 to GLn, and a plurality of pixels PX. Hereinafter, a description overlapping the description of the display apparatus DD described with reference to Figure 1 will be omitted or simplified.

[0179] The display panel DP can include a display area DA and a non-display area NDA. The non-display area NDA can surround at least a portion of the display area DA.

[0180] The non-display area NDA can include at least one first test area TA1 and at least one second test area TA2. Each of the first test area TA1 and the second test area TA2 can be positioned away from a side of the display area DA. Figure 14 The positions of the first test area TA1 and the second test area TA2 shown in

[0181] As shown in Figure 14 , the number of each of the first test area TA1 and the second test area TA2 is 1. Alternatively, each of the first test area TA1 and the second test area TA2 can be plural.

[0182] The first test circuit can be disposed in the first test area TA1. The first test circuit can correspond to the test circuit TC of FIG. 1A or the test circuit TC' of FIG. 1B. Figure 5 That is, the first test circuit can include a first metal pattern disposed in a first area of the first test area TA1, a first test gate driver disposed in a second area adjacent to the first area and including a plurality of test stages each outputting a first test gate signal, and a plurality of test gate lines overlapping the first metal pattern in a plan view, respectively connected to the plurality of test stages of the first test gate driver and receiving the first test gate signal, and each including a first metal line and a second metal line connected in series to the first metal line. Figure 10

[0183] The second test circuit can be disposed in the second test area TA2. The second test circuit can correspond to the test circuit TC" of FIG. 2A or the test circuit TC"' of FIG. 2B. Figure 11 That is, the second test circuit can include a second metal pattern disposed in a third area of the second test area TA2, a second test gate driver disposed in a fourth area adjacent to the third area and including a plurality of test stages each outputting a second test gate signal, and a plurality of test gate lines overlapping the second metal pattern in a plan view, respectively connected to the plurality of test stages of the second test gate driver and receiving the second test gate signal, and each having a zigzag shape in the plan view. Figure 13

[0184] The present disclosure can be applied to various display apparatuses. For example, the present disclosure is applicable to various display apparatuses such as display apparatuses for vehicles, ships, and airplanes, portable communication apparatuses, display apparatuses for exhibitions or information transmission, and medical display apparatuses, etc.

[0185] The foregoing is a detailed description of embodiments, and is not to be interpreted as limiting. Although a number of embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is a description of various embodiments, and is not to be interpreted as limiting. Modifications and other embodiments within the scope of the inventive concept will be apparent to those skilled in the art. Accordingly, the inventive concept is to be limited only as required by the appended claims.​​

Claims

1. A test circuit, comprising: a metal pattern disposed in a first region; a test gate driver disposed in a second region adjacent to the first region and including a plurality of test stages, each of the plurality of test stages outputting a test gate signal; and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each including a first metal line and a second metal line connected in series with the first metal line, and receiving the test gate signal.

2. The test circuit of claim 1, wherein, The second metal line has a resistance greater than a resistance of the first metal line.

3. The test circuit of claim 1, wherein, The first metal line is directly connected to a corresponding one of the plurality of test stages.

4. The test circuit of any one of claims 1-3, wherein, The first metal line is adjacent to the second metal line in a first direction, a first width of a portion of the first metal line overlapping the metal pattern is the same as a second width of the second metal line, and the first width and the second width are measured in a second direction crossing the first direction.

5. The test circuit of claim 4, wherein, a first length of the portion of the first metal line overlapping the metal pattern is different from a second length of the second metal line, and the first length and the second length are measured in the first direction.

6. The test circuit of claim 1, wherein, The metal pattern includes a plurality of sub-patterns connected to each other and overlapping the plurality of test gate lines, respectively, in the plan view.

7. The test circuit of claim 1, wherein, The metal pattern includes a plurality of sub-patterns connected to each other, overlapping the plurality of test gate lines, respectively, in the plan view, and arranged along a first direction, and a plurality of openings are defined in each of the plurality of sub-patterns in the plan view arranged along a second direction crossing the first direction.

8. A test circuit, comprising: a metal pattern disposed in a first region; a test gate driver disposed in a second region adjacent to the first region and including a plurality of test stages, each of the plurality of test stages outputting a test gate signal; and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each having a zigzag shape in the plan view, and receiving the test gate signal.

9. The test circuit of claim 8, wherein, The metal pattern includes a plurality of sub-patterns connected to each other and overlapping the plurality of test gate lines, respectively, in the plan view.

10. The test circuit of claim 8, wherein, The metal pattern includes a plurality of sub-patterns connected to each other, overlapping the plurality of test gate lines, respectively, in the plan view, and arranged along a first direction, and a plurality of openings are defined in each of the plurality of sub-patterns in the plan view arranged along a second direction crossing the first direction.

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