Watchdog control circuit and terminal equipment

Abstract

The utility model relates to the field of electronic circuits, and discloses a watchdog control circuit and terminal equipment, in the circuit, a voltage amplification module is used for amplifying a path of driving signal output by a processor before a boot loader is started to obtain a first amplification driving signal; the signal control module is used for controlling itself to be in a first working state according to the first amplification driving signal and outputting a first control signal; the watchdog module is used for keeping in a zero clearing state according to the first control signal; the voltage amplification module is also used for amplifying the two paths of driving signals output by the processor after the boot loader is started to correspondingly obtain a second amplified driving signal and a third amplified driving signal; the signal control module is further used for controlling the signal control module to be in a second working state according to the second amplification driving signal and transmitting a third amplification driving signal to the watchdog module; the watchdog module is further used for conducting repeated counting according to the third amplification driving signal so as to control starting and stopping of the watchdog function in real time.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a watchdog control circuit and a terminal device. BACKGROUND

[0002] In an embedded system, a watchdog control circuit can be used to monitor computer hardware and software, but the start and stop time of the watchdog control circuit in the prior art is uncontrollable, which can easily lead to frequent system restarts due to the watchdog function. CONTENT OF THE UTILITY MODEL

[0003] Therefore, the embodiments of the present application provide a watchdog control circuit and a terminal device, which can effectively solve the problem of being unable to effectively control the start and stop of the watchdog control circuit.

[0004] In a first aspect, the embodiments of the present application provide a watchdog control circuit, comprising:

[0005] a voltage amplification module, a signal control module and a watchdog module; the signal control module is connected with the voltage amplification module and the watchdog module respectively; the voltage amplification module is further connected with a processor, and the watchdog module is further connected with the processor and a memory respectively;

[0006] The voltage amplification module is configured to amplify a driving signal output by the processor before a boot loader is started, to obtain a first amplified driving signal.

[0007] The signal control module is configured to control itself to be in a first working state according to the first amplified driving signal, and output a first control signal.

[0008] The watchdog module is configured to remain in a clear state according to the first control signal.

[0009] The voltage amplification module is further configured to amplify two driving signals output by the processor after the boot loader is started, to correspondingly obtain a second amplified driving signal and a third amplified driving signal.

[0010] The signal control module is further configured to control itself to be in a second working state according to the second amplified driving signal, and transmit the third amplified driving signal to the watchdog module.

[0011] The watchdog module is further configured to repeatedly count according to the third amplified driving signal.

[0012] In some embodiments, the watchdog module is further configured to output a reset control signal when the third amplified driving signal maintains a single level signal for more than a preset time duration; wherein the single level signal is a high level signal or a low level signal.

[0013] In some embodiments, the voltage amplification module comprises: an enable signal amplification unit and a control signal amplification unit; the enable signal amplification unit and the control signal amplification unit are connected with the processor and the signal control module respectively;

[0014] The enable signal amplification unit is configured to amplify a first driving signal output by the processor before the bootloader is started, to obtain a first amplified driving signal, so that the signal control module is controlled by the signal control module to be in a high impedance state according to the first amplified driving signal;

[0015] The enable signal amplification unit is further configured to amplify a second driving signal output by the processor after the bootloader is started, to obtain a second amplified driving signal, so that the signal control module is controlled by the signal control module to be in a forward output state according to the second amplified driving signal;

[0016] The control signal amplification unit is configured to amplify a third driving signal output by the processor after the bootloader is started, to obtain a third amplified driving signal, so that the signal control module transmits the third amplified driving signal to the watchdog module when the signal control module is in the forward output state.

[0017] In some embodiments, the watchdog module comprises: a reset unit and a filter unit; the filter unit is connected with the reset unit, the memory and the processor respectively; the reset unit is further connected with the signal control module;

[0018] The reset unit is configured to control a timer of the reset unit to be in the clear state according to the first control signal, and to start counting according to the third amplified driving signal;

[0019] The reset unit is further configured to output a reset signal when a loss time of the third amplified driving signal exceeds a preset time length;

[0020] The filter unit is configured to filter the reset signal to obtain a reset control signal, to reset the processor and the memory.

[0021] In some embodiments, the signal control module comprises: a tri-state buffer, a first voltage dividing resistor, a second voltage dividing resistor and a first filter capacitor;

[0022] The enable end of the tri-state buffer is connected with one end of the first voltage dividing resistor, the other end of the first voltage dividing resistor is connected with one end of the second voltage dividing resistor and the voltage amplification module respectively, the input end of the tri-state buffer is connected with the voltage amplification module, the output end of the tri-state buffer is connected with the watchdog module, the power supply end of the tri-state buffer is connected with one end of the first filter capacitor and the power supply respectively, and the other end of the first filter capacitor is grounded.

[0023] In some embodiments, the reset unit comprises a reset chip, a second filter capacitor, a third voltage dividing resistor, a first feedback resistor and a fourth voltage dividing resistor.

[0024] The reset end of the reset chip is connected with one end of the second filter capacitor, one end of the third voltage dividing resistor and one end of the first feedback resistor respectively, and the watchdog output end of the reset chip is connected with the other end of the first feedback resistor.

[0025] The reset output end of the reset chip is connected with the filter unit, the watchdog input end of the reset chip is connected with one end of the fourth voltage dividing resistor, the other end of the third voltage dividing resistor is connected with the power supply, the other end of the fourth voltage dividing resistor is connected with the processor, and the other end of the second filter capacitor is grounded.

[0026] In some embodiments, the filter unit comprises a fifth voltage dividing resistor, a sixth voltage dividing resistor, a third filter capacitor and a seventh voltage dividing resistor.

[0027] One end of the fifth voltage dividing resistor is connected with the reset output end of the reset chip, one end of the third filter capacitor, one end of the sixth voltage dividing resistor and one end of the seventh voltage dividing resistor respectively, the other end of the sixth voltage dividing resistor is connected with the memory, the other end of the seventh voltage dividing resistor is connected with the processor, the other end of the fifth voltage dividing resistor is connected with the power supply, and the other end of the third filter capacitor is grounded.

[0028] In some embodiments, the control signal amplification unit comprises an eighth voltage dividing resistor, a ninth voltage dividing resistor and a first triode.

[0029] The base of the first triode is connected with one end of the eighth voltage dividing resistor, the collector of the first triode is connected with one end of the ninth voltage dividing resistor and the input end of the tri-state buffer respectively, the other end of the eighth voltage dividing resistor is connected with the processor, the other end of the ninth voltage dividing resistor is connected with the power supply, and the emitter of the first triode is grounded.

[0030] In some embodiments, the enable signal amplification unit comprises a tenth voltage dividing resistor and a second triode.

[0031] The base of the second triode is connected with one end of the tenth piezoresistor, the collector of the second triode is connected with the signal control module, the other end of the tenth piezoresistor is connected with the processor, and the emitter of the second triode is grounded.

[0032] In a second aspect, the embodiments of the present application provide a terminal device, comprising a PCB board, wherein the watchdog control circuit as described above is arranged on the PCB board.

[0033] The embodiments of the present application have the following beneficial effects:

[0034] 1. Real-time monitoring and abnormality detection functions are provided for system software.

[0035] 2. After the signal control module is controlled to be in the second working state according to the second amplified driving signal, the third amplified driving signal as the watchdog feeding signal is transmitted to the signal control module, so that the watchdog module is repeatedly counted, thereby realizing flexible configuration of the input time of the watchdog feeding signal of the watchdog control circuit.

[0036] 3. The watchdog control circuit has independence and reliability. DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0038] Figure 1 A structural block diagram of the watchdog control circuit in the embodiments of the present application is shown;

[0039] Figure 2 A circuit diagram of the enable signal amplification unit of the watchdog control circuit in the embodiments of the present application is shown;

[0040] Figure 3 A circuit diagram of the control signal amplification unit of the watchdog control circuit in the embodiments of the present application is shown;

[0041] Figure 4 A circuit diagram of the signal control module of the watchdog control circuit in the embodiments of the present application is shown;

[0042] Figure 5 A circuit diagram of the watchdog module of the watchdog control circuit in the embodiments of the present application is shown.

[0043] Explanation of main element symbols:

[0044] 10-Watchdog control circuit; 20-Voltage amplification module; 21-Enable signal amplification unit; 22-Control signal amplification unit; 30-Signal control module; 40-Watchdog module; 41-Reset unit; 42-Filter unit; 50-Processor; 60-Memory; U1-Three-state buffer; U2-Reset chip; R1-First voltage dividing resistor; R2-Second voltage dividing resistor; R3-Third voltage dividing resistor; R4-First feedback resistor; R5-Fourth voltage dividing resistor; R6-Fifth voltage dividing resistor; R7-Sixth voltage dividing resistor; R8-Seventh voltage dividing resistor; R9-Eighth voltage dividing resistor; R10-Ninth voltage dividing resistor; R11-Tenth voltage dividing resistor; R12-Eleventh voltage dividing resistor; C1-First filter capacitor; C2-Second filter capacitor; C3-Third filter capacitor; C4-Fourth filter capacitor; C5-Fifth filter capacitor; Q1-First triode; Q2-Second triode. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments of the present application.

[0046] The components of the embodiments of the present application generally described and shown in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0047] Hereinafter, the terms "include", "have", and their synonymous words used in various embodiments of the present application are only intended to indicate that specific features, numbers, steps, operations, elements, components, or combinations of the foregoing are present, and should not be understood as excluding the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0048] Unless specifically defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in various embodiments of the present application.

[0049] Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments can be combined with each other unless there is a conflict.

[0050] The watchdog technology aims to detect, record the processor running status, and reset in abnormal cases. Watchdog technology can be implemented in both hardware and software.

[0051] Among them, the hardware watchdog is usually a special chip that monitors the voltage, current and other indicators of the circuit to determine whether the system is running normally. It runs independently of the main system and can automatically restart the system when a serious fault occurs, and can be widely used in various fields.

[0052] For example, the watchdog control circuit is usually composed of a timer and a monitor. The timer starts timing when the system starts, and if it does not receive a "feed dog" signal (i.e. a specific instruction or operation) from the software within the set time (timeout), it is considered that the system has failed, and the protection mechanism will be triggered, such as restarting the system, sending an alarm or notification. The monitor is responsible for real-time monitoring of the system's running state, including CPU usage, memory usage, hard disk space and network connection, etc., and once an anomaly or failure is found, the protection mechanism will also be triggered.

[0053] Software watchdogs run a monitoring program in the operating system to achieve this. The program checks the system's running state at regular intervals and performs corresponding operations when it finds an anomaly. Software watchdogs rely on the stability and reliability of the operating system.

[0054] However, the input signal monitoring timeout time of the WDI (Watchdog Input Pin, Chinese name: watchdog input pin) in the existing watchdog function is set to 1.0S-2.25S, and in reality, due to different times for each batch, the WDI monitoring time is about 1.6S, for example, 1.0s-1.6S. Therefore, for high-throughput systems or other complex systems, the system is powered on to start feeding the dog signal, and before that there is a preloader (The main work of the preloader is to initialize the environment to be loaded, so the time from power-on to the first feeding of the watchdog is difficult to control, and the long system startup time will far exceed 1.6S, at which time the watchdog control circuit cannot receive the input signal from the MCU input to the WDI pin within the set time (1.6S here), and after the timeout, the watchdog control circuit will determine the reset and output the reset to the system, which will cause the system to restart continuously.

[0055] Because the existing watchdog hardware circuit cannot control the start and stop of the watchdog control circuit in real time, the reset function of the watchdog control circuit is easily triggered during the system Uboot (U-boot: Universal Boot Loader, an open source project complying with the GPL (General Public License) clause) loading and starting period from the beginning of power supply, which causes the system to restart frequently.

[0056] Therefore, the present application provides a watchdog control circuit and a terminal device, which, by amplifying a driving signal output by a processor through a voltage amplification module to obtain a first amplified driving signal before the boot loader starts, and by controlling the signal control module to be in a first working state according to the first amplified driving signal and outputting a first control signal to make the watchdog module remain in a clear zero state, and by amplifying two driving signals output by the processor through the voltage amplification module to obtain a second amplified driving signal and a third amplified driving signal after the boot loader starts, and by transmitting the third amplified driving signal to the signal control module after the signal control module is controlled to be in a second working state according to the second amplified driving signal, so that the watchdog module is repeatedly counted, the different driving signals output by the processor are controlled, and finally the watchdog module is started or disabled within a specific time, so that the flexibility of the watchdog function is controlled, the system software is monitored and checked in real time, and the system is reset and other protection measures are taken after detecting an abnormality.

[0057] The watchdog control circuit will be described below in combination with some specific embodiments.

[0058] Figure 1 An architecture diagram of the watchdog control circuit of the embodiment of the present application is shown. Exemplarily, the watchdog control circuit 10 includes:

[0059] A voltage amplification module 20, a signal control module 30 and a watchdog module 40; the signal control module 30 is connected with the voltage amplification module 20 and the watchdog module 40 respectively; the voltage amplification module 20 is further connected with a processor 50, and the watchdog module 40 is further connected with the processor 50 and a memory 60 respectively.

[0060] The voltage amplification module 20 is configured to amplify one driving signal output by the processor 50 before the boot loader starts to obtain a first amplified driving signal; the signal control module 30 is configured to control itself to be in a first working state according to the first amplified driving signal and output a first control signal; and the watchdog module 40 is configured to keep in a clear zero state according to the first control signal.

[0061] The voltage amplification module 20 is also configured to amplify two driving signals output by the processor 50 after the boot loader starts to obtain a second amplified driving signal and a third amplified driving signal; the signal control module 30 is also configured to control itself to be in a second working state according to the second amplified driving signal and transmit the third amplified driving signal to the watchdog module 40; and the watchdog module 40 is also configured to repeatedly count according to the third amplified driving signal.

[0062] The first amplified driving signal is a low-level signal, the first working state is a high-impedance state, the second amplified driving signal is a high-level signal, the second working state is a forward output state, the third amplified driving signal is a square wave signal, and the memory 60 can be a flash chip (FLASH).

[0063] Exemplarily, the specific implementation process of the watchdog control circuit 10 in the application is as follows:

[0064] First, from the time when the watchdog control circuit 10 starts to supply power to the boot loader (English name: Uboot: Universal Boot Loader, the main function is to start the operating system kernel) before the boot loader starts, the watchdog control circuit needs to be controlled to be inoperative.

[0065] Then, the processor 50 (for example, MCU (Microcontroller Unit), MPU (Micro Processor Unit), SoC (System on a Chip) or CPU (Central Processing Unit)) outputs one driving signal to the voltage amplification module 20.

[0066] Then, the voltage amplification module 20 amplifies the one-way driving signal to obtain a low-level first amplified driving signal and outputs the first amplified driving signal to the signal control module 30. The signal control module 30 controls itself to be in a high-impedance state (i.e., a first working state, which refers to an output state of a circuit, neither high level nor low level) according to the low-level signal (the first amplified driving signal). At this time, the signal output pin of the signal control module 30 also remains in the high-impedance state, and the feeding signal input pin of the watchdog module 40 also remains in the high-impedance state. According to the characteristics of the watchdog module 40, the watchdog module 40 remains in the clear state (i.e., a non-working state) according to the first control signal, and the watchdog does not work and does not count.

[0067] However, when the bootloader is started, the watchdog control circuit needs to be controlled to work normally, i.e., to start providing the "feeding" signal (a square wave and a fixed frequency signal) to it.

[0068] At this time, the processor 50 first outputs two-way driving signals to the voltage amplification module 20. The voltage amplification module 20 then amplifies the two-way driving signals and transmits the obtained high-level second amplified driving signal and the square wave third amplified driving signal to the signal control module 30.

[0069] Further, the signal control module 30 starts to work according to the high-level signal (the second amplified driving signal) and controls itself to be in a forward output state (i.e., a second working state, which means that the input and output are the same). Since the system software runs normally at this time, i.e., the processor 50 does not have a program runaway fault, the processor 50 directly transmits the normal output square wave signal (the third amplified driving signal, i.e., the feeding signal) to the watchdog module 40.

[0070] Finally, the watchdog module 40 starts the timing function and begins to count after being normally powered. However, since the watchdog module 40 receives the square wave third amplified driving signal, the watchdog module 40 will re-count when the input signal has a rising edge or a falling edge, thereby realizing the timer counting of the timing clear, to complete the normal "feeding", so the reset output function of the watchdog will not start and will not control the system to frequently reset.

[0071] Different bootloaders of different chips start at different times, so by monitoring the time from power-on to the start of the bootloader of each chip, the feeding signal of the watchdog module 40 is controlled to be in a high-impedance state to control the watchdog module 40 to be in a clear state (i.e., a non-working state) during this period. Since the bootloader will have a waveform or serial port print display when loading, the start time of the bootloader can be monitored.

[0072] It can be understood that, in the present application, before the boot loader is started, the control signal control module 30 is in a high impedance state by controlling the first amplified drive signal output by the voltage amplification module 20 to the processor 50, so that the watchdog module 40 remains in a clear state, and after the boot loader is started, the control signal control module 30 is in a forward output state by controlling the second amplified drive signal and the second amplified drive signal obtained by amplifying two drive signals output by the voltage amplification module 20 to the processor 50, so that the watchdog module 40 starts counting, thereby realizing effective control of the start and shutdown of the watchdog control circuit, and avoiding repeated restart of the entire system after the watchdog control circuit is started before the boot loader is started.

[0073] For example, in one embodiment, the watchdog module 40 is further configured to output a reset control signal when the third amplified drive signal is maintained at a single level signal for more than a preset time duration; wherein the single level signal is a high level signal or a low level signal.

[0074] The preset time duration is the watchdog timeout period of the watchdog module 40, that is, as long as the input signal does not change in level within the watchdog timeout period, the watchdog module 40 will stop the reset timer function and output a reset signal.

[0075] For example, in one embodiment, the watchdog module 40 is further configured to output a reset control signal when the third amplified drive signal is maintained at a single level signal for more than a preset time duration; wherein the single level signal is a high level signal or a low level signal.

[0076] For example, in one embodiment, the voltage amplification module 20 includes an enable signal amplification unit 21 and a control signal amplification unit 22; the enable signal amplification unit 21 and the control signal amplification unit 22 are respectively connected to the processor 50 and the signal control module 30.

[0077] The enable signal amplification unit 21 is configured to amplify the first driving signal output by the processor 50 before the bootloader is started to obtain a first amplified driving signal, so that the signal control module 30 is controlled by the first amplified driving signal to be in a high impedance state; the enable signal amplification unit 21 is also configured to amplify the second driving signal output by the processor 50 after the bootloader is started to obtain a second amplified driving signal, so that the signal control module 30 is controlled by the second amplified driving signal to be in a forward output state; the control signal amplification unit 22 is configured to amplify the third driving signal output by the processor 50 after the bootloader is started to obtain a third amplified driving signal, so that the signal control module 30 transmits the third amplified driving signal to the watchdog module 40 when the signal control module 30 is in the forward output state.

[0078] The first driving signal is a high-level signal, and the second driving signal is a low-level signal.

[0079] For example, before the bootloader is started, the processor 50 outputs a high-level first driving signal to the enable signal amplification unit 21, and the enable signal amplification unit 21 amplifies the first driving signal to obtain a first amplified driving signal, so that the signal control module 30 is in a high impedance state according to the first amplified driving signal.

[0080] However, after the bootloader is started, the processor 50 outputs a low-level second driving signal to the enable signal amplification unit 21, and the processor 50 outputs a third driving signal to the control signal amplification unit 22. Then, the enable signal amplification unit 21 correspondingly amplifies the second driving signal and the third driving signal to obtain a second amplified driving signal and a third amplified driving signal, and the control signal amplification unit 22, so that the signal control module 30 transmits the third amplified driving signal directly to the watchdog module 40 when the signal control module 30 is in a forward output state according to the first amplified driving signal.

[0081] It can be understood that, in the present application, the enable signal amplification unit 21 and the control signal amplification unit 22 amplify the input signals respectively to obtain stable and powerful driving signals to drive the signal control module 30.

[0082] Please refer to Figure 2 For example, in an embodiment, the enable signal amplification unit 21 includes a first voltage divider resistor R11 and a second transistor Q2.

[0083] The base of the second transistor Q2 is connected to one end of the first voltage divider resistor R11, the collector of the second transistor Q2 is connected to the signal control module 30 (identified as WDI_EN in Figure 2 ), the other end of the first voltage divider resistor R11 is connected to the processor 50, and the emitter of the second transistor Q2 is grounded.

[0084] As an example, one GPIO port of processor 50 (in) Figure 2 (Represented by GPIO13) is connected to the second transistor Q2 via the tenth voltage resistor R11. Before the bootloader starts, the processor 50 outputs the first drive signal, which is transmitted to the second transistor Q2 via the tenth voltage resistor R11 to drive whether the second transistor Q2 is turned on.

[0085] However, after the bootloader starts, the processor 50 outputs a second drive signal, which is transmitted to the second transistor Q2 through the tenth voltage resistor R11, to drive whether the second transistor Q2 is turned on or off.

[0086] It is understood that in this application, the time limit of the high and low level of the output signal is set separately through the GPIO13 port of the processor 50, so as to enable and disable the watchdog function at a specific time. This allows the watchdog reset to be controlled at any time, avoiding the watchdog's incorrect judgment due to the system not starting, which would lead to continuous reset.

[0087] Please see Figure 3 For example, in one embodiment, the control signal amplification unit 22 includes: an eighth voltage divider resistor R9, a ninth voltage divider resistor R10, an eleventh voltage divider resistor R12, and a first transistor Q1.

[0088] The base of the first transistor Q1 is connected to one end of the eighth voltage divider resistor R9, and the collector of the first transistor Q1 is connected to one end of the ninth voltage divider resistor R10 and the input terminal of the tri-state buffer U1 (in... Figure 3 The circuit is connected as follows: the eighth voltage divider resistor R9 is connected to the processor 50, the ninth voltage divider resistor R10 is connected to the power supply, and the emitter of the first transistor Q1 is grounded. One end of the eleventh voltage divider resistor R12 is connected to the collector of the first transistor Q1, and the other end of the eleventh voltage divider resistor R12 (via the SYSTEM_RUN lead) is connected to the light-emitting diode to indicate the signal input to the transistor by the processor 50.

[0089] The power supply is 3.3V. Figure 2 It is represented by VCC33 in Chinese.

[0090] As an example, another GPIO (General Purpose Input Output) port of processor 50 (in...) Figure 3 The third drive signal (represented by GPIO-RUN) is output and transmitted to the first transistor Q1 through the eighth voltage divider resistor R9 to drive whether the first transistor Q1 is turned on.

[0091] Please seeFigure 4 For example, in one embodiment, the signal control module 30 comprises a tri-state buffer U1, a first voltage dividing resistor R1, a second voltage dividing resistor R2 and a first filter capacitor C1.

[0092] The enable end of the tri-state buffer U1 is connected with one end of the first voltage dividing resistor R1, the other end of the first voltage dividing resistor R1 is connected with one end of the second voltage dividing resistor R2 and the voltage amplification module 20 respectively, the input end of the tri-state buffer U1 is connected with the voltage amplification module 20, the output end (indicated as WDI_Y in the figure) of the tri-state buffer U1 is connected with the watchdog module 40, and the power supply end of the tri-state buffer U1 is connected with one end of the first filter capacitor C1 and the power supply respectively, and the other end of the first filter capacitor C1 is grounded. Figure 4

[0093] For example, when the enable end OE of the tri-state buffer U1 inputs a high level signal, the output end Y of the tri-state buffer U1 will follow the signal output of the input end A of the tri-state buffer U1, that is, at this time, the signal control module 30 is in a forward output state, that is, if the input is a low level signal, the output is a low level signal; and if the input is a high level signal, the output is a high level signal.

[0094] However, when the enable end OE of the tri-state buffer U1 inputs a low level signal, no matter what signal is input to the input end A of the tri-state buffer U1, the output end Y of the tri-state buffer U1 will remain in a high impedance state.

[0095] For example, in one embodiment, the watchdog module 40 comprises a reset unit 41 and a filter unit 42; the filter unit 42 is connected with the reset unit 41, the memory 60 and the processor 50 respectively; and the reset unit 41 is further connected with the signal control module 30.

[0096] The reset unit 41 is configured to control a timer thereof to be in a clear zero state according to a first control signal, and control the timer to start counting according to a third amplification driving signal; the reset unit 41 is further configured to output a reset signal when the loss time of the third amplification driving signal exceeds a preset time length; and the filter unit 42 is configured to filter the reset signal to obtain a reset control signal to reset the processor 50 and the memory 60.

[0097] For example, after the tri-state buffer U1 controls itself to be in a high impedance state according to the first amplification driving signal, and outputs the first control signal to the reset unit 41, the reset unit 41 controls the timer thereof to remain in the clear zero state according to the first control signal.

[0098] ​After the third amplification control signal is transmitted to the reset unit 41, the reset unit 41 controls the timer to repeatedly count, i.e. the operation of resetting and counting, according to the third amplification control signal.

[0099] However, if the system software runs out of control, the third amplification control signal will be lost. At this time, the low-level signal is input to the reset unit 41, and the loss time exceeds the preset time length, i.e. the time of maintaining the low-level signal exceeds the preset time length. Then, the reset unit 41 outputs the low-level reset signal to the filter unit 42. The filter unit 42 filters the reset signal to obtain two reset control signals to reset the processor 50 and the memory 60 according to the reset control signals.

[0100] Please refer to Figure 5 For example, in one embodiment, the reset unit 41 includes a reset chip U2, a second filter capacitor C2, a fourth filter capacitor C4, a fifth filter capacitor C5, a third voltage dividing resistor R3, a first feedback resistor R4 and a fourth voltage dividing resistor R5.

[0101] The reset end of the reset chip U2 is connected with one end of the second filter capacitor C2, one end of the third voltage dividing resistor R3 and one end of the first feedback resistor R4, respectively. The watchdog output end of the reset chip U2 is connected with the other end of the first feedback resistor R4. The reset output end of the reset chip U2 is connected with the filter unit 42. The watchdog input end of the reset chip U2 is connected with one end of the fourth voltage dividing resistor R5. The other end of the third voltage dividing resistor R3, one end of the fourth filter capacitor C4 and one end of the fifth filter capacitor C5 are connected with the power supply. The other end of the fourth voltage dividing resistor R5 is connected with the processor 50. The other end of the second filter capacitor C2, the other end of the fourth filter capacitor C4 and the other end of the fifth filter capacitor C5 are grounded.

[0102] The model of the reset chip U2 includes SGM706.

[0103] For example, the / MR (manual reset input pin, i.e. the reset end) pin of the reset chip U2 is low-level effective, i.e. the low-level reset; the PFI is the power failure voltage monitor input pin; the / PFO is the power-off voltage monitor output pin; the WDI is the watchdog input pin (i.e. the watchdog input end); the / WDO is the watchdog output pin (i.e. the watchdog output end); and the / RESET is the reset output pin (i.e. the reset output end).

[0104] When the PFI pin is lower than a certain voltage, for example 1.25V, the / PFO pin will be low. When the PFI pin is greater than 1.25V, the / PFO pin will remain at high level.

[0105] If the WDI pin appears a rising or falling edge (e.g. square wave signal), the watchdog timer inside the reset chip U2 will be cleared and thus restart counting. However, if the WDI pin does not receive the expected input signal (e.g. square wave signal change) within a certain time, the watchdog timer will overflow and generate a reset signal; that is, if the WDI pin remains high or low for longer than the watchdog timeout period (TYP, i.e. the preset time length, for example 1.6s), the watchdog timer expires and the / WDO pin goes low. Then, the / WDO pin outputs a low level to the / MR pin, and the / MR pin being low causes the / RESET pin to output a low level to the MCU (processor 50) to reset the entire system.

[0106] Also, as long as the / RESET pin is set or the input of the WDI pin is set to high impedance state, the watchdog timer will remain in the cleared state and will not count. Once the / RESET is released and the WDI is set to high or low, the timer will start counting.

[0107] For example, in one embodiment, the filter unit 42 includes a fifth voltage dividing resistor R6, a sixth voltage dividing resistor R7, a third filter capacitor C3 and a seventh voltage dividing resistor R8.

[0108] One end of the fifth voltage dividing resistor R6 is connected to the reset output end of the reset chip U2, one end of the third filter capacitor C3, one end of the sixth voltage dividing resistor R7 and one end of the seventh voltage dividing resistor R8 respectively, the other end of the sixth voltage dividing resistor R7 is connected to the memory 60, the other end of the seventh voltage dividing resistor R8 is connected to the processor 50, the other end of the fifth voltage dividing resistor R6 is connected to the power supply, and the other end of the third filter capacitor C3 is grounded.

[0109] Among them, the sixth voltage dividing resistor R7 and the seventh voltage dividing resistor R8 are both 0 ohm resistors, in order to divide the reset signal output by the / RESET of the reset chip U2 into two networks, facilitating wiring and measurement.

[0110] Exemplarily, the other end of the sixth voltage dividing resistor R7 is connected to the DI / DO (digital input / output) pin of the memory 60 through the RST_OUT lead, and the other end of the seventh voltage dividing resistor R8 is connected to the / RESET_L (reset) pin of the processor 50 through the RST_B lead, so as to correspondingly control the processor 50 and the memory 60 to be reset when the reset signal output by the reset chip U2 appears, so that the system or terminal device is reset.

[0111] In order to better understand the present application, the following will be combined with Figures 2-5 The working principle of the watchdog control circuit 10 of the present application will be described in detail:

[0112] Please refer toFigure 2 and 4 In the system power on, that is, the watchdog control circuit 10 is powered on, the first driving signal outputted by the GPIO port (GPIO13 pin) of the control MCU is high level, and the first driving signal is transmitted to the second transistor Q2 through the tenth voltage dividing resistor R11. At this time, the second transistor Q2 is turned on, and the collector of the second transistor Q2 is pulled low, that is, the first amplified control signal is low level. Figure 2 The enable end OE of the tri-state buffer U1 connected with the collector of the second transistor Q2 is also pulled low through the WDI_EN lead, so that the output end Y of the tri-state buffer U1 is in a high impedance state (the first working state), and the watchdog input end of the reset chip U2 is also kept in a high impedance state, so that the timer inside the reset chip U2 is kept in a count zero state. Figure 2

[0113] However, in combination with Figure 3 After the Uboot is started, the GPIO13 pin of the control MCU outputs the second driving signal which is low level, and the eighth voltage dividing resistor R9 is transmitted to the first transistor Q1 through the third driving signal which is a square wave outputted by another GPIO port (GPIO16-RUN pin) of the control MCU. Figure 3

[0114] At this time, during the high level period of the square wave, the second transistor Q2 is turned on and the collector of the second transistor Q2 is pulled low; and during the low level period of the square wave, the first transistor Q1 is cut off and the collector of the second transistor Q2 is kept at high level, that is, the third amplified control signal is a square wave. At the same time, the second transistor Q2 is cut off, and the collector of the second transistor Q2 is kept at high level, that is, the second amplified control signal is high level.

[0115] Then, the enable end OE of the tri-state buffer U1 is also maintained at high level according to the high level of the second amplified control signal, so that the tri-state buffer U1 is in a forward output state (the second working state), that is, the output end Y of the tri-state buffer U1 follows the input end A of the tri-state buffer U1, and the output end Y of the tri-state buffer U1 will synchronously output the third amplified control signal of the square wave inputted to the input end A of the tri-state buffer U1.

[0116] Furthermore, the watchdog input end of the reset chip U2 starts to repeatedly reset and count according to the square wave signal inputted by the output end Y of the tri-state buffer U1.

[0117] ​​Finally, when the system has a program runaway and other failures, the third amplified drive signal can be a continuous single low-level signal. If the duration of the continuous low-level signal exceeds the preset time duration, the watchdog timer will overflow, generating a reset signal, i.e. the / WDO pin of the reset chip U2 outputs a low level to the / MR pin, and the / MR pin is low, which will cause the / RESET pin to output a low level to the MCU to reset the entire system.

[0118] The application also provides a terminal device, which comprises a PCB board. Exemplarily, the watchdog control circuit 10 described above is arranged on the PCB board, and thus will not be described again here.

[0119] It can be understood that the watchdog control circuit 10 provided by the application can be applied to multiple scenes, for example, scene 1, an embedded system: such as smart home, industrial automation equipment, etc., which needs to be stably operated for a long time, and the watchdog technology can ensure that the system is recovered in time when an exception occurs.

[0120] Scene 2, server and network equipment: guarantee the continuity and stability of the server and network equipment, and quickly respond to any failure or exception.

[0121] Scene 3, automotive electronics: in the vehicle-mounted electronic system, the watchdog can monitor software errors and sensor failures to ensure the safety and stability of the vehicle.

[0122] Scene 4, communication system: monitor the network connection state, and discover and solve network failures in time.

[0123] Scene 5, financial system: run under the extreme requirements of safety and stability, and the watchdog can monitor the system running state to prevent abnormal conditions such as failure and deadlock.

[0124] The above is only a specific embodiment of the application, but the protection scope of the application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered within the protection scope of the application.

Claims

1. A watchdog control circuit, characterized by The application relates to a voltage amplification module, a signal control module and a watchdog module; the signal control module is connected with the voltage amplification module and the watchdog module; the voltage amplification module is further connected with a processor; the watchdog module is further connected with the processor and a memory; The voltage amplification module is used for amplifying one driving signal output by the processor before a bootloader is started to obtain a first amplified driving signal; The signal control module is used for controlling itself to be in a first working state according to the first amplified driving signal and outputting a first control signal; The watchdog module is used for keeping in a clear zero state according to the first control signal; The voltage amplification module is further used for amplifying two driving signals output by the processor after the bootloader is started to correspondingly obtain a second amplified driving signal and a third amplified driving signal; The signal control module is further used for controlling itself to be in a second working state according to the second amplified driving signal and transmitting the third amplified driving signal to the watchdog module; The watchdog module is further used for repeatedly counting according to the third amplified driving signal. The watchdog module is further used for outputting a reset control signal when the third amplified driving signal maintains a single level signal for more than a preset time length; the single level signal is a high level signal or a low level signal.

2. The watchdog control circuit of claim 1, wherein, The voltage amplification module comprises an enabling signal amplification unit and a control signal amplification unit; the enabling signal amplification unit and the control signal amplification unit are connected with the processor and the signal control module; 3. The watchdog control circuit of claim 1, wherein, The enabling signal amplification unit is used for amplifying a first driving signal output by the processor before the bootloader is started to obtain the first amplified driving signal, so that the signal control module controls itself to be in a high impedance state according to the first amplified driving signal; The enabling signal amplification unit is further used for amplifying a second driving signal output by the processor after the bootloader is started to obtain the second amplified driving signal, so that the signal control module controls itself to be in a forward output state according to the second amplified driving signal; The control signal amplification unit is used for amplifying a third driving signal output by the processor after the bootloader is started to obtain the third amplified driving signal, so that the signal control module transmits the third amplified driving signal to the watchdog module when being in the forward output state. The watchdog module comprises a reset unit and a filter unit; the filter unit is connected with the reset unit, the memory and the processor; the reset unit is further connected with the signal control module; 4. The watchdog control circuit of claim 3, wherein, The reset unit is used for controlling a timer of itself to be in the clear zero state according to the first control signal and starting the timer to count according to the third amplified driving signal; The reset unit is further used for outputting a reset signal when a loss time of the third amplified driving signal is more than a preset time length. ​ The filter unit is configured to filter the reset signal to obtain a reset control signal, so as to reset the processor and the memory.

5. The watchdog control circuit of claim 3, wherein, The signal control module comprises a tri-state buffer, a first voltage dividing resistor, a second voltage dividing resistor and a first filter capacitor. An enable end of the tri-state buffer is connected with one end of the first voltage dividing resistor, the other end of the first voltage dividing resistor is connected with one end of the second voltage dividing resistor and the voltage amplification module respectively, an input end of the tri-state buffer is connected with the voltage amplification module, an output end of the tri-state buffer is connected with the watchdog module, power supply ends of the tri-state buffer are connected with one end of the first filter capacitor and a power supply respectively, and the other end of the first filter capacitor is grounded.

6. The watchdog control circuit of claim 4, wherein, The reset unit comprises a reset chip, a second filter capacitor, a third voltage dividing resistor, a first feedback resistor and a fourth voltage dividing resistor. A reset end of the reset chip is connected with one end of the second filter capacitor, one end of the third voltage dividing resistor and one end of the first feedback resistor respectively, and a watchdog output end of the reset chip is connected with the other end of the first feedback resistor. A reset output end of the reset chip is connected with the filter unit, a watchdog input end of the reset chip is connected with one end of the fourth voltage dividing resistor, the other end of the third voltage dividing resistor is connected with a power supply, the other end of the fourth voltage dividing resistor is connected with the processor, and the other end of the second filter capacitor is grounded.

7. The watchdog control circuit of claim 6, wherein, The filter unit comprises a fifth voltage dividing resistor, a sixth voltage dividing resistor, a third filter capacitor and a seventh voltage dividing resistor. One end of the fifth voltage dividing resistor is connected with the reset output end of the reset chip, one end of the third filter capacitor, one end of the sixth voltage dividing resistor and one end of the seventh voltage dividing resistor respectively, the other end of the sixth voltage dividing resistor is connected with the memory, the other end of the seventh voltage dividing resistor is connected with the processor, the other end of the fifth voltage dividing resistor is connected with the power supply, and the other end of the third filter capacitor is grounded.

8. The watchdog control circuit of claim 5, wherein, The control signal amplification unit comprises an eighth voltage dividing resistor, a ninth voltage dividing resistor and a first triode. A base of the first triode is connected with one end of the eighth voltage dividing resistor, a collector of the first triode is connected with one end of the ninth voltage dividing resistor and the input end of the tri-state buffer respectively, the other end of the eighth voltage dividing resistor is connected with the processor, the other end of the ninth voltage dividing resistor is connected with a power supply, and an emitter of the first triode is grounded.

9. The watchdog control circuit of claim 3, wherein, The enable signal amplification unit comprises a tenth voltage dividing resistor and a second triode. A base of the second triode is connected with one end of the tenth voltage dividing resistor, a collector of the second triode is connected with the signal control module, the other end of the tenth voltage dividing resistor is connected with the processor, and an emitter of the second triode is grounded.

10. A terminal device, comprising: The watchdog control circuit comprises a PCB, and the watchdog control circuit according to any one of claims 1-9 is arranged on the PCB.

Images