Automatic identification and conversion circuit for multi-interface signals
By combining detection pins and control signal outputs in the M.2 and SATA interface circuits, automatic identification and conversion of multi-interface signals is achieved, solving the problem of incompatibility between storage hard drive interfaces and providing a convenient interface conversion solution.
Patent Information
- Application Number
- CN202422705996.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-11-06
AI Technical Summary
In existing technologies, different data channels and interfaces of storage hard drives are incompatible with each other, which requires users to identify the interface and select the corresponding conversion card, making it inconvenient and restrictive.
Design an automatic identification and conversion circuit for multi-interface signals. By combining the detection pins defined in the M.2 interface circuit standard and the pins customized in the SATA interface circuit with the control of the PCIe signal output method, the circuit can automatically identify and convert the signals to the appropriate interface signals.
It achieves automatic identification and conversion of multiple interfaces such as PCIe to SATA, PCIe to M.2, and SATA to M.2, which greatly facilitates the compatible use of interface channel products. It has a simple structure and low cost.
Smart Images
Figure CN223526703U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to interface communication processing technical field, concretely relates to a kind of automatic identification conversion circuit of multi-interface signal. BACKGROUND
[0002] In the field of consumer electronics, due to the iteration of technology and other reasons, there are currently two main data channels, PCIE and SATA channels, and the connection interfaces include PCIE, M.2, and SATA interface circuits. Each interface cannot be directly compatible, causing various inconveniences in real life. The current market adapter cards can only realize one-to-one interface conversion, i.e., PCIE to M.2, SATA to M.2, PCIE to SATA, etc. Users need to identify the supported interfaces and channels of their products first, and then choose the corresponding conversion card. There is a problem of incompatibility between different data channels and interfaces, which limits the actual use and is inconvenient. SUMMARY
[0003] The utility model discloses a kind of automatic identification conversion circuit of multi-interface signal to solve the defects and deficiencies of prior art, with simple structure and can be compatible with the product of multiple interface channels.
[0004] To achieve the above purpose, the utility model takes the technical scheme of a kind of automatic identification conversion circuit of multi-interface signal, including main control circuit board, the main control circuit board is provided with power supply circuit, signal detection circuit, M.2 interface circuit, PCIE interface circuit, signal switching switch circuit, signal conversion circuit and SATA interface circuit;The multiple power supply circuits are connected with the M.2 interface circuit, PCIE interface circuit, SATA output interface circuit, signal detection circuit, signal switching switch circuit, signal conversion circuit;The signal conversion circuit, SATA interface circuit are connected with the signal switching switch circuit, and the signal detection circuit is connected with the M.2 interface circuit, SATA interface circuit, signal switching switch circuit communication.
[0005] Further, the signal switching circuit includes a logic chip, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first resistor and the second resistor are connected in series, one end of which is connected to the power circuit, and the other end is connected to the sixteenth pin of the logic chip. One end of the third resistor is connected to the sixteenth pin of the logic chip, and the other end is connected to the SATA interface circuit. The tenth pin, the eleventh pin, the twelfth pin, and the thirteenth pin of the logic chip are connected to the M.2 interface circuit. One end of the first capacitor is connected to the seventh pin of the logic chip, and the other end is connected to the PCIE interface circuit. One end of the second capacitor is connected to the fifth pin of the logic chip, and the other end is connected to the PCIE interface circuit. One end of the third capacitor is connected to the seventh pin of the logic chip, and the other end is connected to the PCIE interface circuit. The first pin and the third pin of the logic chip are connected to the PCIE interface circuit. One end of the third capacitor is connected to the sixth pin of the logic chip, and the other end is connected to the signal conversion circuit. One end of the fourth capacitor is connected to the fourth pin of the logic chip, and the other end is connected to the signal conversion circuit. The second pin and the fifteenth pin of the logic chip are connected to the signal conversion circuit. The ninth pin and the sixteenth pin of the logic chip are connected to the signal detection circuit. The eighth pin of the logic chip is grounded.
[0006] Further, the signal conversion circuit includes a signal conversion chip and a crystal oscillator. The sixth pin, the thirty-eighth pin, the forty-first pin, the forty-second pin, and the forty-eighth pin of the signal conversion chip are connected to the power circuit. The first pin of the crystal oscillator is connected to the fortieth pin of the signal conversion chip. The second pin and the fourth pin of the crystal oscillator are connected in series, and the fourth pin is grounded. The third pin of the crystal oscillator is connected to the thirty-ninth pin of the signal conversion chip. The thirteenth pin, the fourteenth pin, the fifteenth pin, the seventeenth pin, the eighteenth pin, the twentieth pin, and the twenty-first pin of the signal conversion chip are connected to the PCIE interface circuit. The twelfth pin and the thirteenth pin of the signal conversion chip are connected to the M.2 interface circuit.
[0007] Further, the signal detection circuit comprises a first MOS transistor, a second MOS transistor, a fourth resistor and a fifth resistor; one end of the fourth resistor is electrically connected with the power supply circuit, and the other end is electrically connected with the source electrode of the first MOS transistor; the gate electrode of the first MOS transistor is electrically connected with the M.2 interface circuit, the drain electrode of the first MOS transistor is electrically connected with the source electrode of the second MOS transistor, and the gate electrode of the second MOS transistor is electrically connected with the sixteenth pin of the logic chip and the SATA interface circuit; one end of the fifth resistor is electrically connected with the drain electrode of the second MOS transistor, and the other end is grounded; and the drain electrode of the second MOS transistor is electrically connected with the ninth pin of the logic chip.
[0008] Further, the model of the logic chip comprises but is not limited to HEF4008B.
[0009] Further, the power supply circuit comprises a first power supply, a second power supply and a third power supply, and the first power supply, the second power supply and the third power supply are electrically connected with the PCIE interface circuit and the SATA interface circuit.
[0010] The utility model discloses beneficial effect has:
[0011] The utility model provides a kind of automatic identification conversion circuit of multiple interface signals, it is defined in the detection pin of M.2 interface circuit standard, and then it is defined in a pin on SATA interface circuit, wherein, the detection pin of M.2 output interface is used to detect whether the product using this interface is PCIE channel or SATA channel, and the detection pin of SATA interface circuit is used to detect whether there is product access this interface, by combining the two to control whether PCIE signal is directly output to M.2 interface circuit or converted into SATA signal and then output to M.2 interface circuit or SATA interface circuit, to realize automatic identification and output;Realize the automatic identification conversion function of PCIE to SATA, PCIE to M.2, SATA to M.2 and other multiple interfaces, greatly facilitate the compatible use of various interface channel products, the application not only simple structure, strong practicality and low cost. BRIEF DESCRIPTION OF DRAWINGS
[0012] Fig. 1 It is the module diagram of the utility model a kind of automatic identification conversion circuit of multiple interface signals;
[0013] Fig. 2 It is the circuit principle diagram of signal conversion circuit in the utility model a kind of automatic identification conversion circuit of multiple interface signals;
[0014] Fig. 3 It is the circuit principle diagram of signal detection circuit in the utility model a kind of automatic identification conversion circuit of multiple interface signals;
[0015] Fig. 4 The circuit principle diagram of the signal switching switch circuit in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model;
[0016] Fig. 5 The circuit principle diagram of the SATA input interface circuit in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model;
[0017] Fig. 6 The circuit principle diagram of the M.2 interface circuit in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model;
[0018] Fig. 7 The circuit principle diagram of the PCIE interface circuit in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model;
[0019] Fig. 8 The circuit principle diagram of the SATA output interface circuit in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model;
[0020] Fig. 9 The circuit principle diagram of the first power supply in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model;
[0021] Fig. 10 The circuit principle diagram of the second power supply in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model;
[0022] Fig. 11 The circuit principle diagram of the third power supply in the automatic identification conversion circuit of the multi-interface signal is provided by the utility model. DETAILED DESCRIPTION
[0023] The technical solutions in the embodiments of the utility model will be clearly and completely described below with reference to the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.
[0024] It should be noted that all directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the utility model are only used to explain the relative position relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directionality indications also change accordingly.
[0025] In addition, the description of "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the technical features or implying the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor in the protection scope required by the present application.
[0026] The utility model provides a kind of automatic identification conversion circuit of multi-interface signal.
[0027] In the embodiments of the present application, as shown in Fig. 1-11 The automatic identification conversion circuit of multi-interface signal, including main control circuit board, is provided with power supply circuit, signal detection circuit, M.2 interface circuit, PCIE interface circuit, signal switching switch circuit, signal conversion circuit and SATA interface circuit on the main control circuit board;The plurality of power supply circuits are connected with the M.2 interface circuit, PCIE interface circuit, SATA output interface circuit, signal detection circuit, signal switching switch circuit, signal conversion circuit;The signal conversion circuit, SATA interface circuit are connected with the signal switching switch circuit, and the signal detection circuit is connected with the M.2 interface circuit, SATA interface circuit, signal switching switch circuit.
[0028] In the embodiment, the signal switching circuit includes a logic chip, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; the first resistor and the second resistor are connected in series, one end of which is connected with the power circuit, and the other end is connected with the sixteenth pin of the logic chip; one end of the third resistor is connected with the sixteenth pin of the logic chip, and the other end is connected with the SATA interface circuit; the tenth pin, the eleventh pin, the twelfth pin and the thirteenth pin of the logic chip are connected with the M.2 interface circuit; one end of the first capacitor is connected with the seventh pin of the logic chip, and the other end is connected with the PCIE interface circuit; one end of the second capacitor is connected with the fifth pin of the logic chip, and the other end is connected with the PCIE interface circuit; one end of the third capacitor is connected with the seventh pin of the logic chip, and the other end is connected with the PCIE interface circuit; the first pin and the third pin of the logic chip are connected with the PCIE interface circuit; one end of the third capacitor is connected with the sixth pin of the logic chip, and the other end is connected with the signal conversion circuit; one end of the fourth capacitor is connected with the fourth pin of the logic chip, and the other end is connected with the signal conversion circuit; the second pin and the fifteenth pin of the logic chip are connected with the signal conversion circuit; the ninth pin and the sixteenth pin of the logic chip are connected with the signal detection circuit; and the eighth pin of the logic chip is grounded.
[0029] In the embodiment, the signal conversion circuit includes a signal conversion chip and a crystal oscillator; the sixth pin, the thirty-eighth pin, the forty-first pin, the forty-second pin and the forty-eighth pin of the signal conversion chip are connected with the power circuit; the first pin of the crystal oscillator is connected with the fortieth pin of the signal conversion chip; the second pin and the fourth pin of the crystal oscillator are connected in series, and the fourth pin is grounded; the third pin of the crystal oscillator is connected with the thirty-ninth pin of the signal conversion chip; the thirteenth pin, the fourteenth pin, the fifteenth pin, the seventeenth pin, the eighteenth pin, the twentieth pin and the twenty-first pin of the signal conversion chip are connected with the PCIE interface circuit; and the twelfth pin and the thirteenth pin of the signal conversion chip are connected with the M.2 interface circuit.
[0030] In the embodiment, the signal detection circuit includes a first MOS transistor, a second MOS transistor, a fourth resistor and a fifth resistor; one end of the fourth resistor is electrically connected with the power supply circuit, and the other end is electrically connected with the source electrode of the first MOS transistor; the gate electrode of the first MOS transistor is electrically connected with the M.2 interface circuit, the drain electrode of the first MOS transistor is electrically connected with the source electrode of the second MOS transistor, and the gate electrode of the second MOS transistor is electrically connected with the sixteenth pin of the logic chip and the SATA interface circuit; one end of the fifth resistor is electrically connected with the drain electrode of the second MOS transistor, and the other end is grounded; and the drain electrode of the second MOS transistor is electrically connected with the ninth pin of the logic chip.
[0031] In the embodiment, the model of the logic chip includes but is not limited to HEF4008B.
[0032] In the embodiment, the power supply circuit includes a first power supply, a second power supply and a third power supply, and the first power supply, the second power supply and the third power supply are electrically connected with the PCIE interface circuit and the SATA interface circuit.
[0033] In actual use, the functions of PCIE to SATA, PCIE to M.2 and SATA to M.2 are realized on a conversion board, which requires accurate identification of the interface and channel used by the load. The application uses a detection pin defined in the M.2 interface circuit standard and a self-defined pin (which does not affect the use of SATA products using this interface) on the SATA interface circuit. The detection pin of the M.2 output interface is used to detect whether the product using this interface is a PCIE channel or a SATA channel, and the detection pin of the SATA interface circuit is used to detect whether a product is connected to this interface. By combining the two, the PCIE signal is directly output to the M.2 interface circuit (M.2 PCIE channel product) or converted into a SATA signal and then output to the M.2 interface circuit (M.2 SATA channel product) or the SATA interface circuit, thereby realizing automatic identification and output.
[0034] Specifically, the application realizes the automatic identification and conversion functions of PCIE to SATA, PCIE to M.2, SATA to M.2 and other multiple interfaces, greatly facilitating the compatibility and use of various interface channels.
[0035] The application comprises three interfaces, a PCIE interface circuit J4, an M.2 interface circuit J3 and a SATA interface circuit J1, wherein the PCIE interface circuit is an input interface, the M.2 interface circuit is an output interface, and the SATA interface circuit can be used as an input or an output, that is, the SATA interface circuit comprises a SATA input interface circuit and a SATA output interface circuit; the SATA interface circuit comprises a SATA signal socket, the No. 4 pin of the SATA signal socket J1A is defined as a detection signal SDET, is high when no load is inserted, and is low when a load is inserted; the M.2 interface circuit comprises an M.2 socket, the No. 69 pin of the M.2 socket is defined as a detection signal MDET, is high when no load is inserted or a load of a PCIE channel is inserted, and is low when a load of a SATA channel is inserted;
[0036] When the input is the SATA interface circuit J1, the M.2 interface circuit J3 (SATA channel) is output, and the SDET and MDET signals are both pulled low to low level, at this time, the OE signal is high level, the signal switching switch circuit U3 outputs is closed, and the SATA signal is directly output from the SATA interface circuit J1 to the M.2 interface circuit J3.
[0037] When the input is the PCIE interface J4: ① if the M.2 interface circuit inserts a load of a PCIE channel, the detection signal MDET is high level, the SEL is also high level, the OE is low level, the PCIE signal is output to the M.2 interface circuit J3 through the signal switching switch circuit U3; ② if the M.2 interface circuit inserts a load of a SATA channel, the detection signal MDET is low level, the SEL is also low level, the OE is low level, and the PCIE signal is converted into a SATA signal through the signal conversion circuit U5, and the SATA signal is output to the M.2 interface circuit J3 through the signal switching switch circuit U3; ③ when the SATA interface circuit J1 is connected to a load, the detection signal SDET is low level, the SEL is also pulled low level, and the OE is also low level, at this time, the PCIE signal is converted into a SATA signal through the signal conversion circuit U5, and the SATA signal is output to the SATA interface circuit J1 through the signal switching switch circuit U3, so that automatic identification and output are realized.
[0038] The above only describes preferred embodiments of the utility model, and does not limit the patent range of the utility model, and any equivalent structural transformation made by using the utility model specification and the drawings contents, or direct / indirect application in other related technical fields is included in the patent protection range of the utility model.
Claims
1. An automatic identification and conversion circuit for multi-interface signals, characterized by The main control circuit board is provided with a power supply circuit, a signal detection circuit, an M.2 interface circuit, a PCIE interface circuit, a signal switching switch circuit, a signal conversion circuit and a SATA interface circuit; the power supply circuit is electrically connected with the PCIE interface circuit and the SATA interface circuit; the signal conversion circuit and the SATA interface circuit are electrically connected with the signal switching switch circuit, and the signal detection circuit is in communication connection with the M.2 interface circuit, the SATA interface circuit and the signal switching switch circuit.
2. The automatic identification and translation circuit for multiple interface signals of claim 1, wherein, The signal switching switch circuit comprises a logic chip, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; the first resistor and the second resistor are connected in series, one end of which is electrically connected with the power supply circuit, and the other end is electrically connected with the sixteenth pin of the logic chip; one end of the third resistor is electrically connected with the sixteenth pin of the logic chip, and the other end is electrically connected with the SATA interface circuit; the tenth pin, the eleventh pin, the twelfth pin and the thirteenth pin of the logic chip are electrically connected with the M.2 interface circuit; one end of the first capacitor is electrically connected with the seventh pin of the logic chip, and the other end is electrically connected with the PCIE interface circuit; one end of the second capacitor is electrically connected with the fifth pin of the logic chip, and the other end is electrically connected with the PCIE interface circuit; one end of the third capacitor is electrically connected with the seventh pin of the logic chip, and the other end is electrically connected with the PCIE interface circuit; the first pin and the third pin of the logic chip are electrically connected with the PCIE interface circuit; one end of the third capacitor is electrically connected with the sixth pin of the logic chip, and the other end is electrically connected with the signal conversion circuit; one end of the fourth capacitor is electrically connected with the fourth pin of the logic chip, and the other end is electrically connected with the signal conversion circuit; the second pin and the fifteenth pin of the logic chip are electrically connected with the signal conversion circuit; the ninth pin and the sixteenth pin of the logic chip are electrically connected with the signal detection circuit; and the eighth pin of the logic chip is grounded.
3. The automatic identification and translation circuit for multiple interface signals of claim 2, wherein, The signal conversion circuit comprises a signal conversion chip and a crystal oscillator; the sixth pin, the thirty-eighth pin, the forty-first pin, the forty-second pin and the forty-eighth pin of the signal conversion chip are electrically connected with the power supply circuit; the first pin of the crystal oscillator is electrically connected with the fortieth pin of the signal conversion chip; the second pin and the fourth pin of the crystal oscillator are connected in series; the fourth pin of the crystal oscillator is grounded; the third pin of the crystal oscillator is electrically connected with the thirty-ninth pin of the signal conversion chip; the thirteenth pin, the fourteenth pin, the fifteenth pin, the seventeenth pin, the eighteenth pin, the twentieth pin and the twenty-first pin of the signal conversion chip are electrically connected with the PCIE interface circuit; and the twelfth pin and the thirteenth pin of the signal conversion chip are electrically connected with the M.2 interface circuit.
4. The automatic identification and translation circuit for multiple interface signals of claim 3, wherein, The signal detection circuit includes a first MOS tube, a second MOS tube, a fourth resistor and a fifth resistor; one end of the fourth resistor is electrically connected with the power supply circuit, and the other end is electrically connected with the source electrode of the first MOS tube; the gate electrode of the first MOS tube is electrically connected with the M.2 interface circuit, the drain electrode of the first MOS tube is electrically connected with the source electrode of the second MOS tube, and the gate electrode of the second MOS tube is electrically connected with the sixteenth pin of the logic chip and the SATA interface circuit; one end of the fifth resistor is electrically connected with the drain electrode of the second MOS tube, and the other end is grounded; and the drain electrode of the second MOS tube is electrically connected with the ninth pin of the logic chip.
5. The automatic identification and translation circuit for multiple interface signals of claim 4, wherein, The model of the logic chip includes but is not limited to HEF4008B.
6. The automatic identification and translation of multi-interface signals of claim 1, wherein, The power supply circuit includes a first power supply, a second power supply and a third power supply, and the first power supply, the second power supply and the third power supply are electrically connected with the PCIE interface circuit and the SATA interface circuit.