Display control chip and electronic equipment
By optimizing the HDMI transceiver multiplexing circuit and the I-shaped layout, the problems of excessive size and limited functionality of traditional display control chips are solved, enabling multi-level cascading and reversible insertion display control chip designs, thus improving signal processing efficiency.
Patent Information
- Application Number
- CN202422611604.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-10-28
AI Technical Summary
Traditional display control chips have large receiving and transmitting modules that occupy too much space and have limited functionality, making them unable to meet the requirements of multi-level cascading and reversible insertion in display cabinets.
It adopts an HDMI transceiver multiplexing circuit design, configured as HDMI TX or RX, supports low-speed mode and high-speed readback mode, and optimizes module connection through I-shaped layout and multi-layer metal wiring to reduce area occupation.
It realizes the multi-level cascading and reversible insertion functions of display control chips, while optimizing area utilization and improving signal processing efficiency.
Smart Images
Figure CN223526856U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to display technical field, especially display control chip and electronic equipment. BACKGROUND
[0002] With the rapid development of LED display technology, the market demand for display control chip is also higher, in order to display the multistage cascade of box body is convenient, therefore there will be the network interface of display box body support multistage cascade, and the demand of positive and negative insertion and parameter gray scale.
[0003] And the traditional display control chip usually only supports the single function of receiving or sending data, cannot satisfy the demand of the network interface multistage cascade of display box body, and positive and negative insertion and parameter gray scale, and the receiving and transmitting module in the traditional display control chip occupies the corresponding board independently, and the area is too large, so that the size and other performance parameters of the chip are limited. UTILITY MODEL CONTENT
[0004] In view of the above problem, the utility model discloses a display control chip and electronic equipment, thereby solve the shortcoming that the traditional receiving and transmitting module occupies the area in the chip is too large and the function is single, through the transceiving multiplexing circuit of HDMI, can be configured as HDMI TX or RX, and simultaneously support low speed mode and high speed readback mode.
[0005] According to an aspect of the utility model, a display control chip and electronic equipment are provided, which comprise: at least one processing unit for processing and displaying image signals; a transceiving multiplexing channel for receiving and transmitting signals, the transceiving multiplexing channel comprising a receiving end equalization module and an output channel, the receiving end equalization module receiving and processing signals from sensors and performing corresponding signal conversion; the output channel for converting digital signals into analog signals and outputting through an interface; a transceiving multiplexing channel control module for controlling the receiving and transmitting operations of the transceiving multiplexing channel, wherein the output channel is arranged in a first layer of metal in an I-shaped form, the receiving end equalization module is located in the groove of the I-shaped form of the output channel, and the output channel and the receiving end equalization module multiplex the pad layout in the display control chip.
[0006] Preferably, the transceiving multiplexing channel further comprises a clock data recovery module for recovering a clock signal from the received data signal and providing it to the receiving end equalization module and the output channel.
[0007] Preferably, the connection layout of the signal lines between the logic unit of the clock data recovery module and the internal modules in the clock data recovery module is realized through the third layer of metal and the fourth layer of metal.
[0008] Preferably, the logic unit of the clock data recovery module is realized by the first layer metal and the second layer metal wiring, and the connection wiring between the internal modules of the clock data recovery module is realized by the third layer and the fourth layer metal.
[0009] Preferably, the clock data recovery module further comprises a phase-locked loop module for providing corresponding clock sampling signals through a plurality of clock signal sampling lines.
[0010] Preferably, the sequence of the clock sampling signals received by the clock data recovery module corresponds to the sequence of the clock sampling lines provided by the phase-locked loop module.
[0011] Preferably, the clock sampling lines are connected by the fifth layer metal wiring.
[0012] Preferably, the clock sampling lines and the fifth layer metal only have a cross intersection.
[0013] Preferably, the clock sampling lines are in the third layer metal wiring and / or the fourth layer metal wiring.
[0014] According to another aspect of the present application, an electronic device is also provided, comprising a display panel, and a display control chip as described in any of the above, for providing driving and / or touch control signals to the display panel.
[0015] In the novel layout mode provided by the present application, the traditional receiving and transmitting module has the advantages of small area occupation and single function, and through the transceiving multiplexing circuit of HDMI, the HDMI TX or RX can be configured, and the low-speed mode and the high-speed read-back mode are simultaneously supported. BRIEF DESCRIPTION OF DRAWINGS
[0016] The above and other objects, features and advantages of the present application will become more apparent from the following description of the preferred embodiments of the present application taken with reference to the accompanying drawings, in which:
[0017] Figure 1 A display control chip schematic block diagram according to the first embodiment of the present application is shown.
[0018] Figure 2 A schematic block diagram of a transceiving multiplexing channel in a display control chip according to the second embodiment of the present application is shown.
[0019] Figure 3 A display control chip metal layer schematic diagram according to the third embodiment of the present application is shown.
[0020] Figure 4 A display control chip corresponding metal wiring schematic diagram according to the fourth embodiment of the present application is shown.
[0021] Figure 5 A display control chip corresponding metal wiring schematic diagram according to the fifth embodiment of the utility model is shown.
[0022] Figure 6 A phase-locked loop module schematic diagram in a display control chip according to the sixth embodiment of the utility model is shown.
[0023] Figure 7 A clock signal wiring schematic diagram of a phase-locked loop module in a display control chip according to the seventh embodiment of the utility model is shown. DETAILED DESCRIPTION
[0024] Various embodiments of the utility model will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements or modules are denoted by the same or similar reference numerals. For the sake of clarity, each part in the drawings is not drawn to scale.
[0025] It should be understood that in the following description, "circuitry" can include a single or multiple combinations of hardware circuitry, programmable circuitry, state machine circuitry, and / or elements that can store instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that there are no intervening elements.
[0026] Meanwhile, some terms are used in the patent specification and claims to refer to certain components. Those skilled in the art should understand that hardware manufacturers may use different names to refer to the same component. The patent specification and claims do not distinguish components by name, but by functional differences.
[0027] In this application, the term "semiconductor structure" refers to the entire semiconductor structure formed in each step of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the utility model are described below, such as the structure, materials, dimensions, processing and techniques of the device, in order to more clearly understand the utility model. However, as those skilled in the art can understand, the utility model can be implemented without these specific details.
[0028] Moreover, in this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.
[0029] Figure 1 A display control chip according to the first embodiment of the present application is shown in a schematic block diagram, Figure 2 A schematic block diagram of a transceiver multiplexing channel in a display control chip according to the second embodiment of the present application is shown.
[0030] As Figure 1 and 2 shown, the display control chip of the first embodiment of the present application, for example, includes a plurality of chip-internal processor cores or certain parallel processing units CORE1-CORE3, a transceiver multiplexing channel control module TRX_CHC, and a plurality of transceiver multiplexing channels TRX_CH0.
[0031] The plurality of processor cores or certain parallel processing units CORE1-CORE3 are used for processing and displaying image data, and they are capable of processing different tasks or data streams simultaneously, thereby improving the overall processing speed and efficiency. Such parallel processing capability is particularly important in applications requiring high-performance image processing and video decoding. However, it should be noted that not all display control chips will contain multiple processor cores. In some simple application scenarios, a display control chip can only need one or a few processing units to complete the image processing and display tasks.
[0032] The transceiver multiplexing channel control module TRX_CHC is used to control and manage the receiving and transmitting operations of one or more radio frequency channels, for example, including frequency synthesis, signal modulation and demodulation, power control, etc.
[0033] The plurality of transceiver multiplexing channels TRX_CH0, as specific radio frequency channels, are responsible for receiving and transmitting signals on the channels. This includes receiving signals from other devices, demodulating the signals to extract useful information, and modulating local signals for transmission.
[0034] The application provides a display control chip with a transceiver multiplexing channel control module TRX_CHC and multiple transceiver multiplexing channels TRX_CH0, is designed to support the HDMI TX / RX half-duplex mode, can be configured as the HDMI TX or RX, and simultaneously supports the low-speed mode and the high-speed readback mode. The display box loaded with the display control chip can realize multi-stage cascading and forward and reverse insertion.
[0035] The transceiver multiplexing channel TRX_CH0 in the display control chip, for example, includes a receiving end equalization module 102 and an output channel TX_CH0. When the layout is arranged, the receiving end equalization module 102 and the output channel TX_CH0 are combined and arranged in a nested manner, which takes into account the positions of the two modules connected to the pad connection lines and reasonably compresses the layout area. In an embodiment, the combination of the two modules is repeated 4 times in a single transceiver multiplexing circuit and 8 times in the display control chip.
[0036] Specifically, the receiving end equalization module 102 is used to receive and process signals from sensors or other analog signal sources, and perform corresponding signal conversion, such as converting analog signals to digital signals or converting digital signals to analog signals. The receiving end equalization module can also be used to improve the quality of the received signal. In high-speed data transmission, the signal may be distorted due to channel characteristics such as attenuation, noise, etc. The receiving end equalization module compensates for these distortions by adjusting the amplitude, phase, or frequency response of the signal, thereby ensuring that the received signal can be correctly decoded.
[0037] The output channel TX_CH0 is a channel in the transmitter (TX). In the display control chip, the output channel TX_CH0 is used to convert digital signals to analog signals and send them to external devices (such as displays) through some interface (such as HDMI, DisplayPort, etc.).
[0038] In an embodiment, the output channel TX_CH0 of the application is made into an I-shaped type, and the receiving end equalization module is located at the groove of the I-shaped output channel TX_CH0, and is connected by the first layer of metal to completely match, so that the wiring of the two modules does not overlap, but can reuse the wiring introduced from the pad, reducing interference with the lower device.
[0039] It should be noted that the number of the above modules can be adjusted according to actual needs, and is not limited to multiple, but can also be one.
[0040] The transceiver multiplexing channel TRX_CH0 further comprises a clock data recovery module 103 (CDR, Clock and Data Recovery) for recovering a clock signal from the received data and re-timing (or resampling) the data using the recovered clock signal to ensure the correctness and synchronization of the data. The clock data recovery module 103 is composed of a phase discriminator array digital filter and the like.
[0041] Figure 3 A display control chip metal layer schematic diagram according to a third embodiment of the utility model is shown, Figure 4 A display control chip corresponding metal wiring schematic diagram according to a fourth embodiment of the utility model is shown.
[0042] In the wiring of the clock data recovery module, the most complex flip-flop circuit is found out, the layout of the flip-flop is redrawn according to the requirements of simulation, the clock control line is processed according to the requirements of differential input, and the parasitic consistency is ensured. And the layout of other simple logic units is drawn according to the flip-flop as the standard.
[0043] As Figure 3 and 4 shown, the display control chip metal layer comprises metal wiring layers M1-M5 from low to high, for example. When there is a read-write speed requirement for the transceiver multiplexing channel, the metal wiring layers M3 and M4 are only used for the connection of important signal lines, such as the connection signal line 1031 between the internal modules in the clock data recovery module 103.
[0044] Specifically, the logic area (i.e. the part that implements specific logic functions) of the clock data recovery module 103 and the logic function wiring 1032 of the clock data recovery module 103 are all limited to the M2 metal wiring layer. The connection signal line 1031 between the internal modules in the clock data recovery module 103 is wired in the M3 and M4 metal layers, and the higher-level metal wiring layers (such as M3 and M4) are used to connect different modules. Since these levels are usually located above the lower levels, they have less crosstalk and better signal integrity, and are suitable for long-distance or high-bandwidth signal transmission. In addition, using higher-level metal wiring layers for inter-module connection also helps to reduce the mutual influence between underlying units and wires, and improves the flexibility of the overall layout.
[0045] Figure 5 A display control chip corresponding metal wiring schematic diagram according to a fifth embodiment of the utility model is shown.
[0046] In Figure 5As can be seen, when there is no read-write speed requirement for the transceiver multiplexing channel, the wiring in the transceiver multiplexing channel, including the connection signal lines 1031 between internal modules and the logic function wiring 1032, can be largely used in the metal layers M3 and M4.
[0047] Figure 6 A phase-locked loop module schematic diagram in a display control chip according to the sixth embodiment of the utility model is shown, Figure 7 A clock signal wiring schematic diagram of a phase-locked loop module in a display control chip according to the seventh embodiment of the utility model is shown (it should be understood that, Figure 7 The color wires in the CLK box are all clock sampling lines CLK).
[0048] As Figure 6 and 7 The voltage-controlled oscillator in the transceiver multiplexing channel control module TRX_CHC is applied in the phase-locked loop module 101 to generate a stable clock signal and provide it to other corresponding modules, including the processing unit and the plurality of transceiver multiplexing channels TRX_CH0.
[0049] The clock sampling line CLK of the clock data recovery module 103 in the transceiver multiplexing channel TRX_CH0 comes from the phase-locked loop module 101, so the CLK line sequence given by the phase-locked loop module 101 is first determined to adjust the sequence of receiving CLK inside the clock data recovery module to one-to-one correspondence to reduce unnecessary crosstalk. The clock line CLK has relatively high requirements on speed and environment, so the clock sampling line CLK of the above-mentioned clock data recovery module 103 is connected using the fifth layer of metal, and when encountering unavoidable wiring, a layer reduction process is adopted and only local cross-over is allowed.
[0050] In the novel layout method of the utility model, the shortcomings of the traditional receiving and transmitting module in the chip, such as large area occupation and single function, are solved. Through the transceiver multiplexing circuit of HDMI, the HDMI TX or RX can be configured, and the low-speed mode and high-speed read-back mode are simultaneously supported.
[0051] It should be understood by those of ordinary skill in the art that the words "during," "when," and "while" as used herein in connection with circuit operation are not to be interpreted in a strict chronological sense, but rather are meant to encompass small, reasonable, one or more delays between the initiation of an action and the resulting reaction initiated by the action, such as various transmission delays, etc. The use of the words "about" or "substantially" herein means that an element has a parameter that is intended to be close to the stated value or position. However, as is known in the art, there are always minor deviations that make the value or position difficult to be strictly the stated value. When used in connection with signal states, the actual voltage value or logic state of a signal (e.g., "1" or "0") depends on whether positive or negative logic is used.
[0052] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details of the application, nor limit the application to the specific embodiments. Obviously, many modifications and variations are possible in light of the above teachings. The description of the embodiments was chosen and described in order to explain the principles of the application and its practical application to enable others skilled in the art to best utilize the application with various modifications as are suited to the particular use contemplated. It is intended that the scope of the application be defined by the claims and their equivalents.
Claims
1. A display control chip, characterized by comprising: The display control chip comprises: at least one processing unit for processing and displaying image signals; a transceiver multiplexing channel for receiving and transmitting signals, the transceiver multiplexing channel comprising a receiving end equalization module and an output channel, the receiving end equalization module receiving and processing signals from sensors and performing corresponding signal conversion; the output channel for converting digital signals into analog signals and outputting through an interface; a transceiver multiplexing channel control module for controlling the receiving and transmitting operations of the transceiver multiplexing channel, wherein the output channel is arranged in a first layer of metal in an I-shaped form, the receiving end equalization module is located in the groove of the I-shaped output channel, and the output channel and the receiving end equalization module multiplex the pad wiring in the display control chip.
2. The display control chip according to claim 1, characterized in that, wherein the transceiver multiplexing channel further comprises a clock data recovery module for recovering a clock signal from the received data signal and providing it to the receiving end equalization module and the output channel.
3. The display control chip according to claim 2, characterized in that, wherein the connection wiring of the signal lines between the logic unit of the clock data recovery module and the internal modules of the clock data recovery module is realized by the third layer of metal and the fourth layer of metal.
4. The display control chip according to claim 2, wherein The logic unit of the clock data recovery module is realized by the first layer of metal and the second layer of metal wiring, and the connection wiring of the signal lines between the internal modules of the clock data recovery module is realized by the third layer and the fourth layer of metal.
5. The display control chip according to claim 3 or 4, characterized in that, It further comprises a phase-locked loop module for providing corresponding clock sampling signals through a plurality of clock signal sampling lines.
6. The display control chip according to claim 5, wherein, The sequence in which the clock sampling signals are received by the clock data recovery module corresponds to the sequence of clock sampling lines provided by the phase-locked loop module.
7. The display control chip according to claim 6, characterized in that, The clock sampling lines are connected by the fifth layer of metal wiring.
8. The display control chip according to claim 7, characterized in that, The clock sampling lines and the fifth layer of metal wiring only have a cross intersection.
9. The display control chip of claim 7, wherein, The clock sampling lines are in the third layer of metal wiring and / or the fourth layer of metal wiring.
10. An electronic device, comprising: The display control chip comprises: a display panel; and the display control chip according to any one of claims 1-9, for providing driving and / or touch signals to the display panel.