Dynamic random access memory

Abstract

The embodiment of the utility model provides a dynamic random access memory. The dynamic random access memory comprises a column decoding circuit, a control circuit, a sensing amplification circuit, a bit line and a total data line, the output end of the column decoding circuit is connected with the first control end of the control circuit, and the second control end of the control circuit receives a control signal of the total data line. The four ends of the control circuit are connected with the two ends of the bit line, the two ends of the total data line and the input end of the sensing amplification circuit respectively, in the read operation process, when a column selection signal generated by the column decoding circuit is a column conduction signal and the sensing amplification circuit does not enter a working state, the control circuit conducts the bit line and the sensing amplification circuit through the total data line, and the bit line is read. When the column selection signal generated by the column decoding circuit is a column conduction signal and the sensing amplification circuit enters a working state, the control circuit disconnects the bit line and the total data line. According to the dynamic random access memory, the power consumption can be reduced while the normal work is ensured.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a dynamic random access memory. BACKGROUND

[0002] In the process of the read operation of the dynamic random access memory, when the column selection signal is the column conduction signal, the bit line is connected to the input end of the sense amplifier through the total data line, so that the data of the memory cell can be transmitted from the bit line to the sense amplifier, which is called charge sharing, and when the sense amplification circuit control signal is the sense amplification circuit working signal, the sense amplification circuit is connected, so that the sense amplification circuit can sense the voltage difference of the total data line.

[0003] In the process of charge sharing, there is no additional driving, and the voltage difference of the total data line depends on the time difference between the time when the column selection signal jumps to the column conduction signal and the time when the sense amplification circuit control signal jumps to the sense amplification circuit working signal. However, in the read operation and the write operation, the time length during which the column selection signal maintains the column conduction signal is usually the same, which leads to unnecessary energy consumption. CONTENT OF THE UTILITY MODEL

[0004] The embodiment of the present disclosure provides a dynamic random access memory, which can reduce energy consumption while ensuring normal operation.

[0005] The present disclosure provides a dynamic random access memory, comprising a column decoding circuit, a control circuit, a sense amplification circuit, a bit line and a total data line, the output end of the column decoding circuit is connected to the first control end of the control circuit, the second control end of the control circuit is used for receiving a total data line control signal, the first end of the control circuit is connected to the bit line, the second end of the control circuit is connected to one end of the total data line away from the sense amplification circuit, the third end of the control circuit is connected to one end of the total data line close to the sense amplification circuit, and the fourth end of the control circuit is connected to the input end of the sense amplification circuit.

[0006] The column decoding circuit is configured to generate a column selection signal, and the column selection signal comprises a column conduction signal and a column off signal. The control circuit is configured to, in the process of the read operation, connect the bit line to the sense amplifier through the total data line when the column selection signal is the column conduction signal and the sense amplification circuit is not in the working state, and disconnect the connection between the bit line and the total data line when the column selection signal is the column conduction signal and the sense amplification circuit is in the working state.

[0007] In some embodiments of the present disclosure, the control circuit comprises a signal generation module, a first control module and a second control module, a first input terminal of the signal generation module is connected to an output terminal of the column decoding circuit, a second input terminal of the signal generation module is connected to a control terminal of the sense amplifier circuit to receive a sense amplifier circuit control signal, the sense amplifier circuit control signal comprises a sense amplifier circuit working signal and a sense amplifier circuit working stop signal.

[0008] An output terminal of the signal generation module is connected to a control terminal of the first control module, the first control module is connected between the bit line and the total data line, the second control module is connected between the total data line and an input terminal of the sense amplifier circuit, and a control terminal of the second control module is used to receive the total data line control signal, the total data line control signal comprises a total data line turn-on signal and a total data line turn-off signal.

[0009] The signal generation module is configured to, during the read operation, generate a bit line turn-off signal according to the sense amplifier circuit working signal and the column turn-on signal, so that the first control module disconnects the connection between the bit line and the total data line.

[0010] In some embodiments of the present disclosure, the signal generation module comprises a first NAND gate and a first inverter, a first input terminal of the first NAND gate is connected to an output terminal of the column decoding circuit, a second input terminal of the first NAND gate is connected to a control terminal of the sense amplifier circuit, and an output terminal of the first NAND gate is connected to a control terminal of the first control module through the first inverter.

[0011] In some embodiments of the present disclosure, the control circuit comprises a signal generation module, a first control module and a second control module, a first input terminal of the signal generation module is connected to an output terminal of the column decoding circuit, a second input terminal of the signal generation module is connected to a control terminal of the second control module to receive a total data line control signal, the total data line control signal comprises a total data line turn-on signal and a total data line turn-off signal, an output terminal of the signal generation module is connected to a control terminal of the first control module, the first control module is connected between the bit line and the total data line, and the second control module is connected between the total data line and an input terminal of the sense amplifier circuit.

[0012] The signal generation module is configured to, during the read operation, generate a bit line turn-off signal according to the column turn-on signal and the total data line turn-off signal, so that the first control module disconnects the connection between the bit line and the total data line.

[0013] In some embodiments of the present disclosure, the signal generation module comprises a second NAND gate, a second inverter and a third inverter, a first input end of the second NAND gate is connected to an output end of the column decoding circuit, a control end of the second control module is connected to a second input end of the second NAND gate through the second inverter, and an output end of the second NAND gate is connected to a control end of the first control module through the third inverter.

[0014] In some embodiments of the present disclosure, the first control module comprises a first transistor, a second transistor, a third transistor and a fourth transistor, the bit line comprises a positive bit line and a negative bit line, the total data line comprises a positive total data line and a negative total data line, and the dynamic random access memory further comprises a positive local data line and a negative local data line.

[0015] The positive bit line is connected to the positive local data line through the first transistor, the positive local data line is connected to the positive total data line through the second transistor, the negative bit line is connected to the negative local data line through the third transistor, and the negative local data line is connected to the negative total data line through the fourth transistor, a control end of the first transistor and a control end of the third transistor are connected to an output end of the signal generation module, a control end of the second transistor and a control end of the fourth transistor are used to receive a local data line control signal, and the local data line control signal comprises a local data line turn-on signal and a local data line turn-off signal.

[0016] In some embodiments of the present disclosure, the second control module comprises a fifth transistor and a sixth transistor, the total data line comprises a positive total data line and a negative total data line, the positive total data line is connected to a positive input end of the sense amplifier circuit through the fifth transistor, the negative total data line is connected to a negative input end of the sense amplifier circuit through the sixth transistor, and a control end of the fifth transistor and a control end of the sixth transistor are used to receive the total data line control signal.

[0017] In some embodiments of the present disclosure, the sense amplifier circuit comprises a sense amplification module and a sense control module, a positive input end of the sense amplification module is connected to the positive input end of the sense amplifier circuit, a negative input end of the sense amplification module is connected to the negative input end of the sense amplifier circuit, a power supply end of the sense amplification module is connected to an external power supply, a ground end of the sense amplification module is grounded through the sense control module, and a control end of the sense control module is used to receive a sense amplifier circuit control signal.

[0018] In some embodiments of the present disclosure, the sense amplification module comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourth inverter.

[0019] The positive input end of the sense amplification circuit is connected with the second end of the seventh transistor, the first end of the ninth transistor, the second end of the tenth transistor, the second end of the eleventh transistor, the control end of the twelfth transistor and the control end of the thirteenth transistor, the first end of the seventh transistor and the first end of the eighth transistor are connected with the external power supply, the second end of the eighth transistor is connected with the second end of the ninth transistor, the control end of the tenth transistor, the control end of the eleventh transistor, the second end of the twelfth transistor, the second end of the thirteenth transistor, the input end of the fourth inverter and the negative input end of the sense amplification circuit, and the control end of the seventh transistor is connected with the control end of the eighth transistor and the control end of the ninth transistor.

[0020] The first end of the tenth transistor and the first end of the twelfth transistor are connected with the external power supply, the first end of the eleventh transistor and the first end of the thirteenth transistor are connected with the output end of the sensing control module, the input end of the sensing control module is used for receiving the sense amplification circuit control signal, and the output end of the fourth inverter is connected with the output end of the sense amplification circuit.

[0021] In some embodiments of the present disclosure, the sensing control module comprises a fourteenth transistor and a fifth inverter, the second end of the fourteenth transistor is connected with the ground end of the sense amplification module, the first end of the fourteenth transistor is grounded, the control end of the fourteenth transistor is connected with the output end of the fifth inverter, and the input end of the fifth inverter is used for receiving the sense amplification circuit control signal.

[0022] In the technical scheme of the embodiments of the present disclosure, the dynamic random access memory comprises a column decoding circuit, a control circuit, a sense amplification circuit, a bit line and a total data line, the output end of the column decoding circuit is connected with the first control end of the control circuit, the second control end of the control circuit is used for receiving a total data line control signal, the first end of the control circuit is connected with the bit line, the second end of the control circuit is connected with one end of the total data line away from the sense amplification circuit, the third end of the control circuit is connected with one end of the total data line close to the sense amplification circuit, the fourth end of the control circuit is connected with the input end of the sense amplification circuit, in the process of the read operation, when the column selection signal generated by the column decoding circuit is a column conduction signal and the sense amplification circuit does not enter the working state, the control circuit conducts the bit line to the sense amplification circuit through the total data line, and when the column selection signal generated by the column decoding circuit is a column conduction signal and the sense amplification circuit enters the working state, the control circuit disconnects the connection between the bit line and the total data line, so that in the process of the read operation, the bit line and the total data line do not need to be conducted when the sense amplification circuit normally works, and the power consumption can be reduced while ensuring normal work. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0024] Figure 1 A structural schematic diagram of a dynamic random access memory provided by an embodiment of the present application.

[0025] Figure 2 A timing diagram of a dynamic random access memory provided by an embodiment of the present application.

[0026] Figure 3 A structural schematic diagram of another dynamic random access memory provided by an embodiment of the present application.

[0027] Figure 4 A circuit schematic diagram of a dynamic random access memory provided by an embodiment of the present application.

[0028] Figure 5 A circuit schematic diagram of another dynamic random access memory provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings to make a clear and complete description of the technical solutions of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative effort also belong to the protection scope of the present application.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" together shall mean that the parts are joined directly or through one or more intermediate parts.

[0031] Reference to“an embodiment” or“the embodiment” in this disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase“an embodiment” or“in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment. It is explicitly contemplated that embodiments described in this disclosure can be combined with each other in their individual aspects.

[0032] In addition, the terms“first”,“second”, and the like in the description and claims of this disclosure or the above drawings are used to distinguish different objects, and are not used to describe a particular order, and can explicitly or implicitly include one or more of the features.

[0033] The term“and / or” in this disclosure is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the existence of A, the existence of A and B, and the existence of B. In addition, the character“ / ” herein generally represents an“or” relationship between the front and rear associated objects.

[0034] In the description of this disclosure, unless otherwise specified, the meanings of“a plurality of” and“at least two” are two or more (including two), and similarly,“a plurality of groups” and“at least two groups” mean two or more groups (including two groups).

[0035] In order for those skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings.

[0036] Figure 1 A structure diagram of a dynamic random memory provided by an embodiment of the present disclosure is shown in FIG. 1. Figure 1 As shown in FIG. 1, the dynamic random memory 100 includes a column decoding circuit 110, a control circuit 120, a sense amplification circuit 130, a bit line BL, and a total data line MIO.

[0037] The output end of the column decoding circuit 110 is connected to the first control end of the control circuit 120, the second control end of the control circuit 120 is used to receive a total data line control signal MIOCS, the first end of the control circuit 120 is connected to the bit line BL, the second end of the control circuit 120 is connected to one end of the total data line MIO away from the sense amplification circuit 130, the third end of the control circuit 120 is connected to one end of the total data line MIO close to the sense amplification circuit 130, and the fourth end of the control circuit 120 is connected to the input end of the sense amplification circuit 130.

[0038] The column decoding circuit 110 is configured to generate a column select signal CSL, which includes a column on signal and a column off signal. The control circuit 120 is configured to, during a read operation, connect the bit line BL to the sensing amplifier circuit 130 via the total data line MIO when the column select signal CSL is on and the sensing amplifier circuit 130 is not in operation; and disconnect the connection between the bit line BL and the total data line MIO when the column select signal CSL is on and the sensing amplifier circuit 130 is in operation.

[0039] For example, the column turn-on signal is a high-level signal and the column turn-off signal is a low-level signal. In other embodiments, the column turn-on signal is a low-level signal and the column turn-off signal is a high-level signal. This disclosure does not impose specific limitations on this. This disclosure uses the example of a high-level column turn-on signal and a low-level column turn-off signal to illustrate the dynamic random access memory 100.

[0040] like Figure 1 As shown, the bit line BL includes a positive bit line BLT and a negative bit line BLB, and the total data line MIO includes a positive total data line MIOT and a negative total data line MIOB. The positive first terminal of the control circuit 120 is connected to the positive bit line BLT, the negative first terminal of the control circuit 120 is connected to the negative bit line BLB, the positive second terminal of the control circuit 120 is connected to the end of the positive total data line MIOT away from the sensing amplifier circuit 130, the negative second terminal of the control circuit 120 is connected to the end of the negative total data line MIOB away from the sensing amplifier circuit 130, the positive third terminal of the control circuit 120 is connected to the end of the positive total data line MIOT close to the sensing amplifier circuit 130, the negative third terminal of the control circuit 120 is connected to the end of the negative total data line MIOB close to the sensing amplifier circuit 130, the positive fourth terminal of the control circuit 120 is connected to the positive input terminal of the sensing amplifier circuit 130, and the negative fourth terminal of the control circuit 120 is connected to the negative input terminal of the sensing amplifier circuit 130.

[0041] The first control terminal of the control circuit 120 is connected to the output terminal of the column decoding circuit 110 to receive the column selection signal CSL generated by the column decoding circuit 110. The third control terminal of the control circuit 120 is connected to the control terminal of the sensing amplifier circuit 130 to receive the sensing amplifier circuit control signal SACS. The sensing amplifier circuit control signal SACS includes a sensing amplifier circuit operating signal and a sensing amplifier circuit operating stop signal. For example, the sensing amplifier circuit operating signal is a low-level signal and the sensing amplifier circuit operating stop signal is a high-level signal. In other embodiments, the sensing amplifier circuit operating signal is a high-level signal and the sensing amplifier circuit operating stop signal is a low-level signal. This disclosure does not impose specific limitations on this. This disclosure uses the example of a low-level sensing amplifier circuit operating signal and a high-level sensing amplifier circuit operating stop signal to illustrate the dynamic random access memory 100.

[0042] The control circuit 120 can generate a bit line control signal BLCS according to the received column selection signal CSL and the sense amplifier control signal SACS, wherein the bit line control signal BLCS includes a bit line turn-on signal and a bit line turn-off signal, for example, the bit line turn-on signal is a high-level signal and the bit line turn-off signal is a low-level signal. In other embodiments, the bit line turn-on signal is a low-level signal and the bit line turn-off signal is a high-level signal, which is not specifically limited in the present disclosure, and the embodiments of the present disclosure are exemplarily described with the bit line turn-on signal as a high-level signal and the bit line turn-off signal as a low-level signal.

[0043] The control circuit 120 can control the connection and disconnection between the positive bit line BLT and the positive total data line MIOT and the connection and disconnection between the negative bit line BLB and the negative total data line MIOB according to the generated bit line control signal BLCS.

[0044] Specifically, when the column selection signal CSL is a high-level signal and the sense amplifier control signal SACS is a high-level signal, the bit line control signal BLCS is a high-level signal, and the control circuit 120 turns on the positive bit line BLT and the positive total data line MIOT according to the high-level signal, and turns on the negative bit line BLB and the negative total data line MIOB. When the column selection signal CSL is a high-level signal and the sense amplifier control signal SACS is a low-level signal, the bit line control signal BLCS is a low-level signal, and the control circuit 120 disconnects the connection between the positive bit line BLT and the positive total data line MIOT and the connection between the negative bit line BLB and the negative total data line MIOB according to the low-level signal.

[0045] The second control end of the control circuit 120 receives a total data line control signal MIOCS, wherein the total data line control signal MIOCS includes a total data line turn-on signal and a total data line turn-off signal, for example, the total data line turn-on signal is a low-level signal and the total data line turn-off signal is a high-level signal. In other embodiments, the total data line turn-on signal is a high-level signal and the total data line turn-off signal is a low-level signal, which is not specifically limited in the present disclosure, and the embodiments of the present disclosure are exemplarily described with the total data line turn-on signal as a low-level signal and the total data line turn-off signal as a high-level signal.

[0046] The control circuit 120 can control the connection and disconnection between the positive total data line MIOT and the positive input end of the sense amplifier circuit 130 and the connection and disconnection between the negative total data line MIOB and the negative input end of the sense amplifier circuit 130 according to the received total data line control signal MIOCS.

[0047] Specifically, when the column selection signal CSL is high and the sensing amplifier circuit control signal SACS is high, the total data line control signal MIOCS is low. Control circuit 120 connects the positive total data line MIOT to the positive input terminal of sensing amplifier circuit 130, and the negative total data line MIOB to the negative input terminal of sensing amplifier circuit 130, based on the low-level signal. When the column selection signal CSL is high and the sensing amplifier circuit control signal SACS is low, the total data line control signal MIOCS is high. Control circuit 120 disconnects the connection between the positive total data line MIOT and the positive input terminal of sensing amplifier circuit 130, and the negative total data line MIOB and the negative input terminal of sensing amplifier circuit 130, based on the high-level signal.

[0048] The control terminal of the sensing amplifier circuit 130 receives the sensing amplifier circuit control signal SACS. The sensing amplifier circuit 130 determines whether to enter the operating state based on the sensing amplifier circuit control signal SACS. When the sensing amplifier circuit control signal SACS is a low-level signal, the sensing amplifier circuit 130 enters the operating state and can detect and amplify the voltage difference Vin between its positive and negative input terminals to obtain the sensed voltage Vsa. When the sensing amplifier circuit control signal SACS is a high-level signal, the sensing amplifier circuit 130 does not enter the operating state.

[0049] In other embodiments, Figure 3 This is a schematic diagram of another dynamic random access memory provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown, the first control terminal of the control circuit 120 is connected to the output terminal of the column decoding circuit 110, and the second control terminal of the control circuit 120 receives the total data line control signal MIOCS. The control circuit 120 generates the bit line control signal BLCS according to the received column selection signal CSL and the total data line control signal MIOCS.

[0050] Specifically, when the column select signal CSL is high and the total data line control signal MIOCS is low, the bit line control signal BLCS is high; when the column select signal CSL is high and the total data line control signal MIOCS is high, the bit line control signal BLCS is low.

[0051] Figure 2 A timing diagram of a dynamic random access memory provided in an embodiment of this disclosure, such as... Figure 2 As shown, before the read command is activated, the column select signal CSL is a low level signal. After the read command is activated, the dynamic random access memory enters the read operation, and the column select signal CSL flips from a low level signal to a high level signal at time T1.

[0052] At this time, the sensing amplifier control signal SACS is a high level signal, the total data line control signal MIOCS is flipped from a high level signal to a low level signal, the bit line control signal BLCS is flipped from a low level signal to a high level signal, and the data of the memory cell passes through the bit line BL and the total data line MIO in turn to the input end of the sensing amplifier 130. The sensing amplifier 130 does not enter the working state, the voltage at the positive input end and the negative input end of the sensing amplifier 130 is the preset voltage Vpre, the voltage difference Vin between the positive input end and the negative input end of the sensing amplifier 130 is 0, and the sensing voltage Vsa is 0.

[0053] In the T1-T2 time period, the column selection signal CSL is a high level signal, the sensing amplifier control signal SACS maintains a high level signal, the total data line control signal MIOCS maintains a low level signal, and the bit line control signal BLCS maintains a high level signal. The voltage difference Vin between the positive input end and the negative input end of the sensing amplifier 130 starts to slowly rise from 0, the sensing voltage Vsa starts to slowly rise from 0, or the voltage difference Vin between the positive input end and the negative input end of the sensing amplifier 130 starts to slowly fall from 0, and the sensing voltage Vsa starts to slowly fall from 0.

[0054] After the T2 moment, the sensing amplifier control signal SACS is flipped from a high level signal to a low level signal, the total data line control signal MIOCS is flipped from a low level signal to a high level signal, and the bit line control signal BLCS is flipped from a high level signal to a low level signal. At this time, the data flows from the input end of the sensing amplifier 130 to the inside of the sensing amplifier 130, the voltage difference Vin between the positive input end and the negative input end of the sensing amplifier 130 reaches the maximum value, the sensing voltage Vsa rises to 1, or the voltage difference Vin between the positive input end and the negative input end of the sensing amplifier 130 reaches the minimum value, and the sensing voltage Vsa falls to -1.

[0055] In this way, during the read operation, when the sensing amplifier enters the working state, the connection between the total data line MIO and the sensing amplifier 130 is disconnected, even if the bit line BL and the total data line MIO are turned on to increase the voltage difference between the positive total data line MIOT and the negative total data line MIOB, the sensing amplifier 130 cannot sense the voltage difference between the positive total data line MIOT and the negative total data line MIOB. That is, when the sensing amplifier enters the working state, if the connection between the bit line BL and the total data line MIO is disconnected, the voltage difference between the positive total data line MIOT and the negative total data line MIOB for sensing has been successfully transmitted to the inside of the sensing amplifier 130, thereby ensuring the normal work of the sensing amplifier 130, while avoiding unnecessary energy consumption.

[0056] In the embodiment of the present disclosure, the dynamic random access memory comprises a column decoding circuit, a control circuit, a sense amplifier circuit, a bit line and a total data line, an output end of the column decoding circuit is connected to a first control end of the control circuit, a second control end of the control circuit is used for receiving a total data line control signal, a first end of the control circuit is connected to the bit line, a second end of the control circuit is connected to one end of the total data line away from the sense amplifier circuit, a third end of the control circuit is connected to one end of the total data line close to the sense amplifier circuit, and a fourth end of the control circuit is connected to an input end of the sense amplifier circuit. In the process of the read operation, when the column selection signal generated by the column decoding circuit is a column conduction signal and the sense amplifier circuit does not enter the working state, the control circuit conducts the bit line to the sense amplifier circuit through the total data line, and when the column selection signal generated by the column decoding circuit is the column conduction signal and the sense amplifier circuit enters the working state, the control circuit disconnects the connection between the bit line and the total data line. Therefore, in the process of the read operation, the bit line and the total data line do not need to be conducted when the sense amplifier circuit normally works, so that the power consumption can be reduced while ensuring normal work.

[0057] In some embodiments, Figure 4 A circuit schematic diagram of the dynamic random access memory provided by the embodiment of the present disclosure is shown in combination with Figure 1 and Figure 4 As shown in the figure, the control circuit 120 comprises a signal generation module 121, a first control module 122 and a second control module 123.

[0058] The first input end of the signal generation module 121 is connected to the output end of the column decoding circuit 110, the second input end of the signal generation module 121 is connected to the control end of the sense amplifier circuit 130 to receive the sense amplifier circuit control signal SACS, the output end of the signal generation module 121 is connected to the control end of the first control module 122, the first control module 122 is connected between the bit line BL and the total data line MIO, the second control module 123 is connected between the total data line MIO and the input end of the sense amplifier circuit 130, and the control end of the second control module 123 is used for receiving the total data line control signal MIOCS.

[0059] For example, as shown in the figure, Figure 4 The signal generation module 121 comprises a first NAND gate NAND1 and a first inverter INV1, the first input end of the first NAND gate NAND1 is connected to the output end of the column decoding circuit 110, the second input end of the first NAND gate NAND1 is connected to the control end of the sense amplifier circuit 130, and the output end of the first NAND gate NAND1 is connected to the control end of the first control module 122 through the first inverter INV1.

[0060] The first NAND gate NAND1 can receive the column selection signal CSL and the sensing amplifier control signal SACS, and perform a NAND operation on the column selection signal CSL and the sensing amplifier control signal SACS, and input the NAND operation result to the first inverter INV1. The first inverter INV1 takes the inverse of the NAND operation result to obtain the bit line control signal BLCS.

[0061] During the read operation, when the sensing amplifier 130 is not in the working state, the column selection signal CSL is a high-level signal, the sensing amplifier control signal SACS is a high-level signal, the NAND operation result output by the first NAND gate NAND1 is a low-level signal, the first inverter INV1 outputs a high-level signal, and the first control module 122 turns on the positive bit line BLT and the positive total data line MIOT and turns on the negative bit line BLB and the negative total data line MIOB under the action of the high-level signal.

[0062] When the sensing amplifier 130 is in the working state, the column selection signal CSL is a high-level signal, the sensing amplifier control signal SACS is inverted to a low-level signal, the NAND operation result output by the first NAND gate NAND1 is a high-level signal, the first inverter INV1 outputs a low-level signal, and the first control module 122 disconnects the connection between the positive bit line BLT and the positive total data line MIOT and disconnects the connection between the negative bit line BLB and the negative total data line MIOB under the action of the low-level signal.

[0063] In this way, during the read operation, the signal generation module 120 can generate a bit line shutdown signal according to the sensing amplifier working signal and the column enable signal, so as to make the first control module 122 disconnect the connection between the bit line BL and the total data line MIO.

[0064] In some embodiments, Figure 5 Another circuit schematic diagram of a dynamic random access memory provided by the embodiment of the present disclosure is shown in FIG. 12. The dynamic random access memory includes a column decoding circuit 110, a sensing amplifier 130, a control circuit 120, and a memory cell array 140. Figure 3 and Figure 5 As shown in FIG. 12, the control circuit 120 includes a signal generation module 121, a first control module 122, and a second control module 123.

[0065] The first input end of the signal generation module 121 is connected to the output end of the column decoding circuit 110, the second input end of the signal generation module 121 is connected to the control end of the second control module 123 to receive the total data line control signal MIOCS, the output end of the signal generation module 121 is connected to the control end of the first control module 122, the first control module 122 is connected between the bit line BL and the total data line MIO, and the second control module 123 is connected between the total data line MIO and the input end of the sensing amplifier 130.

[0066] For example, the signal generation module 121 includes a second NAND gate NAND2, a second inverter INV2, and a third inverter INV3. The first input terminal of the second NAND gate NAND2 is connected to the output terminal of the column decoding circuit 110. The control terminal of the second control module 123 is connected to the second input terminal of the second NAND gate NAND2 through the second inverter INV2. The output terminal of the second NAND gate NAND2 is connected to the control terminal of the first control module 122 through the third inverter INV3.

[0067] The second inverter INV2 can receive the total data line control signal MIOCS and invert the total data line control signal MIOCS. The inverted signal of the total data line control signal MIOCS is transmitted to the second NAND gate NAND2. The second NAND gate NAND2 can perform a NAND operation on the column selection signal CSL and the inverted signal of the total data line control signal MIOCS, and input the result of the NAND operation to the third inverter INV3. The third inverter INV3 inverts the result of the NAND operation to obtain the bit line control signal BLCS.

[0068] During the read operation, when the sense amplifier circuit 130 is not in the working state, the column selection signal CSL is a high-level signal and the total data line control signal MIOCS is a low-level signal. The inverted signal of the total data line control signal MIOCS is a high-level signal. The result of the NAND operation output by the second NAND gate NAND2 is a low-level signal. The third inverter INV3 outputs a high-level signal. Under the action of the high-level signal, the first control module 122 turns on the positive bit line BLT and the positive total data line MIOT, and turns on the negative bit line BLB and the negative total data line MIOB.

[0069] When the sense amplifier circuit 130 is in the working state, the column selection signal CSL is a high-level signal and the total data line control signal MIOCS is a high-level signal. The inverted signal of the total data line control signal MIOCS is a low-level signal. The result of the NAND operation output by the second NAND gate NAND2 is a high-level signal. The third inverter INV3 outputs a low-level signal. Under the action of the low-level signal, the first control module 122 disconnects the connection between the positive bit line BLT and the positive total data line MIOT, and disconnects the connection between the negative bit line BLB and the negative total data line MIOB.

[0070] In this way, during the read operation, the signal generation module 121 generates the bit line control signal according to the column enable signal and the total data line control signal, so as to make the first control module 122 disconnect the connection between the bit line BL and the total data line MIO.

[0071] In some embodiments, continuing to refer to Figure 4 and Figure 5The first control module 122 comprises a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4. The dynamic random memory 100 further comprises a local data line IO, and the local data line IO comprises a positive local data line IOT and a negative local data line IOB.

[0072] The positive local data line IOT is connected to the positive bit line BLT through the first transistor M1, the positive local data line IOT is connected to the positive total data line MIOT through the second transistor M2, the negative local data line IOB is connected to the negative bit line BLB through the third transistor M3, the negative local data line IOB is connected to the negative total data line MIOB through the fourth transistor M4, the control end of the first transistor M1 and the control end of the third transistor M3 are connected to the output end of the signal generation module 121, the control end of the second transistor M2 and the control end of the fourth transistor M4 are used to receive a local data line control signal IOCS, and the local data line control signal IOCS comprises a local data line turn-on signal and a local data line turn-off signal.

[0073] For example, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are N-type metal oxide semiconductor field effect transistors (NMOS), the local data line turn-on signal is a high-level signal, and the local data line turn-off signal is a low-level signal. In other embodiments, the local data line turn-on signal is a low-level signal, and the local data line turn-off signal is a high-level signal. The present disclosure does not make specific limitations on this, and the embodiments of the present disclosure are exemplarily described by taking the local data line turn-on signal as a high-level signal and the local data line turn-off signal as a low-level signal.

[0074] The first end of the first transistor M1 is connected to the positive bit line BLT, the second end of the first transistor M1 is connected to the first end of the second transistor M2 through the positive local data line IOT, the second end of the second transistor M2 is connected to the positive total data line MIOT, the gate of the first transistor M1 receives a bit line control signal BLCS, and the gate of the second transistor M2 receives a local data line control signal IOCS.

[0075] The first end of the third transistor M3 is connected to the negative bit line BLB, the second end of the third transistor M3 is connected to the first end of the fourth transistor M4 through the negative local data line IOB, the second end of the fourth transistor M4 is connected to the negative total data line MIOB, the gate of the third transistor M3 receives the bit line control signal BLCS, and the gate of the fourth transistor M4 receives the local data line control signal IOCS.

[0076] In the process of the read operation, when the column selection signal CSL is a high level signal and the sensing amplifier control signal SACS is a high level signal, the bit line control signal BLCS is a high level signal, the first transistor M1 is in a conductive state, the positive bit line BLT and the positive local data line IOT can be conducted, and the third transistor M3 is also in a conductive state, the negative bit line BLB and the negative local data line IOB can be conducted.

[0077] At this time, the local data line control signal IOCS is a high level signal, the second transistor M2 is in a conductive state, the positive local data line IOT and the positive total data line MIOT can be conducted, and the fourth transistor M4 is also in a conductive state, the negative local data line IOB and the negative total data line MIOB can be conducted.

[0078] When the column selection signal CSL is a high level signal and the sensing amplifier control signal SACS is a low level signal, the bit line control signal BLCS is a low level signal, the first transistor M1 is in a non-conductive state, the connection between the positive bit line BLT and the positive local data line IOT can be disconnected, and the third transistor M3 is also in a non-conductive state, the connection between the negative bit line BLB and the negative local data line IOB can be disconnected.

[0079] At this time, the local data line control signal IOCS can be a low level signal, the second transistor M2 is in a non-conductive state, the connection between the positive local data line IOT and the positive total data line MIOT can be disconnected, and the fourth transistor M4 is also in a non-conductive state, the connection between the negative local data line IOB and the negative total data line MIOB can be disconnected.

[0080] Alternatively, the local data line control signal IOCS can be a high level signal, the second transistor M2 is in a conductive state, the positive local data line IOT and the positive total data line MIOT can be conducted, and the fourth transistor M4 is also in a conductive state, the negative local data line IOB and the negative total data line MIOB can be conducted.

[0081] In some embodiments, continuing to refer to Figure 4 and Figure 5 , the second control module 123 includes a fifth transistor M5 and a sixth transistor M6, the positive total data line MIOT is connected to the positive input end of the sensing amplifier 130 through the fifth transistor M5, the negative total data line MIOB is connected to the negative input end of the sensing amplifier 130 through the sixth transistor M6, and the control end of the fifth transistor M5 and the control end of the sixth transistor M6 are used to receive the total data line control signal MIOCS.

[0082] For example, Figure 4 and Figure 5As shown, the fifth transistor M5 and the sixth transistor M6 are PMOS, the first end of the fifth transistor M5 is connected to the positive global data line MIOT, the second end of the fifth transistor M5 is connected to the positive input end of the sense amplifier circuit 130, the first end of the sixth transistor M6 is connected to the negative global data line MIOB, the second end of the sixth transistor M6 is connected to the negative input end of the sense amplifier circuit 130, and the gate of the fifth transistor M5 and the gate of the sixth transistor M6 receive the global data line control signal MIOCS.

[0083] During the read operation, when the column selection signal CSL is a high level signal and the sense amplifier circuit control signal SACS is a high level signal, the global data line control signal MIOCS is a low level signal, then the fifth transistor M5 is in the on state, which can turn on the positive global data line MIOT and the positive input end of the sense amplifier circuit 130, and the sixth transistor M6 is also in the on state, which can turn on the negative global data line MIOB and the negative input end of the sense amplifier circuit 130.

[0084] When the column selection signal CSL is a high level signal and the sense amplifier circuit control signal SACS is a low level signal, the global data line control signal MIOCS is a high level signal, then the fifth transistor M5 is in the off state, which can disconnect the connection between the positive global data line MIOT and the positive input end of the sense amplifier circuit 130, and the sixth transistor M6 is also in the off state, which can disconnect the connection between the negative global data line MIOB and the negative input end of the sense amplifier circuit 130.

[0085] In some embodiments, continuing to refer to Figure 4 and Figure 5 , the sense amplifier circuit 130 includes a sense amplification module 131 and a sense control module 132, wherein the positive input end of the sense amplification module 131 is connected to the positive input end of the sense amplifier circuit 130, the negative input end of the sense amplification module 131 is connected to the negative input end of the sense amplifier circuit 130, the power supply end of the sense amplification module 130 is connected to an external power supply, the ground end of the sense amplification module 130 is grounded through the sense control module 132, and the control end of the sense control module 132 is used to receive the sense amplifier circuit control signal SACS.

[0086] For example, as Figure 4 and Figure 5 , the sense amplification module 131 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourth inverter INV4.

[0087] The positive input end of the sensing amplification circuit 130 is connected with the second end of the seventh transistor M7, the first end of the ninth transistor M9, the second end of the tenth transistor M10, the second end of the eleventh transistor M11, the control end of the twelfth transistor M12 and the control end of the thirteenth transistor M13, the first end of the seventh transistor M7 and the first end of the eighth transistor M8 are connected with an external power supply, the second end of the eighth transistor M8 is connected with the second end of the ninth transistor M9, the control end of the tenth transistor M10, the control end of the eleventh transistor M11, the second end of the twelfth transistor M12, the second end of the thirteenth transistor M13, the input end of the fourth inverter INV4 and the negative input end of the sensing amplification circuit 130, and the control end of the seventh transistor M7 is connected with the control end of the eighth transistor M8 and the control end of the ninth transistor M9.

[0088] The first end of the tenth transistor M10 and the first end of the twelfth transistor M12 are connected with the external power supply, the first end of the eleventh transistor M11 and the first end of the thirteenth transistor M13 are connected with the output end of the sensing control module 132, the input end of the sensing control module 132 receives a sensing amplification circuit control signal SACS, and the output end of the fourth inverter INV4 is connected with the output end of the sensing amplification circuit 130.

[0089] Specifically, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are PMOS, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12 and the thirteenth transistor M13 are NMOS, the gate of the seventh transistor M7, the gate of the eighth transistor M8 and the gate of the ninth transistor M9 receive an equalization control signal DREAQB, and the external power supply can provide a preset voltage Vpre.

[0090] In the process of the read operation, as shown in Figure 4 , first, the equalization control signal DREAQB is a low-level signal, the column selection signal CSL is a low-level signal, the bit line control signal BLCS is a low-level signal, the total data line control signal MIOCS is a high-level signal, and the sensing amplification circuit control signal SACS is a high-level signal. At this time, the seventh transistor M7 and the eighth transistor M8 are in the on state, the external power supply can provide the preset voltage Vpre to the positive input end and the negative input end of the sensing amplification circuit 130, and the ninth transistor M9 is also in the on state, which can equalize the voltages of the positive input end and the negative input end of the sensing amplification circuit 130.

[0091] Then, the column select signal CSL remains low, the bit line control signal BLCS remains low, the total data line control signal MIOCS remains high, the sense amplifier circuit control signal SACS remains high, and the equalization control signal DREAQB flips to high. At this time, the seventh transistor M7 and the eighth transistor M8 are in the off state, the external power supply stops supplying the preset voltage Vpre to the positive and negative input terminals of the sense amplifier circuit 130, and the ninth transistor M9 is also in the off state, which can stop the voltage at the positive and negative input terminals of the equalization sense amplifier circuit 130.

[0092] Subsequently, the equalization control signal DREAQB remains high, the column select signal CSL flips to high, the total data line control signal MIOCS flips to low, the sense amplifier circuit control signal SACS remains high, and the bit line control signal BLCS flips to high.

[0093] Finally, the total data line control signal MIOCS flips to a high level, the column select signal CSL remains high, the sense amplifier circuit control signal SACS flips to a low level, and the bit line control signal BLCS flips to a low level.

[0094] For example, such as Figure 5 and Figure 2 Figure 4 Figure 5 The sensing control module 132 includes a fourteenth transistor M14 and a fifth inverter INV5. The second terminal of the fourteenth transistor M14 is connected to the ground terminal of the sensing amplification module 131, the first terminal of the fourteenth transistor M14 is grounded, the control terminal of the fourteenth transistor M14 is connected to the output terminal of the fifth inverter INV5, and the input terminal of the fifth inverter INV5 receives the sensing amplification circuit control signal SACS.

[0095] Specifically, the fourteenth transistor M14 is a PMOS, and its gate is connected to the output of the fifth inverter INV5. The fifth inverter INV5 can invert the sensing amplifier circuit control signal SACS to obtain the inverted signal of the sensing amplifier circuit control signal SACS. The inverted signal of the sensing amplifier circuit control signal SACS can control the on / off state of the fourteenth transistor M14.

[0096] When the sensing amplifier circuit control signal SACS is high, its inverted form is low, and the fourteenth transistor M14 is off, preventing the sensing amplifier module 131 from operating. When the sensing amplifier circuit control signal SACS is low, its inverted form is high, and the fourteenth transistor M14 is on, allowing the sensing amplifier module 131 to operate.

[0097] The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, the references "a" and "an" are typically used to describe a single item unless otherwise indicated. Similarly, the word "or" is generally intended to mean "and / or" unless otherwise indicated. The terms "comprises," "comprising," "includes," "including," and the like can be used herein and are intended to mean that an item includes one or more of the recited elements or a subset thereof. Similarly, the terms "includes," "including," and the like are intended to mean that an item includes one or more of the recited elements or a subset thereof, but does not require the presence of these elements or subsets at a particular time. The use of the term "or" in the context of a list of items is intended to mean that one or more of the items can be present, and the use of the term "and" in the context of a list of items is intended to mean that one or more of the items can be present. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration," and not to imply that a described embodiment is preferred or superior to other embodiments. The term "in response to" is used herein to mean "in response to a determination that" and not to imply that a described embodiment is preferred or superior to other embodiments.

[0098] Further aspects and scope of adaptations become apparent from the description provided herein. It should be understood that various aspects of the present application can be practiced alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0099] The above detailed description of several embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form described. Many modifications and variations are possible in light of this disclosure. It is intended to cover all modifications and variations as long as they fall within the scope of the disclosure. The disclosure was chosen and disclosed in order to best explain the principles and the practical application of the disclosure to others skilled in the art.

Claims

1. A dynamic random access memory, characterized by, The application relates to a memory cell, which comprises a column decoding circuit, a control circuit, a sense amplifier circuit, a bit line and a total data line. An output end of the column decoding circuit is connected to a first control end of the control circuit, a second control end of the control circuit is used for receiving a total data line control signal, a first end of the control circuit is connected to the bit line, a second end of the control circuit is connected to an end of the total data line away from the sense amplifier circuit, a third end of the control circuit is connected to an end of the total data line close to the sense amplifier circuit, and a fourth end of the control circuit is connected to an input end of the sense amplifier circuit. The column decoding circuit is configured to generate a column selection signal, and the column selection signal comprises a column on signal and a column off signal. The control circuit is configured to, in the process of a read operation, when the column selection signal is the column on signal and the sense amplifier circuit does not enter a working state, turn on the bit line through the total data line and the sense amplifier circuit, and when the column selection signal is the column on signal and the sense amplifier circuit enters the working state, disconnect the bit line and the total data line. The control circuit comprises a signal generation module, a first control module and a second control module.

2. The dynamic random access memory of claim 1, wherein, A first input end of the signal generation module is connected to an output end of the column decoding circuit, a second input end of the signal generation module is connected to a control end of the sense amplifier circuit to receive a sense amplifier circuit control signal, the sense amplifier circuit control signal comprises a sense amplifier circuit working signal and a sense amplifier circuit working stop signal. An output end of the signal generation module is connected to a control end of the first control module, the first control module is connected between the bit line and the total data line, the second control module is connected between the total data line and an input end of the sense amplifier circuit, a control end of the second control module is used for receiving the total data line control signal, and the total data line control signal comprises a total data line on signal and a total data line off signal. The signal generation module is configured to, in the process of the read operation, generate a bit line off signal according to the sense amplifier circuit working signal and the column on signal, so that the first control module disconnects the bit line and the total data line. The signal generation module comprises a first NAND gate and a first inverter.

3. The dynamic random access memory of claim 2, wherein, A first input end of the first NAND gate is connected to an output end of the column decoding circuit, a second input end of the first NAND gate is connected to a control end of the sense amplifier circuit, and an output end of the first NAND gate is connected to a control end of the first control module through the first inverter. The control circuit comprises a signal generation module, a first control module and a second control module.

4. The DRAM of claim 1, wherein, A first input end of the signal generation module is connected to an output end of the column decoding circuit, a second input end of the signal generation module is connected to a control end of the second control module to receive a total data line control signal, and the total data line control signal comprises a total data line on signal and a total data line off signal. ​ An output terminal of the signal generation module is connected to a control terminal of the first control module, the first control module is connected between the bit line and the total data line, and the second control module is connected between the total data line and an input terminal of the sense amplifier circuit; The signal generation module is configured to generate a bit line turn-off signal according to the column decode signal and the total data line turn-off signal during the read operation, so that the first control module disconnects the connection between the bit line and the total data line.

5. The DRAM of claim 4, wherein, The signal generation module comprises a second NAND gate, a second inverter and a third inverter; A first input terminal of the second NAND gate is connected to an output terminal of the column decode circuit, a control terminal of the second control module is connected to a second input terminal of the second NAND gate through the second inverter, and an output terminal of the second NAND gate is connected to a control terminal of the first control module through the third inverter.

6. The dynamic random access memory of claim 2 or 4, wherein, The first control module comprises a first transistor, a second transistor, a third transistor and a fourth transistor, the bit line comprises a positive bit line and a negative bit line, the total data line comprises a positive total data line and a negative total data line, and the dynamic random access memory further comprises a positive local data line and a negative local data line; The positive bit line is connected to the positive local data line through the first transistor, the positive local data line is connected to the positive total data line through the second transistor, the negative bit line is connected to the negative local data line through the third transistor, the negative local data line is connected to the negative total data line through the fourth transistor, a control terminal of the first transistor and a control terminal of the third transistor are connected to an output terminal of the signal generation module, and a control terminal of the second transistor and a control terminal of the fourth transistor are used to receive a local data line control signal, the local data line control signal comprising a local data line turn-on signal and a local data line turn-off signal.

7. The DRAM of claim 2 or 4, wherein, The second control module comprises a fifth transistor and a sixth transistor, and the total data line comprises a positive total data line and a negative total data line; The positive total data line is connected to a positive input terminal of the sense amplifier circuit through the fifth transistor, the negative total data line is connected to a negative input terminal of the sense amplifier circuit through the sixth transistor, and a control terminal of the fifth transistor and a control terminal of the sixth transistor are used to receive the total data line control signal.

8. The dynamic random access memory of any one of claims 1-5, wherein, The sense amplifier circuit comprises a sense amplification module and a sense control module; A positive input terminal of the sense amplification module is connected to a positive input terminal of the sense amplifier circuit, a negative input terminal of the sense amplification module is connected to a negative input terminal of the sense amplifier circuit, a power supply terminal of the sense amplification module is connected to an external power supply, a ground terminal of the sense amplification module is grounded through the sense control module, and a control terminal of the sense control module is used to receive a sense amplifier circuit control signal.

9. The dynamic random access memory of claim 8, wherein, The sense amplification module comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourth inverter; The positive input end of the sense amplifier circuit is connected with the second end of the seventh transistor, the first end of the ninth transistor, the second end of the tenth transistor, the second end of the eleventh transistor, the control end of the twelfth transistor and the control end of the thirteenth transistor, the first end of the seventh transistor and the first end of the eighth transistor are connected with the external power supply, the second end of the eighth transistor is connected with the second end of the ninth transistor, the control end of the tenth transistor, the control end of the eleventh transistor, the second end of the twelfth transistor, the second end of the thirteenth transistor, the input end of the fourth inverter and the negative input end of the sense amplifier circuit, the control end of the seventh transistor is connected with the control end of the eighth transistor and the control end of the ninth transistor; The first end of the tenth transistor and the first end of the twelfth transistor are connected with the external power supply, the first end of the eleventh transistor and the first end of the thirteenth transistor are connected with the output end of the sensing control module, the input end of the sensing control module is used for receiving the sense amplifier circuit control signal, and the output end of the fourth inverter is connected with the output end of the sense amplifier circuit.

10. The dynamic random access memory of claim 8, wherein, The sensing control module comprises a fourteenth transistor and a fifth inverter; The second end of the fourteenth transistor is connected with the ground end of the sensing amplifier module, the first end of the fourteenth transistor is grounded, the control end of the fourteenth transistor is connected with the output end of the fifth inverter, and the input end of the fifth inverter is used for receiving the sense amplifier circuit control signal.

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