NAND Flash read interference testing device

Abstract

The utility model discloses an NAND Flash read interference testing device, comprising an FPGA module, an STM single-chip microcomputer and a plurality of testing seats, the FPGA module is electrically connected with the STM single-chip microcomputer and the plurality of testing seats respectively, the STM single-chip microcomputer is electrically connected with the plurality of testing seats, and the testing seats are used for carrying an NAND Flash; the STM single-chip microcomputer is used for issuing a basic test instruction to carry out a basic test on the NAND Flash carried on each test seat, and collecting test data in the test process and sending the test data to the FPGA module. Wherein the basic test comprises a read-write test; and the FPGA module is used for issuing a read interference test instruction after the basic test is passed so as to carry out read interference test on the NAND Flash carried on the test seat. According to the NAND Flash read interference test device, the read interference test is carried out after the NAND Flash test environment is determined to be normal, so that the influence of other factors on the read interference test is avoided, and the accuracy of a read interference test result is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor test, especially relates to a NAND Flash read interference testing device. BACKGROUND

[0002] NAND Flash (namely flash memory) as a kind of nonvolatile flash memory, is widely used in various electronic devices, for long-term data storage, even if the device power off, data can still be saved.

[0003] In NAND Flash storage, there is read interference phenomenon, that is, when reading the storage unit of NAND Flash, the data of adjacent storage unit can be interfered, resulting in its data change. Therefore, before NAND Flash product leaves factory, it is usually necessary to carry out read interference test by testing device to evaluate the quality and reliability of NAND Flash product.

[0004] However, when NAND Flash is tested for read interference, there may be abnormalities due to NAND Flash structure or test connection, such as NAND Flash has bad block (namely the storage unit block that cannot normally carry out data read-write operation), since the data state of bad block itself is unreliable, it is easy to attribute the data of bad block to read interference error, and then affect the read interference test, resulting in inaccurate read interference test result. UTILITY MODEL CONTENTS

[0005] The main purpose of the utility model is to provide a kind of NAND Flash read interference testing device, to solve the technical problem that current NAND Flash read interference test result is not accurate enough.

[0006] To achieve the above purpose, the utility model provides a kind of NAND Flash read interference testing device, the NAND Flash read interference testing device includes FPGA module, STM single-chip microcomputer and multiple test seats, the FPGA module is electrically connected with the STM single-chip microcomputer and the multiple test seats respectively, the STM single-chip microcomputer is electrically connected with the multiple test seats, and the test seat is used to carry NAND Flash;

[0007] The STM single-chip microcomputer is used to issue basic test instruction to carry out basic test to NAND Flash carried on each test seat, and test data is collected and sent to the FPGA module in the testing process;Wherein, the basic test includes read-write test;

[0008] The FPGA module is configured to issue a read interference test instruction to perform a read interference test on the NAND Flash mounted on the test socket after the basic test is passed.

[0009] In some embodiments, the NAND Flash read interference test device further comprises a first power supply module electrically connected to the plurality of test sockets for supplying power to the plurality of test sockets and the NAND Flash mounted thereon.

[0010] In some embodiments, the NAND Flash read interference test device further comprises a plurality of power switches, each of which is arranged between one of the test sockets and the first power supply module and electrically connected to the STM single-chip microcomputer.

[0011] The STM single-chip microcomputer can control the power switches to be turned on to power on the test sockets and the NAND Flash mounted thereon, or to be turned off to power off the test sockets and the NAND Flash mounted thereon.

[0012] In some embodiments, the basic test further comprises a power-on test before the read-write test.

[0013] The STM single-chip microcomputer collects voltage and current data of the test sockets and the NAND Flash mounted thereon during the power-on test, and determines whether the NAND Flash mounted on the test socket is powered on normally according to the collected voltage and current data.

[0014] In some embodiments, the basic test further comprises a communication test after the power-on test and before the read-write test.

[0015] The STM single-chip microcomputer issues a communication test instruction to test whether the communication with the test socket and the NAND Flash mounted thereon is normal during the communication test.

[0016] In some embodiments, the power switches are MOS tubes.

[0017] In some embodiments, when the FPGA module performs a read interference test on the NAND Flash mounted on the test socket, it randomly selects one page in a preset block of the NAND Flash to perform a repeated read operation, and periodically performs ECC data verification on all pages in the preset block.

[0018] In some embodiments, the STM single-chip microcomputer and the FPGA module communicate through a UART serial port.

[0019] In some embodiments, the NAND Flash read interference test device further comprises a second power module, which is electrically connected with the FPGA module and used for powering the FPGA module.

[0020] In some embodiments, the NAND Flash read interference test device further comprises a host computer, which is in communication connection with the FPGA module.

[0021] The NAND Flash read interference test device of the utility model carries out test to NAND Flash first, issues basic test instruction through STM single-chip microcomputer to carry out basic test including read-write test to NAND Flash carried on each test seat, and collects test data and sends to FPGA module in the test process, issues read interference test instruction through FPGA module to carry out read interference test to NAND Flash carried on the test seat after the basic test passes, namely, the utility model carries out basic test (such as read-write test included to detect whether there is bad block in NAND Flash) to NAND Flash carried on the test seat first, can carry out read interference test after the basic test passes, namely, carries out read interference test to NAND Flash after determining that the test environment of NAND Flash is normal, avoids other factors to cause the influence of read interference test, and it is helpful to improve the accuracy of read interference test result. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is the structural schematic diagram of NAND Flash read interference test device in an embodiment of the utility model. DETAILED DESCRIPTION

[0023] The scheme in the embodiments of the utility model will be clearly and completely described below in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only some of the embodiments in the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the utility model.

[0024] It should be noted that all directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the utility model are only used to explain the relative positional relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directionality indications also change accordingly.

[0025] It is also needed to state that when an element is named as "fixed on" or "set on" another element, it can be directly on another element or a middle element can exist simultaneously. When an element is named as "connected" another element, it can be directly connected another element or a middle element can exist simultaneously.

[0026] In addition, the description involving "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor in the protection scope required by the present application.

[0027] The embodiment of the present application provides a NAND Flash read interference test device, referring to Figure 1 The NAND Flash read interference test device comprises an FPGA module 100, an STM single-chip microcomputer 200 and a plurality of test seats 300, the FPGA module 100 is electrically connected with the STM single-chip microcomputer 200 and the plurality of test seats 300 respectively, the STM single-chip microcomputer 200 is electrically connected with the plurality of test seats 300, and the test seat 300 is used for carrying the NAND Flash;

[0028] The STM single-chip microcomputer 200 is used for issuing a basic test instruction to perform basic test on the NAND Flash carried on each test seat 300, and collecting test data in the test process and sending the test data to the FPGA module 100; wherein the basic test comprises read-write test;

[0029] The FPGA module 100 is used for issuing a read interference test instruction to perform read interference test on the NAND Flash carried on the test seat 300 after the basic test passes.

[0030] Among them, the NAND Flash can be applied to various devices, and the read interference resistance performance of the NAND Flash directly affects the working performance of the applied device. For example, in industrial control devices (such as PLC and HMI), the NAND Flash is often used for long-term data storage and system log recording, and read interference will affect data stability. By screening NAND Flash with strong read interference resistance performance, the long-term stable operation of the device can be ensured. In network devices such as routers and switches, NAND Flash stores firmware and configuration files, and has high requirements for data stability. Screening NAND Flash with high anti-interference performance can help improve the reliability of network devices. In car navigation and entertainment systems, NAND Flash is used to store a large amount of read data. Screening NAND Flash with high read interference resistance can help ensure the stability of the vehicle system in harsh environments. In smart home and Internet of Things devices, NAND Flash is often used for configuration information and log storage, and has a long running cycle and frequent reading. Screening NAND Flash with strong read interference resistance can prolong the service life of the device and improve data reliability. In this embodiment, the NAND Flash can be SPI NAND Flash or PPI NAND Flash.

[0031] The NAND Flash read interference test device related in this embodiment is mainly a test device for NAND Flash, which is used to test the read interference of NAND Flash to verify the read interference resistance performance of NAND Flash. Moreover, a basic test is performed before the read interference test to ensure that the read interference test of NAND Flash is performed in a normal test environment.

[0032] Among them, the STM single-chip microcomputer 200 (also referred to as STM microcontroller) related can issue basic test instructions and high-precision ADC sampling. After issuing the basic test instructions, the test data of each test seat 300 is sampled in real time, the analog signals of the NAND Flash tested by each test seat 300 are received and converted into data information, and then the sampled test data (such as current and voltage data) are analyzed and processed to verify the test environment before the read interference test of the NAND Flash. Among them, the basic test includes read-write test, but is not limited thereto. The read-write test can be: performing a small range of read-write operation once, such as writing test data to a specified page and then reading back the test data to verify whether the test data is correctly written and read. Through the read-write test, it can be judged whether each NAND Flash has serious bad blocks or communication problems.

[0033] The FPGA module 100 involved can issue read interference test instructions. The FPGA module 100 is the core of the anti-read interference test device, is responsible for implementing efficient parallel SPI (Serial Peripheral Interface) interface and PPI (Parallel Peripheral Interface) interface control, has a high parallel architecture, can realize read interference multi-channel parallel test through time division multiplexing, and improves test efficiency. The FPGA module 100 has multiple SPI and PPI interfaces, can realize multi-channel parallel test through configuration. The FPGA module 100 can select Xilinx or Intel FPGA module 100, has rich I / O interfaces, can fully utilize the time division multiplexing mechanism of the FPGA, and realizes more parallel test of NAND Flash. For example, the FPGA module 100 can simultaneously configure 20 SPI channels, alternately uses the interfaces through grouping test, and realizes parallel test of 40 SPI interfaces, improves the number of chips tested at the same time and efficiency.

[0034] When the NAND Flash read interference test device executes test on the NAND Flash, first, the STM single-chip microcomputer 200 issues basic test instructions to perform basic test including read-write test on the NAND Flash carried on each test seat 300, collects test data in the test process and sends the test data to the FPGA module 100, and after the basic test passes, the FPGA module 100 issues read interference test instructions to perform read interference test on the NAND Flash carried on the test seat 300.

[0035] That is, the NAND Flash read interference test device first performs basic test (such as read-write test included, to detect whether there is a bad block in the NAND Flash) on the NAND Flash carried on the test seat 300, can perform read interference test after the basic test passes, that is, performs read interference test on the NAND Flash after determining that the test environment of the NAND Flash is normal, avoids that other factors affect the read interference test, and helps to improve the accuracy of the read interference test result.

[0036] In some embodiments, reference is made to Figure 1The NAND Flash read interference test device further comprises a first power module 400 electrically connected with the plurality of test seats 300, for supplying power to the plurality of test seats 300 and the NAND Flash mounted thereon. In the embodiment, the first power module 400 is configured as a test-dedicated power supply, for supplying power to the test seats 300 and the NAND Flash. A power switch 500 can be arranged between the first power module 400 and the plurality of test seats 300, and the power switch 500 is responsible for controlling the plurality of test seats 300 to be powered on or powered off synchronously. Alternatively, a plurality of power switches 500 can be arranged between the first power module 400 and the plurality of test seats 300, and each power switch 500 is responsible for controlling one or more test seats 300 to be powered on or powered off.

[0037] In some embodiments, the basic test further comprises a power-on test before the read-write test. Figure 1 The NAND Flash read interference test device further comprises a plurality of power switches 500, each of which is arranged between a test seat 300 and the first power module 400 and electrically connected with the STM single-chip microcomputer 200. The STM single-chip microcomputer 200 can control the power switch 500 to be turned on to power on the test seat 300 and the NAND Flash mounted thereon, or to be turned off to power off the test seat 300 and the NAND Flash mounted thereon. In the embodiment, each test seat 300 is equipped with an independent power switch 500, which is controlled by the STM single-chip microcomputer 200 to achieve independent power management of each test seat 300. The independent power supply of each test seat 300 can be achieved by controlling the power supply channel through the power switch 500, and when power abnormality (such as short circuit or leakage) occurs in a certain test seat 300, the power supply state of other test seats 300 will not be affected. This design can effectively isolate the power interference between different test seats 300, ensure the independence and accuracy of the test data of each test seat 300, and is suitable for reliability test of a plurality of NAND Flash in parallel test. Moreover, when abnormality occurs in a certain test seat 300, the STM single-chip microcomputer 200 can immediately turn off the corresponding power switch 500 to cut off the power supply of the test seat 300, thereby avoiding the influence of the test seat 300 failure on the overall system. This instant power-off protection mechanism can effectively protect other normally working test seats 300 and the power supply system, and improve the fault tolerance and reliability of the test system.

[0038] In some embodiments, the basic test further comprises a power-on test before the read-write test.

[0039] The STM single-chip microcomputer 200 collects voltage and current data of the test socket 300 and the NAND Flash mounted thereon during the power-on initialization test, and determines whether the power-on of the NAND Flash mounted on the test socket 300 is normal according to the collected voltage and current data.

[0040] That is, at the beginning of the basic test, the first power module 400 powers on each test socket 300 and the NAND Flash mounted thereon, waits for the power to stabilize, and confirms that the voltage and current are within the normal range. The STM single-chip microcomputer 200 collects voltage and current data of the test socket 300 and the NAND Flash mounted thereon, and analyzes the fluctuation of the collected voltage and current data to determine whether the power-on of the NAND Flash is normal and identify potential abnormalities, such as excessive current (which may indicate that the test socket 300 has a short circuit or leakage) and unstable voltage.

[0041] In some embodiments, the basic test further includes a communication test after the power-on test and before the read-write test.

[0042] The STM single-chip microcomputer 200 issues a communication test instruction during the communication test to test whether the communication with the test socket 300 and the NAND Flash mounted thereon is normal.

[0043] Specifically, the STM single-chip microcomputer 200 sends a communication test instruction (such as a read ID instruction) to the test socket 300 and the NAND Flash, waits for a short time (the waiting time is determined according to the specific product and communication speed, and generally there will be feedback within a few seconds), and then observes whether there is a return information (such as an ID value).

[0044] If the STM single-chip microcomputer 200 receives feedback content containing information corresponding to the communication test instruction, it means that the communication link of the test socket 300 is normal, and the test socket 300 can normally transmit and receive data. The STM single-chip microcomputer 200 communicates normally with the test socket 300 and the NAND Flash mounted thereon.

[0045] If there is no return, it may be that the communication link has a problem such as a broken circuit, for example, poor interface contact or hardware failure of the test socket 300, which causes the communication test instruction to not be sent to the test socket 300 and the NAND Flash mounted thereon or not to respond after being sent. If an error message is returned, it may involve a variety of reasons such as communication rate mismatch and network congestion, and further investigation and adjustment of the corresponding communication parameters or network environment are required.

[0046] Through the above sending of the communication test instruction and the observation and analysis of the response, it can be checked whether the STM single-chip microcomputer 200 and the test seat 300 and the NAND Flash carried thereby are in a normal state, and if an abnormality occurs, further in-depth troubleshooting and repair are required, so as to ensure that the communication interface of the STM single-chip microcomputer 200 and each test seat 300 is normally connected.

[0047] In the embodiment, the basic test involved at least includes power-on test, communication test and read-write test, and the test sequence is: power-on test → communication test → read-write test, and when the power-on test passes, the communication test can be continued to be executed, and when the communication test passes, the read-write test can be continued to be executed. When any one of the power-on test, the communication test and the read-write test of a certain test seat 300 and the NAND Flash carried thereby does not pass, it means that the basic test does not pass, and the system records problem information and reports an abnormality.

[0048] In some embodiments, with reference to Figure 1 The power switch 500 is a MOS tube. The power switch 500 uses a MOS tube as a switching device, has high input impedance, low driving power, fast switching speed and other characteristics, the input impedance of the MOS tube is extremely high, almost no input current is required to control its switching state, the load of the driving circuit is extremely small, no obvious current draw and voltage drop will be generated to the previous stage circuit, the driving signal only needs to provide sufficient voltage to effectively control the on-off of the MOS tube, so that the control circuit design is simpler and easier to implement. Because of the high input impedance, the MOS tube only needs a small driving power to work normally, compared with the current-controlled bipolar transistor, no large base current is required to drive, so that the driving circuit design can be simplified, the power consumption and cost of the driving circuit can be reduced, and it is also more conducive to miniaturization and integration. In addition, the MOS tube can be quickly started and stopped by the switching instruction of the STM single-chip microcomputer 200 within milliseconds or even microseconds, so as to accurately control the power supply at the beginning and end of the test, and avoid unnecessary current consumption.

[0049] In some embodiments, the FPGA module 100 performs read interference test on the NAND Flash carried on the test seat 300. When performing read interference test, a page is randomly selected in the preset block of the NAND Flash to perform repeated read operation, and periodic ECC data check is performed on all pages in the preset block.

[0050] In the embodiment, the test principle of the read interference test is that: first, the preset block of the NAND Flash is programmed, and the initial ECC state of all pages of the preset block is recorded, which is usually 0-bit error, and if there is a page with initial ECC state of 1-bit error, the state is recorded.

[0051] Then, a page is randomly selected in the preset block, and a high-frequency read operation is performed on the page. For example, the read operation can be implemented by sending a 13 instruction and reading data to the NAND Flash internal cache, without the need to transfer data to the host, so as to reduce the test resource occupation.

[0052] During the read disturb test, the ECC data of all pages in the preset block is checked according to a preset checking period. The checking period can be self-defined. For example, after 10 million read operations are performed on the page, the ECC data of all pages in the preset block is checked once. That is, after a certain number of read operations, the data is compared through ECC checking to determine whether bit flipping occurs. Through periodic sampling, the ECC state and error rate of the page are recorded, and the read disturb intensity change from bit flipping to data failure is captured. That is, the ECC state of each page in the preset block is recorded at the beginning, and the change of the ECC is monitored as the read disturb test is performed.

[0053] Further, in the mass production test, the pages in the preset block are subjected to high-frequency read operations, and when the ECC state of the page jumps from 0-bit error to 1-bit error, the more the number of read operations performed, the better the read disturb resistance of the NAND Flash. Therefore, the read disturb resistance of the NAND Flash can be graded according to the number of read operations performed when the ECC state of the page jumps from 0-bit to 1-bit, so as to reduce the flow of chips with low read disturb resistance into high-reliability application scenarios. For example, when the ECC state of the page jumps from 0-bit to 1-bit, if the number of read operations performed is significantly higher than the preset number (e.g., 10 million), it is determined that the read disturb resistance of the NAND Flash is optimal, and it is suitable for high-reliability scenarios. If the number of read operations performed is close to the preset number (e.g., 10 million), it is determined that the read disturb resistance of the NAND Flash is good, and it is suitable for general reliability scenarios. If the number of read operations performed is significantly lower than the preset number (e.g., 10 million), it is determined that the read disturb resistance of the NAND Flash is weak, and it is suitable for low-reliability scenarios.

[0054] In some embodiments, UART serial communication is used between the STM single-chip microcomputer 200 and the FPGA module 100. UART (universal asynchronous receiver-transmitter) serial communication has simple hardware connection, requires few external components, has low hardware cost, and has a relatively simple communication protocol, which helps to reduce development cost and shorten development cycle.

[0055] In some embodiments, with reference to Figure 1The NAND Flash read interference test device further comprises a second power module 600, which is electrically connected with the FPGA module 100 and used for supplying power for the FPGA module 100. In the embodiment, the second power module 600 is used as a special power supply for the FPGA module 100 and is configured to supply power for the FPGA module 100. The second power module 600 can provide stable voltage and current output, so that the FPGA module 100 can obtain stable power supply in different working states, and system failure and error caused by power supply problems are reduced. In addition, different FPGA modules 100 may need different power supply voltages in different application scenarios, and the second power module 600 can conveniently adjust the output voltage according to the type and application requirement of the FPGA module 100, so that various voltage requirements can be met.

[0056] In some embodiments, with reference to Figure 1 The NAND Flash read interference test device further comprises a host computer 700, which is in communication connection with the FPGA module 100. The host computer 700 can be a computer, and the FPGA can communicate with the host computer 700 through a USB interface, so as to upload real-time sampling data, chip power supply state, test state and other information to the host computer 700. The host computer 700 displays the power supply state, current / voltage fluctuation and data record of each test seat 300 and the NAND Flash carried thereby in correspondence, and a user can monitor the test progress in real time through an interface and adjust test parameters according to requirements.

[0057] The above only describes some or preferred embodiments of the present application, and neither the text nor the drawings can limit the scope of protection of the present application. Equivalent structural transformations and direct / indirect applications in other related technical fields made by using the content of the present application and drawings are included in the scope of protection of the present application.

Claims

1. A NAND Flash read disturb test apparatus, characterized by, The application relates to a NAND Flash test device, which comprises an FPGA module, an STM single-chip microcomputer and a plurality of test seats, wherein the FPGA module is electrically connected with the STM single-chip microcomputer and the plurality of test seats respectively, the STM single-chip microcomputer is electrically connected with the plurality of test seats, and the test seat is used for carrying the NAND Flash. The STM single-chip microcomputer is used for issuing a basic test instruction to perform basic test on the NAND Flash carried on each test seat and collecting test data in the test process and sending the test data to the FPGA module; wherein the basic test comprises read-write test. The FPGA module is used for issuing a read interference test instruction to perform read interference test on the NAND Flash carried on the test seat after the basic test is passed.

2. The NAND Flash read disturb test apparatus of claim 1, wherein, The application further comprises a first power module, which is electrically connected with the plurality of test seats and is used for supplying power for the plurality of test seats and the NAND Flash carried thereon.

3. The NAND Flash read disturb test apparatus of claim 2, wherein, The application further comprises a plurality of power switches, each of which is arranged between a test seat and the first power module and is electrically connected with the STM single-chip microcomputer. The STM single-chip microcomputer can control the power switch to be opened to power on the test seat and the NAND Flash carried thereon or to be closed to power off the test seat and the NAND Flash carried thereon.

4. The NAND Flash read disturb test apparatus of claim 3, wherein, The basic test further comprises power-on test before the read-write test. The STM single-chip microcomputer collects voltage and current data of the test seat and the NAND Flash carried thereon in the power-on test process and judges whether the NAND Flash carried on the test seat is normally powered on according to the collected voltage and current data.

5. The NAND Flash read disturb test apparatus of claim 4, wherein, The basic test further comprises communication test after the power-on test and before the read-write test. The STM single-chip microcomputer issues a communication test instruction in the communication test process to test whether the communication with the test seat and the NAND Flash carried thereon is normal.

6. The NAND Flash read disturb test apparatus of claim 3, wherein, The power switch is a MOS tube.

7. The NAND Flash read disturb test apparatus according to any one of claims 1 to 6, wherein When the FPGA module performs read interference test on the NAND Flash carried on the test seat, a repeated read operation is performed on a randomly selected page in a preset block of the NAND Flash, and periodic ECC data check is performed on all pages in the preset block.

8. The NAND Flash read disturb test apparatus according to any one of claims 1 to 6, wherein UART serial communication is adopted between the STM single-chip microcomputer and the FPGA module.

9. The NAND Flash read disturb test apparatus according to any one of claims 1 to 6, wherein The application further comprises a second power module, which is electrically connected with the FPGA module and is used for supplying power for the FPGA module.

10. The NAND Flash read disturb test apparatus according to any one of claims 1 to 6, wherein The application further comprises an upper computer, which is in communication connection with the FPGA module.

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