Composite package

Abstract

The embodiment of the utility model provides a composite packaging piece. A composite package includes a vertical stack of a first semiconductor package, a second semiconductor package, and a third semiconductor package, where the first semiconductor package includes at least one first semiconductor die, the at least one first semiconductor die including a first metal bond pad; the second semiconductor package comprises at least one second semiconductor tube core, and the at least one second semiconductor tube core comprises a second metal bonding pad; a third semiconductor package including at least one third semiconductor die, the at least one third semiconductor die including a third metal bonding pad; bonding each pair of vertically adjacent semiconductor packages within the vertical stack to each other by metal-to-metal bonding between the paired metal bonding pads; and vertical sidewalls of at least three semiconductor packages including the first semiconductor package, the second semiconductor package, and the third semiconductor package vertically coincide with each other.

Description

TECHNICAL FIELD

[0001] The embodiment of the utility model relates to a composite package. BACKGROUND

[0002] Multiple semiconductor chips can be vertically stacked to provide semiconductor packages with reduced package size, increased data transfer rates, and enhanced performance. SUMMARY

[0003] The embodiment of the utility model provides a composite package, include: the vertical stack of first semiconductor package, second semiconductor package and third semiconductor package, wherein the first semiconductor package includes at least one first semiconductor die, the at least one first semiconductor die includes first metal bonding pad, the second semiconductor package includes at least one second semiconductor die, the at least one second semiconductor die includes second metal bonding pad, the third semiconductor package includes at least one third semiconductor die, the at least one third semiconductor die includes third metal bonding pad, by the metal-to-metal bonding between the matched metal bonding pad, every pair of vertically adjacent semiconductor package in the vertical stack is bonded with each other, and the vertical sidewall of at least three semiconductor packages including the first semiconductor package, the second semiconductor package and the third semiconductor package vertically coincides with each other.

[0004] The embodiment of the utility model provides a composite package, include: the vertical stack of first semiconductor package, second semiconductor package and third semiconductor package, wherein the first semiconductor package includes at least one first semiconductor die, the at least one first semiconductor die includes first metal bonding pad, the second semiconductor package includes at least one second semiconductor die, the at least one second semiconductor die includes second metal bonding pad, the third semiconductor package includes at least one third semiconductor die, the at least one third semiconductor die includes third metal bonding pad, by the metal-to-metal bonding between the matched metal bonding pad, every pair of vertically adjacent semiconductor package in the vertical stack is bonded with each other, and the vertical sidewall of at least three semiconductor packages including the first semiconductor package, the second semiconductor package and the third semiconductor package vertically coincides with each other.

[0005] The utility model embodiment provides a kind of composite package, comprising: the vertical stack of first semiconductor package, second semiconductor package and third semiconductor package, wherein the first semiconductor package includes at least one first semiconductor die, and the at least one first semiconductor die includes first metal bonding pad;The second semiconductor package includes at least one second semiconductor die, and the at least one second semiconductor die includes second metal bonding pad;The third semiconductor package includes at least one third semiconductor die, and the at least one third semiconductor die includes third metal bonding pad;By the metal-to-metal bonding between the metal bonding pad of pairing, every pair of vertically adjacent semiconductor package in the vertical stack is bonded with each other;The sidewall of the second semiconductor package is vertically coincident with the sidewall of the first semiconductor package, and is vertically coincident with the sidewall of the third semiconductor package;And one or more of the at least one first semiconductor die, the at least one second semiconductor die and the at least one third semiconductor die include the corresponding sidewall that is laterally offset from the sidewall of the second semiconductor package.

[0006] To let above-mentioned features and advantages of the utility model embodiment can be more obvious and easy to understand, below specific embodiment is held, and cooperation drawing is described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0007] The aspects of the disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0008] Figure 1 is the schematic diagram of a series of processing steps that can be used to form a composite package according to aspects of the disclosure.

[0009] Figure 2 is a vertical cross-sectional view of a silicon-based wafer that can be used during the manufacture of a composite package of the disclosure.

[0010] Figures 3A-3C is a series of vertical cross-sectional views of a first exemplary structure during the formation of a first reconstituted wafer that can be used during the manufacture of a composite package of the disclosure.

[0011] Figures 4A-4C is a series of vertical cross-sectional views of a second exemplary structure during the formation of a second reconstituted wafer that can be used during the manufacture of a composite package of the disclosure.

[0012] Figures 5A-5Lis a vertical cross-sectional view of various configurations of a first composite package according to embodiments of the present disclosure.

[0013] Figures 6A-6L is a vertical cross-sectional view of various configurations of a second composite package according to embodiments of the present disclosure.

[0014] Figures 7A-7D is a vertical cross-sectional view of various configurations of a third composite package according to embodiments of the present disclosure.

[0015] Figures 8A-8D is a vertical cross-sectional view of various configurations of a fourth composite package according to embodiments of the present disclosure.

[0016] Figure 9 is a first flowchart illustrating steps for forming a semiconductor structure according to embodiments of the present disclosure.

[0017] Figure 10 is a second flowchart illustrating steps for forming a semiconductor structure according to embodiments of the present disclosure.

[0018] Figure 11 is a third flowchart illustrating steps for forming a semiconductor structure according to embodiments of the present disclosure.

[0019] BRIEF DESCRIPTION OF DRAWINGS

[0020] 2: semiconductor substrate

[0021] 3: insulating spacer

[0022] 4: substrate via structure

[0023] 5: backside insulating layer

[0024] 10: first semiconductor package

[0025] 11: gap

[0026] 12: semiconductor device

[0027] 14: dielectric material layer

[0028] 16: metal interconnect structure

[0029] 17: molded compound die frame

[0030] 17M: molded compound matrix

[0031] 18: frontside metal bond pad

[0032] 19: backside metal bond pad

[0033] 20: second semiconductor package

[0034] 30 third semiconductor package

[0035] 40 fourth semiconductor package

[0036] 60 handling substrate

[0037] 61 adhesive layer

[0038] 70, 70A, 70B, 70C semiconductor die

[0039] 80 composite package

[0040] 88 solder material portion

[0041] 100 first wafer

[0042] 108 carrier substrate

[0043] 109 first adhesive layer

[0044] 118 reconstituted wafer

[0045] 200 second wafer

[0046] 300 third wafer

[0047] 400 fourth wafer

[0048] 601 first carrier wafer

[0049] 602 second carrier wafer

[0050] A1, A2, A3, A4, A5 auxiliary processing steps

[0051] S1, S2, S3, S4, S5, S6, S7, S8, S9 processing steps

[0052] UA unit area DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features do not form direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0054] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly. Unless otherwise noted, each component having a same reference numeral is assumed to be of the same material composition and to have a thickness in a same range of thicknesses.

[0055] The present disclosure relates to semiconductor structures, and in particular to a method of forming a composite package including a vertical stack of three or more semiconductor dies that can be stacked in a vertical direction using metal-to-metal bonding thereamongst, and a method of forming the same. Different aspects of the present disclosure are described with reference to the accompanying drawings.

[0056] Reference Figure 1A series of processing steps that can be used to form the composite package 80 is shown schematically in accordance with aspects of the present disclosure. In a first processing step SI, a first carrier wafer 601 is provided, which can comprise a circular wafer or a polygonal wafer such as a rectangular wafer. In embodiments in which the first carrier wafer 601 comprises a circular wafer, the diameter of the first carrier wafer 601 can be, for example, 200 millimeters (mm), 300 mm, 450 mm, etc. In general, the first carrier wafer 601 can comprise a semiconductor wafer, an insulative wafer, a conductive wafer, or a composite wafer having sufficient mechanical strength to support additional wafers that are subsequently bonded thereto. The thickness of the first carrier wafer 601 can be in the range of 500 micrometers to 2 millimeters, although lesser and greater thicknesses can also be used. In one embodiment, the first carrier wafer 601 can comprise a commercially available silicon wafer.

[0057] Referring to a first auxiliary processing step Al (and to step 910 of FIG. 9, discussed below), Figure 9 The first wafer 100 is provided. The first wafer 100 comprises a two-dimensional array of first semiconductor dies 70. Each of the first semiconductor dies 70 comprises a respective array of top metal bonding pads configured for metal-to-metal bonding. As used herein, metal-to-metal bonding refers to a bonding method in which two sets of metal bonding pads disposed in two semiconductor dies can be brought into direct contact with one another and can be annealed at an elevated temperature to induce intermetallic diffusion of metal across each interface between pairs of metal bonding pads to an extent that provides a bond between the pairs of metal bonding pads. Metal-to-metal bonding does not use any intervening material, such as a solder material. Rather, the material of the metal that diffuses into the pairs of metal bonding pads causes the bond between the pairs of metal bonding pads. Typical materials that can be used for metal-to-metal bonding include copper, copper alloys, nickel, aluminum, silver, gold, etc.

[0058] In general, the first semiconductor dies 70 can comprise any type of semiconductor die known in the art. For example, the first semiconductor dies 70 can comprise logic dies, system-on-chip dies, memory dies, etc.

[0059] Referring to Figure 2 is shown. The first wafer 100 is provided. The first wafer 100 comprises a two-dimensional array of first semiconductor dies 70. Each of the first semiconductor dies 70 comprises a respective array of top metal bonding pads configured for metal-to-metal bonding. As used herein, metal-to-metal bonding refers to a bonding method in which two sets of metal bonding pads disposed in two semiconductor dies can be brought into direct contact with one another and can be annealed at an elevated temperature to induce intermetallic diffusion of metal across each interface between pairs of metal bonding pads to an extent that provides a bond between the pairs of metal bonding pads. Metal-to-metal bonding does not use any intervening material, such as a solder material. Rather, the material of the metal that diffuses into the pairs of metal bonding pads causes the bond between the pairs of metal bonding pads. Typical materials that can be used for metal-to-metal bonding include copper, copper alloys, nickel, aluminum, silver, gold, etc. Figure 1of the first wafer 100 provided at the first auxiliary processing step Al in FIG. 1. In this example, the first wafer 100 can include a semiconductor-based wafer that includes a semiconductor substrate 2 that extends continuously as a single continuous structure over the entire area of the first wafer 100. As used herein, a semiconductor-based wafer refers to a wafer that includes a single continuous semiconductor substrate having the same lateral extent as the wafer. In this embodiment, the first wafer 100 can be provided as shown in FIG. 2, for example, by providing a semiconductor substrate having a thickness (e.g., a thickness in the range of 500 microns to 1 millimeter); by forming vertically-extending via cavities in the upper portion of the semiconductor substrate having a depth in the range of 5 microns to 30 microns, and filling the vertically-extending via cavities using a combination of insulating spacers 3 and through-substrate via (TSV) structures 4; by forming semiconductor devices 12 on and / or within the upper portion of the semiconductor substrate; by forming metal interconnect structures 16 and frontside metal bonding pads 18 formed within a dielectric material layer 14, and thinning the semiconductor substrate from the backside to provide a semiconductor substrate 2 as shown in FIG. 3; and by forming backside metal bonding pads 19 within a backside insulating layer 5 on the backside of the semiconductor substrate 2. Figure 2 of the first wafer 100 provided at the first auxiliary processing step Al in FIG. 1. In this example, the first wafer 100 can include a semiconductor-based wafer that includes a semiconductor substrate 2 that extends continuously as a single continuous structure over the entire area of the first wafer 100. As used herein, a semiconductor-based wafer refers to a wafer that includes a single continuous semiconductor substrate having the same lateral extent as the wafer. In this embodiment, the first wafer 100 can be provided as shown in FIG. 2, for example, by providing a semiconductor substrate having a thickness (e.g., a thickness in the range of 500 microns to 1 millimeter); by forming vertically-extending via cavities in the upper portion of the semiconductor substrate having a depth in the range of 5 microns to 30 microns, and filling the vertically-extending via cavities using a combination of insulating spacers 3 and through-substrate via (TSV) structures 4; by forming semiconductor devices 12 on and / or within the upper portion of the semiconductor substrate; by forming metal interconnect structures 16 and frontside metal bonding pads 18 formed within a dielectric material layer 14, and thinning the semiconductor substrate from the backside to provide a semiconductor substrate 2 as shown in FIG. 3; and by forming backside metal bonding pads 19 within a backside insulating layer 5 on the backside of the semiconductor substrate 2. Figure 2 of the first wafer 100 provided at the first auxiliary processing step Al in FIG. 1. In this example, the first wafer 100 can include a semiconductor-based wafer that includes a semiconductor substrate 2 that extends continuously as a single continuous structure over the entire area of the first wafer 100. As used herein, a semiconductor-based wafer refers to a wafer that includes a single continuous semiconductor substrate having the same lateral extent as the wafer. In this embodiment, the first wafer 100 can be provided as shown in FIG. 2, for example, by providing a semiconductor substrate having a thickness (e.g., a thickness in the range of 500 microns to 1 millimeter); by forming vertically-extending via cavities in the upper portion of the semiconductor substrate having a depth in the range of 5 microns to 30 microns, and filling the vertically-extending via cavities using a combination of insulating spacers 3 and through-substrate via (TSV) structures 4; by forming semiconductor devices 12 on and / or within the upper portion of the semiconductor substrate; by forming metal interconnect structures 16 and frontside metal bonding pads 18 formed within a dielectric material layer 14, and thinning the semiconductor substrate from the backside to provide a semiconductor substrate 2 as shown in FIG. 3; and by forming backside metal bonding pads 19 within a backside insulating layer 5 on the backside of the semiconductor substrate 2.

[0060] The thickness of the thinned semiconductor substrate 2 can be in the range of 5 microns to 30 microns, and each of the backside metal bonding pads 19 can be formed on a respective one of the TSV structures 4. Conductive paths can be formed between the frontside metal bonding pads 18 and the backside metal bonding pads 19. Each such conductive path can include a respective one of the TSV structures 4. The first wafer 100 can include a two-dimensional periodic repetition of semiconductor dies 70. The semiconductor dies 70 within the first wafer 100 refer to first semiconductor dies 70. The first semiconductor dies 70 are interconnected to one another, and each of the first semiconductor dies 70 includes a respective portion of the semiconductor substrate 2 that extends continuously over the entire area of the first wafer 100.

[0061] Alternatively, the first wafer 100 provided at the first auxiliary processing step Al in FIG. 1 can include a reconstituted wafer. Figure 1 is a continuous schematic vertical cross-sectional view of a first exemplary structure during formation of a first reconstituted wafer 118 that can be used as the first wafer 100. Figures 3A-3C is a continuous schematic vertical cross-sectional view of a first exemplary structure during formation of a first reconstituted wafer 118 that can be used as the first wafer 100.

[0062] Referring to FIG. 1, the first auxiliary processing step Al can include providing a first wafer 100. Figure 3AThe first exemplary structure includes a carrier substrate 108, a first adhesive layer 109 formed on a top surface of the carrier substrate 108, and a two-dimensional array of semiconductor dies 70 bonded to the first adhesive layer 109. The carrier substrate 108 can include an optically transparent substrate, such as a glass substrate or a sapphire substrate. In a top view, the carrier substrate 108 can have a circular shape or a polygonal shape. In embodiments in which the carrier substrate 108 has a circular shape in a top view, the diameter of the carrier substrate 108 can be in a range of 150 mm to 450 mm, although smaller and larger diameters can be used. Additionally, the thickness of the carrier substrate 108 can be in a range of 500 microns to 2,000 microns, although smaller and larger thicknesses can also be used. Alternatively, the carrier substrate 108 can be provided in a rectangular panel form. In such alternative embodiments, the dimensions of the first carrier can be substantially the same.

[0063] The first adhesive layer 109 can be applied to a front side surface of the carrier substrate 108. In one embodiment, the first adhesive layer 109 can be a light-to-heat conversion (LTHC) layer. The LTHC layer can be a solvent-based coating applied using a spin-on method. The LTHC layer can convert ultraviolet light into heat, which can cause the material of the LTHC layer to lose adhesion. Alternatively, the first adhesive layer 109 can include a heat-decomposable adhesive material. For example, the first adhesive layer 109 can include an acrylic pressure sensitive adhesive that decomposes at elevated temperatures. The peel temperature of the heat-decomposable adhesive material can be in a range of 150 degrees Celsius to 200 degrees Celsius.

[0064] The first semiconductor dies 70 can be bonded to the first adhesive layer 109 in a two-dimensional periodic pattern, i.e., as a two-dimensional periodic array of first semiconductor dies 70. The area of a repeating unit is referred to herein as the unit area UA. Each first semiconductor die 70 can include a semiconductor substrate 2, an array of substrate via structures 4, an array of insulative spacers 3, semiconductor devices 12 formed on a top side of the semiconductor substrate 2, metal interconnect structures 16 and front side metal bond pads 18 formed within a dielectric material layer 14, a backside insulative layer 5, and backside metal bond pads 19 formed within the backside insulative layer 5 and contacting a backside surface of a respective one of the TSV structures 4. In one embodiment, the first semiconductor dies 70 can be provided by dicing a wafer having substantially the same structure as the first wafer 100 described above into discrete semiconductor dies. The first semiconductor dies 70 can include logic dies, system-on-chip (SoC) dies, memory dies, or any other type of semiconductor die known in the art. The gaps 11 between the first semiconductor dies 70 bonded to the first adhesive layer 109 in the two-dimensional periodic pattern can provide spacing and isolation between adjacent pairs of first semiconductor dies 70.

[0065] Referring to Figure 3B The molding compound can be applied to the gaps 11 between adjacent pairs of semiconductor dies 70. The molding compound can include an epoxy-based compound that can be hardened (i.e., cured) to provide a dielectric material portion having sufficient rigidity and mechanical properties. The molding compound can include an epoxy resin, a hardener, silica as a filler material, and other additives. Depending on the viscosity and flowability, the molding compound can be provided in a liquid form or in a solid form. The liquid molding compound provides better handling, good flowability, fewer voids, better filling, and fewer flow marks. The solid molding compound provides less cure shrinkage, better stand-off, and less die drift. A high filler content (e.g., 85% by weight) in the molding compound can shorten the time in the mold, reduce mold shrinkage, and reduce mold warpage. A uniform filler size distribution in the molding compound can reduce flow marks and can enhance flowability. In embodiments in which the adhesive layer includes a thermal release material, the curing temperature of the molding compound can be lower than the release temperature of the first adhesive layer 109. For example, the curing temperature of the molding compound can be in the range of 125 °C to 150 °C.

[0066] The molding compound can be cured at a curing temperature to form a molding compound matrix 17M laterally surrounding the two-dimensional array of semiconductor dies 70. The molding compound matrix 17M includes a plurality of molding compound die frames interconnected to each other. Each molding compound die frame is a portion of the molding compound matrix 17M that is located within the area of a repeating unit within the structure covering the two-dimensional periodic array of carrier substrates 108. Thus, each molding compound die frame laterally surrounds and embeds a respective semiconductor die 70. The Young's modulus of pure epoxy is about 3.35 GPa, and by adding additives, the Young's modulus of the molding compound can be higher than the Young's modulus of pure epoxy. The Young's modulus of the molding compound can be greater than 3.5 GPa. In some embodiments, suitable alternative molding materials can be used for the molding compound matrix 17M.

[0067] Portions of the molding compound matrix 17M covering the horizontal plane including the top surfaces of the semiconductor dies 70 can be removed by a planarization process. For example, chemical mechanical planarization (CMP) can be used to remove portions of the molding compound matrix 17M covering the horizontal plane. The remaining portions of the molding compound matrix 17M and the semiconductor dies 70 in combination include a reconstituted wafer 118. Each portion of the molding compound matrix 17M located within the unit area UA constitutes a molding compound die frame.

[0068] Referring to Figure 3CThe first adhesive layer 109 can be decomposed by ultraviolet radiation or by thermal annealing at a release temperature. In embodiments where the carrier substrate 108 comprises an optically transparent material and the first adhesive layer 109 comprises an LTHC layer, the first adhesive layer 109 can be decomposed by shining ultraviolet light through the transparent carrier substrate. The LTHC layer can absorb the ultraviolet radiation and generate heat, which decomposes the material of the LTHC layer and causes the transparent carrier substrate 108 to separate from the reconstituted wafer 118. In embodiments where the first adhesive layer 109 comprises a thermally decomposable adhesive material, a thermal annealing process at a release temperature can be performed to separate the carrier substrate 108 from the reconstituted wafer 118 when using an adhesive material. The separated reconstituted wafer 118 can be used as the first wafer 100 provided at the auxiliary processing step Al in Figure 1 .

[0069] In some embodiments, the reconstituted wafer 118 used as the first wafer 100 at the first auxiliary processing step Al shown in Figure 1 may comprise a plurality of semiconductor dies 70 and / or at least one optional dummy die per unit area UA. Figures 4A-4C is a continuous schematic vertical cross-sectional view of a second exemplary structure during formation of a second reconstituted wafer 118 that can be used as the first wafer 100.

[0070] Referring to Figure 4A , the second exemplary structure can be derived from the first exemplary structure shown in FIG. 3 by replacing the single semiconductor die 70 per unit area UA in the first exemplary structure of Figure 3A with a plurality of semiconductor dies (70A, 70B, 70C) per unit area UA. In this embodiment, the plurality of semiconductor dies (70A, 70B, 70C) per unit area UA includes at least a first type of semiconductor die 70A, a second type of semiconductor die 70B, and an optional third type of semiconductor die 70C, and includes an additional semiconductor wafer (not shown). Each of the semiconductor dies 70 within the unit area UA can comprise a logic die, a system-on-chip (SoC) die, a memory die, a bridge die, a die, or any other type of semiconductor die known in the art. Alternatively, one or more of the plurality of semiconductor dies (70A, 70B, 70C) can be replaced with a dummy die, which is a non-functional die used to facilitate the planarization process of the planarization molding compound matrix. 17M. For example, one or more of the second type of semiconductor die 70B, the optional third type of semiconductor die 70C, and the optional additional semiconductor die (not shown) can be replaced with a dummy die. Such embodiments are expressly contemplated herein.

[0071] Each of the plurality of semiconductor dies (70A, 70B, 70C) can include a semiconductor substrate 2, an optional array of through-substrate via (TSV) structures 4, an optional array of insulating spacers 3, an optional semiconductor device 12 formed on a top side of the semiconductor substrate 2, a metal interconnect structure 16 and front side metal bonding pads 18 formed within a dielectric material layer 14, a back side insulating layer 5, and back side metal bonding pads 19 formed within the back side insulating layer 5 and contacting a back side surface of a respective one of the TSV structures 4. At least one, a plurality, and / or each of the plurality of semiconductor dies (70A, 70B, 70C) can include a respective array of through-substrate via (TSV) structures 4 and a respective array of insulating spacers 3. At least one, a plurality, and / or each of the plurality of semiconductor dies (70A, 70B, 70C) can include a respective set of semiconductor devices 12.

[0072] Referring to Figure 4B , the first wafer 100 can be attached to a top surface of the first carrier wafer 601, e.g., using an adhesive layer (not shown). The adhesive layer can include a UV-decomposable adhesive material or a heat-decomposable adhesive material. In general, the first wafer 100 including the two-dimensional array of first semiconductor dies 70 can be attached to the first carrier wafer 601. The two-dimensional array of first semiconductor dies 70 includes an array of physically exposed first top metal bonding pads and an array of first bottom metal bonding pads that face the top surface of the first carrier wafer 601 and are in contact with the adhesive layer. Figure 3B The described processing steps to form a matrix 17M of molding compound laterally surrounding each semiconductor die 70 over the carrier substrate 108.

[0073] Referring to Figure 4C , the first wafer 100 can be attached to a top surface of the first carrier wafer 601, e.g., using an adhesive layer (not shown). The adhesive layer can include a UV-decomposable adhesive material or a heat-decomposable adhesive material. In general, the first wafer 100 including the two-dimensional array of first semiconductor dies 70 can be attached to the first carrier wafer 601. The two-dimensional array of first semiconductor dies 70 includes an array of physically exposed first top metal bonding pads and an array of first bottom metal bonding pads that face the top surface of the first carrier wafer 601 and are in contact with the adhesive layer. Figure 3C The described processing steps to separate the reconstituted wafer 118 from the carrier substrate 108. The reconstituted wafer 118 can be used as the first wafer 100 provided at the auxiliary processing step Al in Figure 1

[0074] Referring to Figure 1 , the first wafer 100 can be attached to a top surface of the first carrier wafer 601, e.g., using an adhesive layer (not shown). The adhesive layer can include a UV-decomposable adhesive material or a heat-decomposable adhesive material. In general, the first wafer 100 including the two-dimensional array of first semiconductor dies 70 can be attached to the first carrier wafer 601. The two-dimensional array of first semiconductor dies 70 includes an array of physically exposed first top metal bonding pads and an array of first bottom metal bonding pads that face the top surface of the first carrier wafer 601 and are in contact with the adhesive layer. Figure 9 In one embodiment, the array of first top metal bonding pads includes an array of front side metal bonding pads 18 formed within a dielectric material layer 14, and the array of first bottom metal bonding pads includes an array of back side metal bonding pads 19 formed within a respective back side insulating layer 5. In this embodiment, the first semiconductor dies 70 are positioned such that the front side metal bonding pads 18 face upward and the back side metal bonding pads 19 face downward.

[0075]

[0076] ​​In another embodiment, the array of first top metal bonding pads comprises an array of backside metal bonding pads 19 formed within a respective backside insulating layer 5, and the array of first bottom metal bonding pads comprises an array of frontside metal bonding pads 18 formed within a dielectric material layer 14. In this embodiment, the first semiconductor dies 70 can be positioned such that the backside metal bonding pads 19 face upwards and the frontside metal bonding pads 18 face downwards.

[0077] In general, the first wafer 100 comprising a two-dimensional array of first semiconductor dies 70 can be bonded to a top surface of the first carrier wafer 601, the two-dimensional array of first semiconductor dies 70 comprising an array of first top metal bonding pads (18, 19) and an array of first bottom metal bonding pads (18, 19). The first wafer 100 can comprise a semiconductor-based wafer as shown in Figure 2 , or can comprise a reconstituted wafer 118 as shown in Figure 3C or 4C.

[0078] Referring to the second auxiliary processing step A2 as shown in Figure 1 , a second wafer 200 is provided (see also step 920 in Figure 9 ). The second wafer 200 comprises a two-dimensional array of second semiconductor dies 70, the two-dimensional array of second semiconductor dies 70 comprising an array of second top metal bonding pads and an array of second bottom metal bonding pads. In general, the second wafer 200 can have a semiconductor-based wafer as shown in Figure 2 , or can be a reconstituted wafer 118 as shown in Figure 3C and 4C . In other words, any semiconductor-based wafer as shown in Figure 2 or a reconstituted wafer 118 as shown in Figure 3C and 4C may be used for the second wafer 200. Thus, any type of wafer that can be used for the first wafer 100 can be used as the second wafer 200.

[0079] Referring to the third processing step S3 as shown in Figure 1 , a third wafer 300 is provided (see also step 930 in Figure 9The second wafer 200 can be bonded to the first wafer 100 by performing a first metal-to-metal bonding process (step 930 in FIG. 9). The array of first top metal bonding pads (18 or 19) in the first wafer 100 is bonded to the array of second bottom metal bonding pads (18 or 19) in the second wafer 200 by inter-diffusion of the first metal. In one embodiment, the first top metal bonding pads (18 or 19) in the first wafer 100 can be copper bonding pads, the array of second bottom metal bonding pads (18 or 19) in the second wafer 200 can be additional copper bonding pads, and the metal-to-metal bonding can be copper-to-copper bonding. In addition, a dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding, can be performed between the topmost insulating layer of the first wafer 100 and the bottommost insulating layer of the second wafer 200.

[0080] In one embodiment, the first top metal bonding pads in the first wafer 100 can include first frontside metal bonding pads 18 formed within the dielectric material layer 14 of the first wafer 100, and the second bottom metal bonding pads in the second wafer 200 can include second backside metal bonding pads 19 formed within the backside insulating layer 5 of the second wafer 200. In this embodiment, the dielectric-to-dielectric bonding between the dielectric material layer 14 of the first wafer 100 and the backside insulating layer 5 of the second wafer 200 can be performed simultaneously with the metal-to-metal bonding.

[0081] In another embodiment, the first top metal bonding pads in the first wafer 100 can include first frontside metal bonding pads 18 formed within the dielectric material layer 14 of the first wafer 100, and the second bottom metal bonding pads in the second wafer 200 can include second frontside metal bonding pads 18 formed within the dielectric material layer 14 of the second wafer 200. In this embodiment, the dielectric-to-dielectric bonding between the dielectric material layer 14 of the first wafer 100 and the dielectric material layer 14 of the second wafer 200 can be performed simultaneously with the metal-to-metal bonding.

[0082] In yet another embodiment, the first top metal bonding pads in the first wafer 100 can include first backside metal bonding pads 19 formed within the backside insulating layer 5 of the first wafer 100, and the second bottom metal bonding pads in the second wafer 200 can include second backside metal bonding pads 19 formed within the backside insulating layer 5 of the second wafer 200. In this embodiment, the dielectric-to-dielectric bonding between the backside insulating layer 5 of the first wafer 100 and the backside insulating layer 5 of the second wafer 200 can be performed simultaneously with the metal-to-metal bonding.

[0083] In yet another embodiment, the first top metal bonding pads in the first wafer 100 can comprise first backside metal bonding pads 19 formed within the backside insulating layer 5 of the first wafer 100, and the second bottom metal bonding pads in the second wafer 200 can comprise second frontside metal bonding pads 18 formed within the dielectric material layer 14 of the second wafer 200. In this embodiment, the dielectric-to-dielectric bonding between the backside insulating layer 5 of the first wafer 100 and the dielectric material layer 14 of the second wafer 200 can be performed simultaneously with the metal-to-metal bonding.

[0084] Generally, the array of first semiconductor dies 70 in the first wafer 100 and the array of second semiconductor dies 70 in the second wafer 200 can have the same shape per unit area UA, and can have the same two-dimensional periodicity. Generally, by performing the first metal-to-metal bonding process, a second wafer 200 comprising a two-dimensional array of second semiconductor dies 70 comprising an array of second top metal bonding pads (18 or 19) and an array of second bottom metal bonding pads (18 or 19) can be bonded to the first wafer, wherein the array of first top metal bonding pads (18 or 19) is bonded to the array of second bottom metal bonding pads (18, 19) by intermetallic diffusion.

[0085] Reference is made to the third auxiliary processing step A3 shown in Figure 1 Reference is made to the third auxiliary processing step A3 shown in Figure 9 The third wafer 300 comprises a two-dimensional array of third semiconductor dies 70 comprising an array of third top metal bonding pads and an array of third bottom metal bonding pads. Generally, the third wafer 300 can have the same shape per unit area UA as the first wafer 100 and the second wafer 200, and can have the same two-dimensional periodicity as the first wafer 100 and the second wafer 200. Figure 2 The third wafer 300 can be a semiconductor-based wafer as shown in Figure 3C and 4C The third wafer 300 can be a reconstituted wafer 118 as shown in Figure 2 The third wafer 300 can be a semiconductor-based wafer as shown in Figure 3C and 4C The third wafer 300 can be a reconstituted wafer 118 as shown in

[0086] Reference is made to the fourth processing step S4 shown in Figure 1 Reference is made to the fourth processing step S4 shown in Figure 9The third wafer 300 can be bonded to the second wafer 200 by performing a second metal-to-metal bonding process (step 950 in FIG. 9), in which the array of second top metal bonding pads (18 or 19) in the second wafer 200 is bonded to the array of third bottom metal bonding pads (18 or 19) in the third wafer 300 by interdiffusion of the second metal. In one embodiment, the second top metal bonding pads (18 or 19) in the second wafer 200 can be copper bonding pads, the array of third bottom metal bonding pads (18 or 19) in the third wafer 300 can be additional copper bonding pads, and the metal-to-metal bonding can be copper-to-copper bonding. In addition, a dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding, can be performed between the topmost insulating layer of the second wafer 200 and the bottommost insulating layer of the third wafer 300.

[0087] In one embodiment, the second top metal bonding pads in the second wafer 200 can include second frontside metal bonding pads 18 formed within the dielectric material layer 14 of the second wafer 200, and the third bottom metal bonding pads in the third wafer 300 can include third backside metal bonding pads 19 formed within the backside insulating layer 5 of the third wafer 300. In this embodiment, the dielectric-to-dielectric bonding between the dielectric material layer 14 of the second wafer 200 and the backside insulating layer 5 of the third wafer 300 can be performed simultaneously with the metal-to-metal bonding.

[0088] In another embodiment, the second top metal bonding pads in the second wafer 200 can include second frontside metal bonding pads 18 formed within the dielectric material layer 14 of the second wafer 200, and the third bottom metal bonding pads in the third wafer 300 can include third frontside metal bonding pads 18 formed within the dielectric material layer 14 of the third wafer 300. In this embodiment, the dielectric-to-dielectric bonding between the dielectric material layer 14 of the second wafer 200 and the dielectric material layer 14 of the third wafer 300 can be performed simultaneously with the metal-to-metal bonding.

[0089] In yet another embodiment, the second top metal bonding pads in the second wafer 200 can include second backside metal bonding pads 19 formed within the backside insulating layer 5 of the second wafer 200, and the third bottom metal bonding pads in the third wafer 300 can include third backside metal bonding pads 19 formed within the backside insulating layer 5 of the third wafer 300. In this embodiment, the dielectric-to-dielectric bonding between the backside insulating layer 5 of the second wafer 200 and the backside insulating layer 5 of the third wafer 300 can be performed simultaneously with the metal-to-metal bonding.

[0090] In yet another embodiment, the second top metal bonding pads in the second wafer 200 can comprise second backside metal bonding pads 19 formed within a backside insulating layer 5 of the second wafer 200, and the third bottom metal bonding pads in the third wafer 300 can comprise third frontside metal bonding pads 18 formed within a dielectric material layer 14 of the third wafer 300. In this embodiment, the dielectric-to-dielectric bonding between the backside insulating layer 5 of the second wafer 200 and the dielectric material layer 14 of the third wafer 300 can be performed simultaneously with the metal-to-metal bonding.

[0091] In general, the array of second semiconductor dies 70 in the second wafer 200 and the array of third semiconductor dies 70 in the third wafer 300 can have the same shape per unit area UA, and can have the same two-dimensional periodicity. In general, by performing the second metal-to-metal bonding process, a third wafer 300 comprising a two-dimensional array of third semiconductor dies 70 comprising an array of third top metal bonding pads (18 or 19) and an array of third bottom metal bonding pads (18 or 19) can be bonded to the second wafer, where the array of second top metal bonding pads (18 or 19) is bonded to the array of third bottom metal bonding pads (18, 19) by intermetallic diffusion.

[0092] Referring to the fourth auxiliary processing step A4, at least one semiconductor-based wafer comprising a plurality of semiconductor dies 70 can be provided. In an illustrative example, a first semiconductor-based wafer comprising a two-dimensional array of first-type semiconductor dies 70A and a second semiconductor-based wafer comprising a two-dimensional array of second-type semiconductor dies 70B can be provided. Optionally, at least one additional semiconductor-based wafer (not shown) comprising a two-dimensional array of additional semiconductor dies (e.g., of a third type) can be provided. Each of the first-type semiconductor wafer 70A, the second-type semiconductor wafer 70B, the third-type semiconductor wafer, etc. can have a respective shape that is smaller than the shape of the unit area UA within the first wafer 100, the second wafer 200, and the third wafer 300.

[0093] Referring to the fifth auxiliary processing step A5, the semiconductor-based wafers can be diced along dicing lanes to provide various types of semiconductor dies 70, which can include first-type semiconductor dies 70A, second-type semiconductor dies 70B, optional third-type semiconductor dies (not shown), etc. In general, each of the first-type semiconductor dies 70A, the second-type semiconductor dies 70B, the optional third-type semiconductor dies, etc. can independently comprise any type of semiconductor die known in the art, and can include, for example, logic dies, system-on-chip (SoC) dies, memory dies, bridge dies, integrated passive device dies, etc.

[0094] In one embodiment, each semiconductor die (70A, 70B, 70C) within the set of multiple semiconductor dies 70 can include a semiconductor substrate 2, an optional array of through-substrate via (TSV) structures 4, an optional array of insulating spacers 3, an optional semiconductor device 12 formed on a top side of the semiconductor substrate 2, a metal interconnect structure 16 and front side metal bonding pads 18 formed within a dielectric material layer 14, a backside insulating layer 5 formed within the optional backside insulating layer 5 and contacting a backside surface of a respective one of the optional TSV structures 4, and optional backside metal bonding pads 19. Generally, in embodiments where TSV structures 4 are present in the semiconductor dies (70A, 70B, 70C), the backside insulating layer 5 is present in the semiconductor dies (70A, 70B, 70C) shown in FIG. 5. In embodiments where TSV structures 4 are not present in the semiconductor dies (70A, 70B, 70C), the backside metal bonding pads 19 are not present in the semiconductor dies (70A, 70B, 70C) shown in FIG. 5.

[0095] Referring to the fifth processing step S5, a set of multiple semiconductor dies 70, such as a combination of first-type semiconductor dies 70A, second-type semiconductor dies 70B, and third-type semiconductor dies 70C, can be bonded to at least one third semiconductor die 70 within a respective unit area UA in the third wafer 300. By metal-to-metal bonding, each semiconductor die (70A, 70B, 70C) within the set of multiple semiconductor dies 70 can be bonded to at least one third semiconductor die 70 within a respective unit area UA. Thus, no adhesive layer is used at this processing step.

[0096] Each semiconductor die (70A, 70B, 70C) within the set of multiple semiconductor dies 70 can be bonded to a respective set of physically exposed metal bonding pads (18 or 19) of the respective semiconductor die 70 in the third wafer 300 through the front side metal bonding pads 18 of the respective semiconductor die (70A, 70B, 70C), or can be bonded to a respective set of physically exposed metal bonding pads (18 or 19) of the respective semiconductor die 70 in the third wafer 300 through the backside metal bonding pads 19 (if present) of the respective semiconductor die (70A, 70B, 70C).

[0097] A two-dimensional periodic array of multiple sets of semiconductor dies (70A, 70B, 70C) can be positioned over the third wafer 300. Subsequently, the two-dimensional periodic array of multiple sets of semiconductor dies (70A, 70B, 70C) can be pressed against the third wafer 300, and the assembly of the first carrier wafer 601, the first wafer 100, the second wafer 200, the third wafer 300, and the two-dimensional periodic array of multiple sets of semiconductor wafers (70A, 70B, 70C) can be annealed at an elevated temperature, for example, in the range of 200 to 400 degrees Celsius, to provide metal-to-metal bonding between the two-dimensional periodic array of multiple sets of semiconductor dies (70A, 70B, 70C) and the two-dimensional array of third semiconductor dies 70. Alternatively, a dielectric-to-dielectric bond, for example, a silicon oxide-to-silicon oxide bond, can be used between the physically exposed dielectric layer of the third wafer 300 and the bottom side dielectric layer of the semiconductor dies (70A, 70B, 70C).

[0098] With reference to the sixth processing step S6, the processing steps described with reference to Figure 4B and 4C may be performed to form a matrix of molding compound around the two-dimensional array of multiple sets of multiple semiconductor dies (70A, 70B, 70C). A fourth wafer 400 can be attached to the third wafer 300. The fourth wafer 400 can be a reconstituted wafer.

[0099] In general, by performing a third metal-to-metal bonding process, a fourth wafer 400 including a two-dimensional array of fourth semiconductor dies 70 can be attached to the third wafer 300, the two-dimensional array of fourth semiconductor dies 70 including an array of fourth bottom metal bonding pads (18, 19) bonded to the array of third top metal bonding pads (18, 19) by third intermetallic diffusion.

[0100] While the disclosure is described using an embodiment in which the first wafer 100, the second wafer 200, and the third wafer 300 are provided prior to bonding to an underlying wafer, and the fourth wafer 400 is assembled over the third wafer by separately using metal-to-metal bonding to attach the semiconductor dies (70A, 70B, 70C), each of the second wafer 200 and the third wafer 300 can be assembled over a respective underlying wafer by attaching the second semiconductor dies 70 or the third semiconductor dies 70 to the respective underlying wafer, and by forming a matrix of molding compound. Further, the fourth wafer 400 can be provided as a semiconductor-based wafer as shown in Figure 2 or as a reconstituted wafer as shown in Figure 3C or 4C. All such variations are expressly contemplated herein.

[0101] Furthermore, embodiments are explicitly contemplated in which any of the first wafer 100, the second wafer 200, the third wafer 300, or the fourth wafer 400 is omitted. Additionally, embodiments are explicitly contemplated in which at least one additional wafer (not shown) comprising a respective two-dimensional periodic array of semiconductor dies is attached to and bonded to the bonded assembly of the first carrier wafer 601, the first wafer 100, the second wafer 200, the third wafer 300, and the fourth wafer 400. In general, the present disclosure can be implemented with at least three wafers, each wafer comprising a respective two-dimensional periodic array of semiconductor dies 70.

[0102] It should be noted that ordinal numbers such as "first," "second," "third," and "fourth" are not part of the component names, but are merely adjectives. Thus, the first wafer 100 described in the specification can be referred to as the first wafer, the second wafer, the third wafer, or the ith wafer, where i is an integer greater than 3. Similarly, the second wafer 200 described in the specification can be referred to as the first wafer, the second wafer, the third wafer, or the jth wafer, where j is an integer greater than 3. Similarly, the third wafer 300 described in the specification can be referred to as the first wafer, the second wafer, the third wafer, or the kth wafer, where k is an integer greater than 3. Similarly, the fourth wafer 400 described in the specification can be referred to as the first wafer, the second wafer, the third wafer, or the lth wafer, where l is an integer greater than 3.

[0103] Each unit area UA in the first wafer 100 can include only a single first semiconductor die 70 or multiple first semiconductor dies 70. Each unit area UA in the second wafer 200 can include only a single second semiconductor die 70 or multiple second semiconductor dies 70. Each unit area UA in the third wafer 300 can include only a single third semiconductor die 70 or multiple third semiconductor dies 70. Each unit area UA in the fourth wafer 400 can include only a single fourth semiconductor die 70 or multiple fourth semiconductor dies 70. In embodiments in which each unit area UA in any wafer (100, 200, 300, or 400) contains multiple semiconductor dies 70, the multiple semiconductor dies 70 can include first-type semiconductor dies 70A and second-type semiconductor dies 70B. In this embodiment, the semiconductor dies in this wafer (100, 200, 300, 400) include both first-type semiconductor dies 70A and second-type semiconductor dies 70B.

[0104] In the illustrative example, in embodiments in which each unit area UA in the third wafer 300 includes a first-type semiconductor die 70A and a second-type semiconductor die 70B, a third semiconductor die 70 in the third wafer 300 includes a first-type semiconductor die 70A and a second-type semiconductor die 70B. In this embodiment, the two-dimensional array of third semiconductor dies 70 includes a two-dimensional periodic array of repeating units, the repeating units including a combination of a first-type semiconductor die 70A and a second-type semiconductor die 70B that is different from the first-type semiconductor die 70A. The same features apply to each of the first wafer 100, the second wafer 200, the fourth wafer 400, and any additional wafers (if present) that include an array of semiconductor dies 70.

[0105] In some embodiments, at least one of the first wafer 100, the second wafer 200, the third wafer 300, and the fourth wafer 400 can include a reconfigured wafer 118. In one embodiment, a first one of the first wafer 100, the second wafer 200, and the third wafer 300 can include a reconfigured wafer 118 in which a matrix of molding compound 17M laterally surrounds a first two-dimensional array selected from the two-dimensional array of first semiconductor dies 70, the two-dimensional array of second semiconductor dies 70, and the two-dimensional array of third semiconductor dies 70. In one embodiment, a second one of the first wafer 100, the second wafer 200, and the third wafer 300 includes an additional reconfigured wafer in which an additional matrix of molding compound 17M laterally surrounds a second two-dimensional array selected from the two-dimensional array of first semiconductor dies 70, the two-dimensional array of second semiconductor dies 70, and the two-dimensional array of third semiconductor dies 70. In one embodiment, a third one of the first wafer 100, the second wafer 200, and the third wafer 300 includes yet another additional reconfigured wafer in which yet another additional matrix of molding compound 17M laterally surrounds a third two-dimensional array selected from the two-dimensional array of first semiconductor dies 70, the two-dimensional array of second semiconductor dies 70, and the two-dimensional array of third semiconductor dies 70.

[0106] In the illustrative example, the third wafer 300 includes a reconfigured wafer in which the third semiconductor dies 70 are laterally surrounded by a matrix of molding compound 17M. In another illustrative example, the second wafer 200 includes an additional reconfigured wafer in which the second semiconductor dies 70 are laterally surrounded by an additional matrix of molding compound 17M. In yet another illustrative example, the first wafer 100 includes yet another additional reconfigured wafer in which the first semiconductor dies 70 are laterally surrounded by yet another additional matrix of molding compound 17M.

[0107] In an illustrative example, the two-dimensional array of third semiconductor dies 70 in the third wafer 300 includes a two-dimensional periodic array of repeating units that include a combination of a first-type semiconductor die 70A and a second-type semiconductor die 70B that is different from the first-type semiconductor die 70A. In another illustrative example, the two-dimensional array of second semiconductor dies 70 in the second wafer 200 includes a two-dimensional periodic array of repeating units that include a combination of an additional first-type semiconductor die 70A and an additional second-type semiconductor die 70B that is different from the first-type semiconductor die 70A. In yet another illustrative example, the two-dimensional array of fourth semiconductor dies 70 in the fourth wafer 400 includes a two-dimensional periodic array of repeating units that include a combination of yet another additional first-type semiconductor die 70A and yet another additional second-type semiconductor die 70B that is different from the first-type semiconductor die 70A. The first-type semiconductor dies 70A and the second-type semiconductor dies 70B within the same unit area UA in the same wafer (100, 200, 300, 400) can differ from each other in design, size, and / or functionality.

[0108] Referring to a seventh processing step S7, a second carrier wafer 602 can be optionally attached to the topmost wafer (e.g., the fourth wafer 400) in the bonded assembly of the first carrier wafer 601 and the at least three wafers (100, 200, 300) that include respective two-dimensional periodic arrays of semiconductor dies 70. The second carrier wafer 602 can be attached to the topmost wafer, for example, through an adhesive layer (not shown). The second carrier wafer 602 can include any material that can be used for the first carrier wafer 601.

[0109] Referring to an eighth processing step S8, the first carrier wafer 601 can be separated from the assembly of the at least three wafers (100, 200, 300, 400) and the optional second carrier wafer 602. For example, the adhesive layer between the first carrier wafer 601 and the first wafer 100 can be decomposed by ultraviolet radiation or by a thermal annealing at a peeling temperature. In embodiments in which the first carrier wafer 601 includes an optically transparent material and the adhesive layer thereon includes an LTHC layer, the adhesive layer can be decomposed by shining ultraviolet light through the transparent carrier substrate. In embodiments in which the adhesive layer includes a thermally decomposable adhesive material, the thermal annealing process can be performed at a peeling temperature that is higher than the metal-to-metal bonding temperature used to form the bonded assembly (100, 200, 300, 400, optionally 602).

[0110] Upon separation of the first carrier wafer 601 from the bonded assembly (100, 200, 300, optionally 400, optionally 602), first bottom metal bonding pads of the first semiconductor dies 70 in the first wafer 100 can be physically exposed. The physically exposed first bottom metal bonding pads can include backside metal bonding pads 19 of the first semiconductor dies 70, or can include frontside metal bonding pads 18 of the first semiconductor dies 70. An array of solder material portions (not shown) can be affixed to the array of first bottom metal bonding pads.

[0111] Referring to a ninth processing step S9, the bonded assembly (100, 200, 300, optionally 400, optionally 602) including at least the first wafer 100, the second wafer 200, and the third wafer 300 can be singulated into a plurality of composite packages 80. Each of the composite packages 80 can include a respective one (or more) of the first semiconductor dies 70, a respective one (or more) of the second semiconductor dies 70, a respective one (or more) of the third semiconductor dies 70, an optional respective one (or more) of the fourth semiconductor dies 70, and an optional respective operative substrate 6 of the second carrier wafer 602, which is a singulated portion of the second carrier wafer 602 (in embodiments in which the second carrier wafer 602 is singulated during the singulation step). Alternatively, the second carrier wafer 602 can be singulated prior to the singulation step. In this embodiment, each of the composite packages 80 can include a respective one (or more) of the first semiconductor dies 70, a respective one (or more) of the second semiconductor dies 70, a respective one (or more) of the third semiconductor dies 70, and an optional respective one (or more) of the fourth semiconductor dies 70.

[0112] The composite packages 80 of the present disclosure can be provided according to various architectures of each wafer (100, 200, 300, 400) and the total number of wafers (100, 200, 300, 400) in the bonded assembly that are singulated. Figures 5A-5L is a vertical cross-sectional view of various architectures of a first composite package 80 according to embodiments of the present disclosure. Figures 6A-6L is a vertical cross-sectional view of various architectures of a second composite package 80 according to embodiments of the present disclosure. Figures 7A-7D is a vertical cross-sectional view of various architectures of a third composite package 80 according to embodiments of the present disclosure. Figures 8A-8D is a vertical cross-sectional view of various architectures of a fourth composite package 80 according to embodiments of the present disclosure.

[0113] Referring to a ninth processing step S9, the bonded assembly (100, 200, 300, optionally 400, optionally 602) including at least the first wafer 100, the second wafer 200, and the third wafer 300 can be singulated into a plurality of composite packages 80. Each of the composite packages 80 can include a respective one (or more) of the first semiconductor dies 70, a respective one (or more) of the second semiconductor dies 70, a respective one (or more) of the third semiconductor dies 70, an optional respective one (or more) of the fourth semiconductor dies 70, and an optional respective operative substrate 6 of the second carrier wafer 602, which is a singulated portion of the second carrier wafer 602 (in embodiments in which the second carrier wafer 602 is singulated during the singulation step). Alternatively, the second carrier wafer 602 can be singulated prior to the singulation step. In this embodiment, each of the composite packages 80 can include a respective one (or more) of the first semiconductor dies 70, a respective one (or more) of the second semiconductor dies 70, a respective one (or more) of the third semiconductor dies 70, and an optional respective one (or more) of the fourth semiconductor dies 70. Figures 5A-5LEach cut portion in the first wafer 100 constitutes a first semiconductor package 10; each cut portion in the second wafer 200 constitutes a second semiconductor package 20; each cut portion in the third wafer 300 constitutes a third semiconductor package 30; and each cut portion in the fourth wafer 400 constitutes a fourth semiconductor package 40. Each first semiconductor package includes at least one first semiconductor die 70; each second semiconductor package includes at least one second semiconductor die 70; each third semiconductor package includes at least one third semiconductor die 70; and each fourth semiconductor package includes at least one fourth semiconductor die 70.

[0114] Each semiconductor package (10, 20, 30, 40) includes at least one semiconductor die 70. Each semiconductor package (10, 20, 30, 40) can consist of a single semiconductor die 70, or can include a mold compound die frame 17 and at least one semiconductor die 70 (which can be a single semiconductor die 70 or multiple semiconductor dies 70), where the at least one semiconductor die 70 is laterally surrounded by the mold compound die frame 17.

[0115] Each first semiconductor package 10 can or can not include a mold compound die frame 17; each second semiconductor package 20 can or can not include a mold compound die frame 17; each third semiconductor package 30 can or can not include a mold compound die frame 17; and each fourth semiconductor package 40 can or can not include a mold compound die frame 17. Each mold compound die frame 17 includes a cut portion of a respective mold compound matrix. The sidewalls of the first semiconductor package 10, the second semiconductor package 20, the third semiconductor package 30, and the fourth semiconductor package 40 (if present) within the same composite package 80 vertically coincide. As used herein, first and second surfaces vertically coincide with each other if a second surface overlies or underlies a first surface and if a vertical plane including the first surface and the second surface exists.

[0116] Reference is made to Figures 5A-5L FIGS. 1A-1L, 2A-2L, 3A-3L, and 4A-4L illustrate various architectures of a first composite package 80 according to embodiments of the present disclosure. The first composite package 80 includes a vertical stack of a first semiconductor package 10, a second semiconductor package 20, a third semiconductor package 30, a fourth semiconductor package 40, an adhesive layer 61, and an operational substrate 60.

[0117] Figure 5A The architectures illustrated in FIGS. 1A-1L, 2A-2L, 3A-3L, and 4A-4L correspond to embodiments in which each of the first wafer 100, the second wafer 200, the third wafer 300, and the fourth wafer 400 includes a respective reconfigured wafer 118, which can be as described with reference to Figures 3A-3C, 4A-4C, or a combination of the fifth processing step S5 and the sixth processing step S6. As described above, each of the first wafer 100, the second wafer 200, the third wafer 300, and the fourth wafer 400 can use any of the references Figures 3A-3C the processing steps described or references to a combination of the fifth processing step S5 and the sixth processing step S6. Figures 4A-4C the processing steps described or references to a combination of the fifth processing step S5 and the sixth processing step S6.

[0118] Figure 5B The architecture shown in FIG. 1 corresponds to the first wafer 100 including references to Figure 2 the semiconductor-based wafers described and each of the second wafer 200, the third wafer 300, and the fourth wafer 400 include embodiments of respective reconstituted wafers 118, which can be as described with reference to Figures 3A-3C , 4A-4C, or a combination of the fifth processing step S5 and the sixth processing step S6.

[0119] Figure 5C The architecture shown in FIG. 1 corresponds to each of the first wafer 100 and the second wafer 200 including references to Figure 2 the respective semiconductor-based wafers described and each of the third wafer 300 and the fourth wafer 400 include embodiments of respective reconstituted wafers 118, which can be as described with reference to Figures 3A-3C , 4A-4C, or a combination of the fifth processing step S5 and the sixth processing step S6.

[0120] Figure 5D The architecture shown in FIG. 1 corresponds to each of the first wafer 100, the second wafer 200, and the third wafer 300 including references to Figure 2 the respective semiconductor-based wafers described and the fourth wafer 400 include embodiments of reconstituted wafers 118, which can be as described with reference to Figures 3A-3C , 4A-4C, or a combination of the fifth processing step S5 and the sixth processing step S6.

[0121] In Figures 5A-5DIn the architecture shown in FIG. 1, all semiconductor dies 70 are either face-up or face-down. In this embodiment, each metal-to-metal bonding occurs between a paired front-side metal bonding pad 18 and a backside metal bonding pad 19. In some architectures, all semiconductor dies 70 are face-up, and the front-side metal bonding pads 18 can be underbonding metal pads in the underbonding wafer (100, 200, or 300), and the backside metal bonding pads 19 can be overbonding metal pads in the overbonding wafer (200, 300, or 400). In some other architectures, all semiconductor dies 70 are face-down, and the front-side metal bonding pads 18 can be overbonding metal pads in the overbonding wafer (200, 300, or 400), and the backside metal bonding pads 19 can be underbonding metal pads in the underbonding wafer (100, 200, or 300). Although Figures 5A-5D While the architecture shown in FIG. 1 shows all semiconductor dies 70 face-down, embodiments are expressly contemplated herein in which all semiconductor dies 70 are face-up.

[0122] In general, each of the semiconductor packages (10, 20, 30, 40) in the composite package 80 can be derived from a respective semiconductor-based wafer (e.g., a semiconductor-based wafer as shown in FIG. 1), can be derived from a respective reconfigured wafer 118 that includes a single semiconductor die 70 per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 2), or can be derived from a respective reconfigured wafer 118 that includes multiple semiconductor dies per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 3). Figure 2 In general, each of the semiconductor packages (10, 20, 30, 40) in the composite package 80 can be derived from a respective semiconductor-based wafer (e.g., a semiconductor-based wafer as shown in FIG. 1), can be derived from a respective reconfigured wafer 118 that includes a single semiconductor die 70 per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 2), or can be derived from a respective reconfigured wafer 118 that includes multiple semiconductor dies per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 3). Figure 3C In general, each of the semiconductor packages (10, 20, 30, 40) in the composite package 80 can be derived from a respective semiconductor-based wafer (e.g., a semiconductor-based wafer as shown in FIG. 1), can be derived from a respective reconfigured wafer 118 that includes a single semiconductor die 70 per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 2), or can be derived from a respective reconfigured wafer 118 that includes multiple semiconductor dies per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 3). Figure 4C In general, each of the semiconductor packages (10, 20, 30, 40) in the composite package 80 can be derived from a respective semiconductor-based wafer (e.g., a semiconductor-based wafer as shown in FIG. 1), can be derived from a respective reconfigured wafer 118 that includes a single semiconductor die 70 per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 2), or can be derived from a respective reconfigured wafer 118 that includes multiple semiconductor dies per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 3). Figure 1 In general, each of the semiconductor packages (10, 20, 30, 40) in the composite package 80 can be derived from a respective semiconductor-based wafer (e.g., a semiconductor-based wafer as shown in FIG. 1), can be derived from a respective reconfigured wafer 118 that includes a single semiconductor die 70 per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 2), or can be derived from a respective reconfigured wafer 118 that includes multiple semiconductor dies per unit area UA (e.g., a reconfigured wafer 118 as shown in FIG. 3).

[0123] Figures 5E-5H Additional architectures are shown in which at least one semiconductor package (10, 20, 30, 40) in the composite package 80 is replaced with a respective semiconductor package (10, 20, 30, 40) derived from a different type of wafer (100, 200, 300, 400). Figures 5A-5D Additional architectures are shown in which at least one semiconductor package (10, 20, 30, 40) in the composite package 80 is replaced with a respective semiconductor package (10, 20, 30, 40) derived from a different type of wafer (100, 200, 300, 400).

[0124] For example, the architecture shown in FIG. 1 can be derived from the architecture shown in FIG. 2 by using a first semiconductor package 10 that includes a plurality of semiconductor dies 70 formed within a molded compound die frame 17. Figure 5E For example, the architecture shown in FIG. 1 can be derived from the architecture shown in FIG. 2 by using a first semiconductor package 10 that includes a plurality of semiconductor dies 70 formed within a molded compound die frame 17. Figure 5A For example, the architecture shown in FIG. 1 can be derived from the architecture shown in FIG. 2 by using a first semiconductor package 10 that includes a plurality of semiconductor dies 70 formed within a molded compound die frame 17. Figure 5F For example, the architecture shown in FIG. 1 can be derived from the architecture shown in FIG. 2 by using a first semiconductor package 10 that includes a plurality of semiconductor dies 70 formed within a molded compound die frame 17. Figure 5E For example, the architecture shown in FIG. 1 can be derived from the architecture shown in FIG. 2 by using a first semiconductor package 10 that includes a plurality of semiconductor dies 70 formed within a molded compound die frame 17. Figure 5G For example, the architecture shown in FIG. 1 can be derived from the architecture shown in FIG. 2 by using a first semiconductor package 10 that includes a plurality of semiconductor dies 70 formed within a molded compound die frame 17. Figure 5FThe architecture shown in FIG. 1 is implemented by using a first semiconductor package 10 that includes a plurality of semiconductor dies 70 formed within a molded compound die frame 17. Figure 5H The architecture shown in FIG. 1 can be derived from Figure 5G The architecture shown in FIG. 1 is implemented by using a first semiconductor package 10 that includes a single semiconductor die 70 derived from using a first wafer 100 based on a semiconductor wafer.

[0125] Referring to Figures 5I-5L FIG. 1 shows an architecture in which a first subset of semiconductor packages (10, 20, 30, 40) are face up and a second subset of semiconductor packages (10, 20, 30, 40), which is a complementary subset, are face down. In this embodiment, the backside metal bonding pads 19 of at least one overlying semiconductor die 70 in an overlying semiconductor package (20, 30, or 40) can be bonded to the backside metal bonding pads 19 of at least one underlying semiconductor die 70 in an underlying semiconductor package (10, 20, or 30). Alternatively or additionally, the frontside metal bonding pads 18 of at least one overlying semiconductor die 70 in an overlying semiconductor package (20, 30, or 40) can be bonded to the frontside metal bonding pads 18 of at least one underlying semiconductor die 70 in an underlying semiconductor package (10, 20, or 30).

[0126] For example, Figure 5I The architecture shown in FIG. 1 can be derived from Figure 5E The architecture shown in FIG. 1 is implemented by flipping the second semiconductor package 20 upside down; Figure 5J The architecture shown in FIG. 1 can be derived from Figure 5F The architecture shown in FIG. 1 is implemented by flipping the second semiconductor package 20 upside down; Figure 5K The architecture shown in FIG. 1 can be derived from Figure 5G The architecture shown in FIG. 1 is implemented by flipping the second semiconductor package 20 upside down; and Figure 5L The architecture shown in FIG. 1 can be derived from Figure 5H The architecture shown in FIG. 1 is implemented by flipping the second semiconductor package 20 upside down. Alternative embodiments in which the replacement semiconductor package (10, 30, 40) and / or at least one additional semiconductor package (10, 30, 40) is flipped upside down are expressly contemplated herein.

[0127] Figures 6A-6L are vertical cross-sectional views of various architectures of a second composite package 80 according to embodiments of the present disclosure. Generally, Figures 6A-6L The second composite package 80 shown in FIG. 1 can be derived from Figures 5A-5L The first composite package 80 shown in FIG. 1 is implemented by removing the third semiconductor package 30 within each composite package. In such embodiments, the fourth processing step S7 can be omitted, and reference is made to Figure 1The second carrier wafer 602 can not be used during the described processing sequence. Alternatively, the second carrier wafer 602 can be detached prior to the singulation step, i.e. the ninth processing step S9. In this embodiment, the composite package 80 does not comprise the handling substrate 60 or the adhesive layer 61. Figures 6A-6L The architecture of the composite package 80 can be derived from the architecture shown in Figures 5A-5L by omitting the formation of the handling substrate 60 and the adhesive layer 61, respectively.

[0128] As mentioned above, the composite package 80 of the present disclosure comprises a vertical stack of three or more semiconductor packages (10, 20, 30, 40). The total number of semiconductor packages (10, 20, 30, 40) in the vertical stack can be 3, 4, 5 or 6 or more.

[0129] Referring to Figures 7A-7D , various exemplary architectures of a third composite package 80 according to embodiments of the present disclosure are shown, which can be derived from any of the first composite packages 80 shown in Figures 5A-5L by reducing the total number of semiconductor packages (10, 20, 30) to three in the vertical stack.

[0130] Referring to Figures 8A-8D , various exemplary architectures of a fourth composite package 80 according to embodiments of the present disclosure are shown, which can be derived from any of the second composite packages 80 shown in Figures 6A-6L by reducing the total number of semiconductor packages (10, 20, 30) to three in the vertical stack.

[0131] Referring collectively to Figure 1 , 2, 3A-3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, and according to various embodiments of the present disclosure, a composite package 80 is provided that includes a vertical stack of at least the first semiconductor package 10, the second semiconductor package 20, and the third semiconductor package 30. The first semiconductor package 10 includes at least one first semiconductor die 70 that includes first metal bonding pads (18, 19); the second semiconductor package 20 includes at least one second semiconductor die 70 that includes second metal bonding pads (18, 19); the third semiconductor package 30 includes at least one third semiconductor die 70 that includes third metal bonding pads (18, 19); each pair of vertically adjacent semiconductor packages within the vertical stack are bonded to one another by metal-to-metal bonding between mating metal bonding pads (18, 19); and vertical sidewalls of the at least three semiconductor packages (10, 20, 30, optionally 40) including the first semiconductor package 10, the second semiconductor package 20, and the third semiconductor package 30 vertically coincide with one another.

[0132] In one embodiment, a first of the at least three semiconductor packages (10, 20, 30, optionally 40) includes a molding compound die frame 17 that laterally surrounds one of the at least one first semiconductor die 70, the at least one second semiconductor die 70, and the at least one third semiconductor die 70. In one embodiment, a second of the at least three semiconductor packages (10, 20, 30, optionally 40) includes an additional molding compound die frame 17 that laterally surrounds another of the at least one first semiconductor die 70, the at least one second semiconductor die 70, and the at least one third semiconductor die 70.

[0133] In one embodiment, the at least one first semiconductor die 70 consists of a single semiconductor die 70 having a sidewall that vertically coincides with an outer sidewall of the molding compound die frame 17. In one embodiment, the at least one third semiconductor die 70 includes a plurality of third semiconductor dies 70 that are laterally spaced apart from one another by and laterally surrounded by the molding compound die frame 17.

[0134] According to another aspect of the present disclosure, there is provided a composite package 80 comprising a vertical stack of at least a first semiconductor package 10, a second semiconductor package 20, and a third semiconductor package 30. The first semiconductor package 10 comprises at least one first semiconductor die 70 comprising first metal bonding pads (18, 19); the second semiconductor package 20 comprises at least one second semiconductor die 70 comprising second metal bonding pads (18, 19); the third semiconductor package 30 comprises at least one third semiconductor die 70 comprising third metal bonding pads (18, 19); each pair of vertically adjacent semiconductor packages within the vertical stack is bonded to one another by metal-to-metal bonding between a pair of mating metal bonding pads (18, 19); and each of the at least one second semiconductor die 70 comprises a respective array of through-substrate via (TSV) structures 4 contacting a subset of the second metal bonding pads (18, 19).

[0135] In one embodiment, the at least one first semiconductor die 70 comprises first top metal bonding pads (18, 19); the at least one second semiconductor die 70 comprises second bottom metal bonding pads (18, 19) bonded to the first top metal bonding pads (18, 19), and further comprises second top metal bonding pads (18, 19); and the at least one third semiconductor die 70 comprises third bottom metal bonding pads (18, 19) bonded to the second top metal bonding pads (18, 19). In one embodiment, the subset of the second metal bonding pads (18, 19) comprises the second top metal bonding pads (18, 19). In one embodiment, the subset of the second metal bonding pads (18, 19) comprises the second bottom metal bonding pads (18, 19).

[0136] In one embodiment, a first of the at least three semiconductor packages (10, 20, 30, optionally 40) comprises a molding compound die frame 17 laterally surrounding one of the at least one first semiconductor die 70, the at least one second semiconductor die 70, and the at least one third semiconductor die 70. In one embodiment, a second of the at least three semiconductor packages (10, 20, 30, optionally 40) comprises an additional molding compound die frame 17 laterally surrounding another of the at least one first semiconductor die 70, the at least one second semiconductor die 70, and the at least one third semiconductor die 70.

[0137] In one embodiment, sidewalls of the second semiconductor package 20 vertically coincide with sidewalls of the first semiconductor package 10 and with sidewalls of the third semiconductor package 30. In one embodiment, the at least one third semiconductor die 70 includes a plurality of third semiconductor dies 70. In one embodiment, the at least one second semiconductor die 70 includes a plurality of second semiconductor dies 70. In one embodiment, the composite package 80 includes an array of solder material portions 88 that are attached to the first semiconductor package 10.

[0138] According to yet another aspect of the present disclosure, a composite package 80 is provided, the composite package 80 including a vertical stack of at least a first semiconductor package 10, a second semiconductor package 20, and a third semiconductor package 30. The first semiconductor package 10 includes at least one first semiconductor die 70 including first metal bonding pads (18, 19); the second semiconductor package 20 includes at least one second semiconductor die 70 including second metal bonding pads (18, 19); the third semiconductor package 30 includes at least one third semiconductor die 70 including third metal bonding pads (18, 19); each pair of vertically adjacent semiconductor packages within the vertical stack are bonded to one another by metal-to-metal bonding between mating metal bonding pads (18, 19); sidewalls of the second semiconductor package 20 vertically coincide with sidewalls of the first semiconductor package 10 and with sidewalls of the third semiconductor package 30; and one or more of the at least one first semiconductor die 70, the at least one second semiconductor die 70, and the at least one third semiconductor die 70 includes a respective sidewall that is laterally offset from a sidewall of the second semiconductor package 20.

[0139] In one embodiment, a first of the at least three semiconductor packages (10, 20, 30, optionally 40) includes a molding compound die frame 17 that laterally surrounds one of the at least one first semiconductor die 70, the at least one second semiconductor die 70, and the at least one third semiconductor die 70. In one embodiment, a second of the at least three semiconductor packages (10, 20, 30, optionally 40) includes an additional molding compound die frame 17 that laterally surrounds another of the at least one first semiconductor die 70, the at least one second semiconductor die 70, and the at least one third semiconductor die 70. In one embodiment, a horizontal plane of the molding compound die frame 17 is in contact with a horizontal plane of the additional molding compound die frame 17.

[0140] In one embodiment, at least one of the semiconductor packages (10, 20, 30) includes at least one additional semiconductor die 70. In one embodiment, the at least one third semiconductor die 70 includes a plurality of third semiconductor dies 70.

[0141] Figure 9 A first flow chart illustrating steps for forming a semiconductor structure is shown in accordance with embodiments of the present disclosure.

[0142] Referring to Figure 9 Step 910 of FIG. 9A and Figure 1 the first auxiliary processing step Al of FIG. 10A and Figure 2 , 3A -3C and 4A-4C, a first wafer 100 including a two-dimensional array of first semiconductor dies 70 is provided, the two-dimensional array of first semiconductor dies 70 including an array of first top metal bonding pads (18, 19) and an array of first bottom metal bonding pads (18, 19).

[0143] Referring to Figure 9 Step 920 of FIG. 9B and Figure 1 the second auxiliary processing step A2 of FIG. 10B and Figure 2 , 3A -3C and 4A-4C, a second wafer 200 including a two-dimensional array of second semiconductor dies 70 is provided, the two-dimensional array of second semiconductor dies 70 including an array of second top metal bonding pads (18, 19) and an array of second bottom metal bonding pads (18, 19).

[0144] Referring to Figure 9 Step 930 of FIG. 9C and Figure 1 the third processing step S3 of FIG. 11C and Figure 2 , 3A -3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, the second wafer 200 is bonded to the first wafer 100 by performing a first metal-to-metal bonding process, wherein the array of first top metal bonding pads (18, 19) is bonded to the array of second bottom metal bonding pads (18, 19) by interdiffusion of the first metal.

[0145] Referring to Figure 9 Step 940 of FIG. 9D and Figure 1 the third auxiliary processing step A3 of FIG. 12D and Figure 2 , 3A -3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, a third wafer 300 including a two-dimensional array of third semiconductor dies 70 is provided, the two-dimensional array of third semiconductor dies 70 including an array of third bottom metal bonding pads (18, 19).

[0146] Referring toFigure 9 of step 950 of Figure 1 of fourth processing step S4 of Figure 2 , 3A - 3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, the third wafer 300 can be bonded to the second wafer 200 by performing a second metal-to-metal bonding process, wherein the array of second top metal bonding pads (18, 19) is bonded to the array of third bottom metal bonding pads (18, 19) by interdiffusion of the second metal.

[0147] In one embodiment, the third wafer 300 can comprise a reconstituted wafer, wherein the third semiconductor dies 70 are laterally surrounded by a matrix 17 of molding compound. In one embodiment, the second wafer 200 can comprise an additional reconstituted wafer, wherein the second semiconductor dies 70 are laterally surrounded by an additional matrix 17 of molding compound. In one embodiment, the first semiconductor dies 70 can be interconnected to each other, and each of the first semiconductor dies 70 can comprise a respective portion of the semiconductor substrate 2 that extends continuously over the entire area of the first wafer 100. In one embodiment, the first wafer 100 can comprise another additional reconstituted wafer, wherein the first semiconductor dies 70 are laterally surrounded by another additional matrix 17 of molding compound. In one embodiment, the third semiconductor dies comprise first-type semiconductor dies and second-type semiconductor dies; and the two-dimensional array of third semiconductor dies comprises a two-dimensional periodic array of repeating units, the repeating units comprising a combination of a first-type semiconductor die and a second-type semiconductor die different from the first-type semiconductor die. In one embodiment, the method can further comprise singulating the bonded assembly comprising at least the first wafer 100, the second wafer 200, and the third wafer 300 into a plurality of compound packages, each compound package comprising components of a respective one of the first semiconductor dies, a respective one of the second semiconductor dies, and a respective one of the third semiconductor dies. In one embodiment, each of the compound packages can comprise a respective additional one of the third semiconductor dies.

[0148] Figure 10 is a second flowchart illustrating steps for forming a semiconductor structure according to embodiments of the present disclosure.

[0149] Referring to Figure 10 of step 1010 of Figure 1 of second processing step S2 of Figure 2 , 3A - 3C and 4A-4C, the first wafer 100 comprising a two-dimensional array of first semiconductor dies 70 can be attached to a top surface of the first carrier wafer 601, the two-dimensional array of first semiconductor dies 70 comprising an array of first top metal bonding pads (18, 19) and an array of first bottom metal bonding pads (18, 19).

[0150] Referring to Figure 10 Step 1020 of Figure 1 the third processing step S3 of Figure 2 , 3A - 3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, by performing a first metal-to-metal bonding process, a second wafer 200 comprising a two-dimensional array of second semiconductor dies 70 including an array of second top metal bonding pads (18, 19) and an array of second bottom metal bonding pads (18, 19) can be bonded to the first wafer 100, wherein the array of first top metal bonding pads (18, 19) is bonded to the array of second bottom metal bonding pads (18, 19) through first intermetallic diffusion.

[0151] Referring to Figure 10 Step 1030 of Figure 1 the fourth processing step S4 of Figure 2 , 3A - 3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, by performing a second metal-to-metal bonding process, a third wafer 300 comprising a two-dimensional array of third semiconductor dies 70 including an array of third bottom metal bonding pads (18, 19) can be bonded to the second wafer 200, wherein the array of second top metal bonding pads (18, 19) is bonded to the array of third bottom metal bonding pads (18, 19) through second intermetallic diffusion.

[0152] In one embodiment, the method can further include a step of bonding the second carrier wafer 602 to a top surface of the bonded assembly comprising the first carrier wafer 601, the first wafer 100, the second wafer 200, and the third wafer 300; and a step of separating the first carrier wafer 601 from the first wafer 100 after bonding the second carrier wafer 602 to the bonded assembly. In one embodiment, the method can further include a step of bonding an array of portions of solder material to the array of first bottom metal bonding pads 19; and a step of singulating the bonded assembly into a plurality of composite packages 80, each composite package 80 comprising a vertical stack of a respective one of the first semiconductor dies, a respective one of the second semiconductor dies, and a respective one of the third semiconductor dies. In one embodiment, one of the first wafer 100, the second wafer 200, and the third wafer 300 can comprise a reconstituted wafer, wherein the matrix of molding compound 17 laterally surrounds the first semiconductor dies, the second semiconductor dies, or the third semiconductor dies. In one embodiment, another one of the first wafer 100, the second wafer 200, and the third wafer 300 can comprise an additional reconstituted wafer, the additional reconstituted wafer comprising an additional matrix of molding compound 17. In one embodiment, the third semiconductor dies can comprise first-type semiconductor dies and second-type semiconductor dies; and the third wafer 300 can comprise a two-dimensional periodic array of repeating units, the repeating units comprising a combination of a first-type semiconductor die and a second-type semiconductor die different from the first-type semiconductor die. In one embodiment, the two-dimensional array of third semiconductor dies comprises an array of third top metal bonding pads; and the method can further include a step of bonding a fourth wafer 400 comprising a two-dimensional array of fourth semiconductor dies to the third wafer 300 by performing a third metal-to-metal bonding process, the fourth semiconductor dies comprising an array of fourth bottom metal bonding pads, wherein the array of third top metal bonding pads is bonded to the array of fourth bottom metal bonding pads by third intermetallic diffusion.

[0153] Figure 11 is a third flowchart illustrating steps for forming a semiconductor structure according to embodiments of the present disclosure.

[0154] Referring to Figure 11 step 1110 of Figure 1 the second processing step S2 of Figure 2 , 3A -3C and 4A-4C, a first wafer 100 comprising a two-dimensional array of first semiconductor dies 70 can be bonded to a top surface of a first carrier wafer 601, the two-dimensional array of first semiconductor dies 70 comprising an array of first top metal bonding pads (18, 19) and an array of first bottom metal bonding pads (18, 19)

[0155] Referring to Figure 11 step 1120 of Figure 1a third processing step S3 of the first processing steps S1 and S2 and Figure 2 , 3A - 3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, by performing a first metal-to-metal bonding process, a second wafer 200 comprising a two-dimensional array of second semiconductor dies 70 including an array of second top metal bonding pads (18, 19) and an array of second bottom metal bonding pads (18, 19) can be bonded to the first wafer 100, wherein the array of first top metal bonding pads (18, 19) is bonded to the array of second bottom metal bonding pads (18, 19) by first intermetallic diffusion.

[0156] Referring to Figure 11 step 1130 of the first processing steps S1 and S2 and Figure 1 a fourth processing step S4 of the first processing steps S1 and S2 and Figure 2 , 3A - 3C, 4A-4C, 5A-5L, 6A-6L, 7A-7D, and 8A-8D, by performing a second metal-to-metal bonding process, a third wafer 300 comprising a two-dimensional array of third semiconductor dies 70 including an array of third bottom metal bonding pads (18, 19) can be bonded to the second wafer 200, wherein the array of second top metal bonding pads (18, 19) is bonded to the array of third bottom metal bonding pads (18, 19) by second intermetallic diffusion. A first one of the first wafer 100, the second wafer 200, and the third wafer 300 comprises a reconstituted wafer, wherein a matrix of molding compound 17M laterally surrounds a first two-dimensional array selected from the group consisting of the two-dimensional array of first semiconductor dies 70, the two-dimensional array of second semiconductor dies 70, and the two-dimensional array of third semiconductor dies 70.

[0157] In one embodiment, a third one of the first wafer 100, the second wafer 200, and the third wafer 300 can comprise another additional reconstituted wafer, wherein another additional matrix of molding compound 17 laterally surrounds a third two-dimensional array selected from the group consisting of the two-dimensional array of first semiconductor dies, the two-dimensional array of second semiconductor dies, and the two-dimensional array of third semiconductor dies. In one embodiment, the two-dimensional array of third semiconductor dies comprises a two-dimensional periodic array of repeating units, the repeating units comprising a combination of a first type of semiconductor die and a second type of semiconductor die different from the first type of semiconductor die. In one embodiment, the method can further comprise a step of singulating a bonded assembly comprising at least the first wafer 100, the second wafer 200, and the third wafer 300 into a plurality of composite packages, each composite package comprising an assembly of a respective one of the first semiconductor dies, a respective one of the second semiconductor dies, and a respective one of the third semiconductor dies.

[0158] Referring to all of the drawings and in accordance with various embodiments of the present disclosure, a composite package is provided that includes a vertical stack of a first semiconductor package 10, a second semiconductor package 20, and a third semiconductor package 30, wherein the first semiconductor package 10 includes at least one first semiconductor die 70 that includes first metal bonding pads (18, 19); the second semiconductor package 20 includes at least one second semiconductor die that includes second metal bonding pads (18, 19); the third semiconductor package 30 includes at least one third semiconductor die that includes third metal bonding pads (18, 19); each pair of vertically adjacent semiconductor packages (10, 20, 30) within the vertical stack are bonded to one another by metal-to-metal bonding between mating metal bonding pads (18, 19); and vertical sidewalls of the at least three semiconductor packages (10, 20, 30) that include the first semiconductor package 10, the second semiconductor package 20, and the third semiconductor package 30 vertically coincide with one another.

[0159] In one embodiment, a first of the at least three semiconductor packages (10, 20, 30) includes a mold compound die frame 17 that laterally surrounds one of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die. In one embodiment, a second of the at least three semiconductor packages (10, 20, 30) includes an additional mold compound die frame 17 that laterally surrounds another of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die. In one embodiment, the at least one first semiconductor die 70 consists of a single semiconductor die having sidewalls that vertically coincide with outer sidewalls of the mold compound die frame 17. In one embodiment, the at least one third semiconductor die includes a plurality of third semiconductor dies that are laterally spaced apart from one another by and laterally surrounded by the mold compound die frame.

[0160] According to another aspect of the present disclosure, there is provided a composite package comprising: a vertical stack of a first semiconductor package 10, a second semiconductor package 20, and a third semiconductor package 30, wherein the first semiconductor package 10 comprises at least one first semiconductor die 70, the at least one first semiconductor die 70 comprising first metal bonding pads (18, 19); the second semiconductor package 20 comprises at least one second semiconductor die, the at least one second semiconductor die comprising second metal bonding pads (18, 19); the third semiconductor package 30 comprises at least one third semiconductor die, the at least one third semiconductor die comprising third metal bonding pads (18, 19); each pair of vertically adjacent semiconductor packages (10, 20, 30) within the vertical stack is bonded to one another by metal-to-metal bonding between a pair of mating metal bonding pads (18, 19); and each of the at least one second semiconductor die comprises a respective array of through-substrate via (TSV) structures 4 contacting a subset of the second metal bonding pads (18, 19).

[0161] In one embodiment, the at least one first semiconductor die 70 comprises first top metal bonding pads (18, 19); the at least one second semiconductor die comprises second bottom metal bonding pads (18, 19) bonded to the first top metal bonding pads (18, 19), and further comprises second top metal bonding pads (18, 19); and the at least one third semiconductor die comprises third bottom metal bonding pads (18, 19) bonded to the second top metal bonding pads (18, 19). In one embodiment, the subset of the second metal bonding pads (18, 19) comprises the second top metal bonding pads (18, 19). In one embodiment, the subset of the second metal bonding pads (18, 19) comprises the second bottom metal bonding pads (18, 19). In one embodiment, a first of the at least three semiconductor packages (10, 20, 30) comprises a molded compound die frame 17 laterally surrounding one of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die. In one embodiment, a second of the at least three semiconductor packages (10, 20, 30) comprises an additional molded compound die frame 17 laterally surrounding another of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die. In one embodiment, a sidewall of the second semiconductor package vertically coincides with a sidewall of the first semiconductor package, and with a sidewall of the third semiconductor package. In one embodiment, the at least one third semiconductor die comprises a plurality of third semiconductor dies. In one embodiment, the at least one second semiconductor die comprises a plurality of second semiconductor dies. In one embodiment, the composite package can further comprise an array of solder material portions 88 attached to the first semiconductor package.

[0162] According to another aspect of the present disclosure, there is provided a composite package comprising a vertical stack of a first semiconductor package 10, a second semiconductor package 20, and a third semiconductor package 30, wherein the first semiconductor package comprises at least one first semiconductor die comprising first metal bonding pads (18, 19), the second semiconductor package comprises at least one second semiconductor die comprising second metal bonding pads (18, 19), the third semiconductor package comprises at least one third semiconductor die comprising third metal bonding pads (18, 19), each pair of vertically adjacent semiconductor packages within the vertical stack are bonded to each other by metal-to-metal bonding between the mating metal bonding pads (18, 19), a sidewall of the second semiconductor package vertically coincides with a sidewall of the first semiconductor package and with a sidewall of the third semiconductor package, and one or more of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die comprises a respective sidewall laterally offset from the sidewall of the second semiconductor package.

[0163] In one embodiment, a first of the at least three semiconductor packages (10, 20, 30) comprises a molding compound die frame 17 laterally surrounding one of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die. In one embodiment, a second of the at least three semiconductor packages (10, 20, 30) comprises an additional molding compound die frame 17 laterally surrounding another of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die. In one embodiment, a horizontal plane of the molding compound die frame 17 is in contact with a horizontal plane of the additional molding compound die frame 17. In one embodiment, the at least one third semiconductor die comprises a plurality of third semiconductor dies.

[0164] Various embodiments of the present disclosure can be used to provide a composite package comprising a vertical stack of three or more semiconductor packages 70 vertically bonded to each other by metal-to-metal bonding and optionally by additional dielectric-to-dielectric bonding. The vertical stack of semiconductor packages 70 enables the fabrication of high-density, high-performance semiconductor packages.

[0165] The foregoing summary of features of several embodiments has been presented for purposes of summarizing aspects of the disclosure and to provide a basic understanding of various aspects of the disclosure. No limitation to the scope of the disclosure is intended by the foregoing summary of features of several embodiments. Unless otherwise expressly provided in the text of this document, no limitation to the scope of the disclosure is intended by the use of the terms "comprises," "comprising," "includes," "including," or "has," "having" or any other variation thereof. Inherent in the use of these terms is the recognition that the item in question can comprise, include, or consist essentially of other items. In other words, the indefinite articles "a" and "an" are intended to mean "one or more" unless otherwise expressly provided in the text of this document. Each embodiment described in the application is intended to be inherently within the scope of the disclosure, whether or not it is explicitly described in the same sentence as the term "inherently." Whenever a Markush group or list of two or more components is recited in the same paragraph as one or more additional components, it is intended that one or more additional components can be present, even though the additional components are not explicitly recited. Whenever a process step or process step is recited in the same paragraph as one or more additional process steps, it is intended that one or more additional process steps can be present, even though the additional process steps are not explicitly recited. Whenever the use of the verb "may" is used in the disclosure to describe the formation of a component or the performance of a process step, it is explicitly contemplated that an embodiment in which such component is not formed or such process step is not performed can also be provided, so long as the resulting apparatus or device provides equivalent results. Thus, whenever the use of the verb "may" is applied to the formation of a component or the performance of a process step, it should also be interpreted as "may" or "may or may not" to the extent that omission of such component or such process step can provide the same or equivalent results, including slightly superior results and slightly inferior results. It will be understood by those within the art that, in light of the disclosure, many changes can be made to the specific embodiments described while still obtaining a fulfilling the same intended and / or similar results. It will be appreciated by those of ordinary skill in the art that any of the various embodiments described herein can be implemented in any of a variety of ways.

Claims

1. A composite package, characterized by, The composite package comprises: a vertical stack of a first semiconductor package, a second semiconductor package, and a third semiconductor package, wherein the first semiconductor package comprises at least one first semiconductor die comprising first metal bonding pads; the second semiconductor package comprises at least one second semiconductor die comprising second metal bonding pads; the third semiconductor package comprises at least one third semiconductor die comprising third metal bonding pads; each pair of vertically adjacent semiconductor packages within the vertical stack is bonded to each other by metal-to-metal bonding between a pair of mating metal bonding pads; and vertical sidewalls of the at least three semiconductor packages vertically coincide with each other.

2. The composite package of claim 1, wherein, a first one of the at least three semiconductor packages comprises a molded compound die frame laterally surrounding one of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die.

3. The composite closure of claim 1, wherein, the at least one third semiconductor die comprises a plurality of third semiconductor dies laterally spaced apart from each other by a molded compound die frame and laterally surrounded by the molded compound die frame.

4. A composite package, characterized by The composite package comprises: a vertical stack of a first semiconductor package, a second semiconductor package, and a third semiconductor package, wherein the first semiconductor package comprises at least one first semiconductor die comprising first metal bonding pads; the second semiconductor package comprises at least one second semiconductor die comprising second metal bonding pads; the third semiconductor package comprises at least one third semiconductor die comprising third metal bonding pads; each pair of vertically adjacent semiconductor packages within the vertical stack is bonded to each other by metal-to-metal bonding between a pair of mating metal bonding pads; and each of the at least one second semiconductor die comprises a respective array of substrate via structures (4) contacting a subset of the second metal bonding pads.

5. The composite closure of claim 4, wherein, the at least one third semiconductor die comprises a plurality of third semiconductor dies.

6. The composite closure of claim 4, wherein, The composite package can further comprise an array of solder material portions affixed to the first semiconductor package.

7. A composite package, characterized by The composite package comprises: a vertical stack of a first semiconductor package, a second semiconductor package, and a third semiconductor package, wherein the first semiconductor package comprises at least one first semiconductor die comprising first metal bonding pads; the second semiconductor package comprises at least one second semiconductor die comprising second metal bonding pads; the third semiconductor package comprises at least one third semiconductor die comprising third metal bonding pads; Each pair of vertically adjacent semiconductor packages within the vertical stack are joined to one another by metal-to-metal joining between mating metal joining pads; a sidewall of the second semiconductor package vertically coincides with a sidewall of the first semiconductor package, and with a sidewall of the third semiconductor package; and one or more of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die includes a respective sidewall laterally offset from a sidewall of the second semiconductor package.

8. The composite package of claim 7, wherein, A first of the at least three semiconductor packages includes a mold compound die frame laterally surrounding one of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die.

9. The composite closure of claim 7, wherein, A second of the at least three semiconductor packages includes an additional mold compound die frame laterally surrounding another of the at least one first semiconductor die, the at least one second semiconductor die, and the at least one third semiconductor die.

10. The composite closure of claim 7, wherein, A horizontal plane of the mold compound die frame is in contact with a horizontal plane of the additional mold compound die frame.

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