Semiconductor package and power module

Abstract

The utility model discloses a semiconductor package and a power module. All interconnects are formed by direct copper (direct copper). The utility model also discloses a power module comprising the semiconductor package. Thus, the power module is suitable for use as a high efficiency power module. In addition, the direct copper interconnection also enhances the heat dissipation of the semiconductor package, so that the operation of the power module is more reliable, especially at high temperature. The power module also includes a substrate (e.g., a direct copper bond (DBC) substrate or a ceramic substrate) on which the semiconductor package is mounted; a plurality of external connection mechanisms coupled to the substrate for electrically leading out the power module; and the at least one signal lead is arranged on the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor package and a power module comprising the same. More particularly, the present application relates to a semiconductor package having direct copper (Cu) interconnects and a power module comprising the same. BACKGROUND

[0002] Conventional power modules such as power converters use wire bonds to interconnect multiple components. However, they cannot meet the demands of high power and high efficiency (including fast switching, high frequency, and high voltage and large current) and heat dissipation. At the same time, conventional power modules also do not have sufficient reliability because wire bonds are easily damaged under long-term operation. SUMMARY

[0003] The present application discloses a power module having a special semiconductor package. All interconnects in the special semiconductor package are direct copper (Cu) interconnects. Therefore, the power module is suitable for use as a high efficiency power module. In addition, the direct copper (Cu) interconnects also enhance the heat dissipation of the semiconductor package, thereby making the operation of the power module (particularly at high temperature) more reliable. The power module includes various forms of converters, such as inverters for converting direct current (DC) to alternating current (AC), rectifiers for converting alternating current (AC) to direct current (DC), choppers for converting direct current (DC) to direct current of different voltages, and AC voltage stabilizers for converting alternating current (AC) to alternating current of different phases.

[0004] As a first aspect of the present application, a semiconductor package for a power module is disclosed. The semiconductor package comprises: at least one high-side semiconductor die having a high-side active face and a high-side inactive face; at least one low-side semiconductor die having a low-side active face and a low-side inactive face; a plurality of vertical structures surrounding the at least one high-side semiconductor die and at least one low-side semiconductor die, wherein each vertical structure has a front face aligned with the high-side active face and the low-side active face, and a back face aligned with the high-side inactive face and the low-side inactive face; a molding layer encapsulating the at least one high-side semiconductor die and at least one low-side semiconductor die, and the plurality of vertical structures; a front side build-up layer coupled to the high-side active face of the at least one high-side semiconductor die and the low-side active face of the at least one low-side semiconductor die, and the front face of the vertical structures; a back side build-up layer coupled to the high-side inactive face of the at least one high-side semiconductor die and the low-side inactive face of the at least one low-side semiconductor die, and the back face of the vertical structures; and an external connection layer coupled to the back side build-up layer.

[0005] As a second aspect of the present application, a power module is disclosed. The power module comprises: a semiconductor package having at least one high-side semiconductor die and at least one low-side semiconductor die; a substrate (e.g., direct copper bonding (DBC) substrate or ceramic substrate) on which the semiconductor package is mounted, wherein functional circuitry of the at least one low-side semiconductor die and at least one high-side semiconductor die is brought out of the substrate; an external connection mechanism coupled to the substrate for electrically bringing out the power module; and at least one signal lead mounted on the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings illustrate embodiments of the present application for the purpose of explaining the principles of the disclosure of the present application. It is to be understood, however, that the drawings are merely for purposes of illustration and are not to be construed as limiting the scope of the present application.

[0007] Figure 1 A flowchart of a panel-level method S10 for manufacturing a power module 100 having a semiconductor package 200 is shown in accordance with an exemplary embodiment of the present disclosure.

[0008] Figure 2a And 2b A step S102 of the panel-level method S10 is shown.

[0009] Figures 3a to 3h A step S104 of the panel-level method S10 is shown.

[0010] Figure 4 A step S106 of the panel-level method S10 is shown.

[0011] Figures 5a to 5c A step S108 of the panel-level method S10 is shown.

[0012] Figures 6 to 8 An optional step S110 of the panel-level method S10 is shown.

[0013] Figure 9 And Figure 10 A step S112 of the panel-level method S10 is shown.

[0014] Figures 11 to 16 A step S114 of the panel-level method S10 is shown.

[0015] Figure 17 A step S116 of the panel-level method S10 is shown.

[0016] Figures 18a to 18d A step S118 and a first embodiment of a step S120 of the panel-level method S10 are shown.

[0017] Figure 19a And 19bExample 260 of a semiconductor package 200 obtained from panel-level method S10 is shown.

[0018] Figure 20 A second embodiment of steps S118 and S120 of panel-level method S10 is shown.

[0019] Figures 21a to 21c Other embodiments 270, 280, and 290 of the semiconductor package 200 obtained from panel-level method S10 are shown.

[0020] Figures 22a to 22d Other embodiments 300, 310, 320 and 330 of the semiconductor package 200 obtained from panel-level method S10 are shown.

[0021] Figures 23a to 25b Step S122 of panel-level method S10 is shown.

[0022] Figures 26a to 27a An embodiment of step S124 of panel-level method S10 and an embodiment 400 of power module 100 are shown.

[0023] Figure 27b An optional step S126 is shown for performing panel-level method S10 on embodiment 400 to form another embodiment 410 corresponding to power module 100.

[0024] Figure 28a and 28b An optional step S128 is shown for performing panel-level method S10 on embodiment 400, thereby forming a corresponding embodiment 420 of power module 100.

[0025] Figure 29 An optional step S126 is shown for performing panel-level method S10 on embodiment 420 to form another embodiment 430 corresponding to power module 100.

[0026] Figure 30a and 30b Another optional step S130 of the panel-level method S10 is shown, thereby forming a corresponding embodiment 440 of the power module 100.

[0027] Figure 30c An optional step S126 is shown for performing panel-level method S10 on embodiment 440 to form another embodiment 450 corresponding to power module 100.

[0028] Figures 31a to 33b Other embodiments of the power module 100, 460, 470, 480, 490, 500 and 510, are shown.

[0029] Figure 34a and34b Two further embodiments 340, 350 of the semiconductor package 200 are shown.

[0030] Figure 35a and 35b Another embodiment of the step S124 of the panel level method S10 is shown, employing the embodiment 340 of the semiconductor package 200 for manufacturing the embodiment 520 of the power module 100.

[0031] Figure 36a and 36b Further embodiments 530, 540 of the power module 100 with a liquid cooling system are shown.

[0032] Reference Signs

[0033] 100 power module, 102 first carrier, 1022 carrier upper surface, 104 first thermal release tape, 106 second carrier, 1062 carrier upper surface, 108 second thermal release tape, 110 substrate, 1102 first conductive layer, 1104 second conductive layer, 1106 third conductive layer, 1108 fourth conductive layer, 1110 bottom surface, 1112 alternating current (AC) conductive layer, 1114 direct current (DC) conductive layer, 1116 low side wiring, 1118 high side wiring, 112, 112' external connection mechanism, 1122 alternating current (AC) copper clip, 1124 direct current positive (DC+) copper clip, 1126 direct current negative (DC-) copper clip, 114 first portion, 116 second portion, 118 third portion, 120 first conductive joint, 122 second conductive joint, 124 third conductive joint, 130 first signal lead, 132 lead upper surface, 134 second signal lead, 138 monolithic signal lead, 1382 top, 1384 bottom, 140 module molding layer, 142 fastener, 150 heat sink, 160 first liquid cooling system, 162 intermediate component, 164 second liquid cooling system, 200 semiconductor package, 202 low side semiconductor die, 2022 low side active face, 2024 low side inactive face, 2026 low side pre-via, 2028 low side filled via, 204 high side semiconductor die, 2042 high side active face, 2044 high side inactive face, 2046 high side pre-via, 2048 high side filled via, 206 copper pillar, 2062 front surface, 2064 / 2064' back surface / (new) back surface, 2066 top, 2072 first copper pillar, 2074 second copper pillar, 2076 third copper pillar, 2078 fourth copper pillar, 208 molding layer, 2082 first molding face, 2084 second molding face, 2086a first top, 2086b second top, 2092 low side gate current path, 2094 high side gate current path, 210 molding panel, 2102 (molding panel) front surface, 2104 (molding panel) back surface, 212 lapping device, 220 backside build-up layer, 2204 (backside build-up layer) upper surface, 222 backside seed layer, 224 backside redistribution layer (RDL) 2244 (backside redistribution layer (RDL)) upper surface, 226 backside dielectric layer, 2264 (backside dielectric layer) upper surface, 2266 (backside dielectric layer) top, 230 frontside build-up layer, 232 first frontside seed layer, 234 first frontside redistribution layer (RDL), 236 first frontside dielectric layer, 2364 (first frontside dielectric layer) upper surface, 238 recess, 240 fill recess, 242 second frontside seed layer, 244 second frontside redistribution layer (RDL), 246 second frontside dielectric layer, 2462 (second frontside dielectric layer) top, 248 external connection layer, 2482 low side external connection layer, 2484 high side external connection layer, 2486 first external connection layer, 2487 second external connection layer,2488 third external connection layer, 2489 fourth external connection layer, 249 external connection dielectric layer, 250 sub-panel, 252 molded interconnect substrate (MIS) unit, 2522 wiring layer, 2522a first wiring layer, 2522b second wiring layer, 2524 insulating portion, 2526 MIS front surface, 2528 MIS back surface, 254 molded via substrate (MVS) unit, 2542 conductive via, 2544 insulating portion, 2546 MVS front surface, 2548 MVS back surface, 256 metal frame, 2562 connection pad, 2564 connection strip, 257 metal unit, 2572 first void, 2574 second void, 258 temporary support, 260-340 embodiments of semiconductor packages, 400-540 embodiments of power modules. DETAILED DESCRIPTION

[0034] Figure 1 A flowchart of a panel-level method S10 for manufacturing a power module 100 with a semiconductor package 200 is shown according to an example embodiment of the present disclosure. The panel-level method S10 includes steps S102-S124, and also includes optional steps S126, S128, and S130.

[0035] Figure 2a And Figure 2b Step S102 of the panel-level method S10 is shown, which is to provide a first carrier 102 and possibly a first thermal release tape 104. Figure 2a A cross-sectional view of a portion of the first carrier 102 and a portion of the first thermal release tape 104 fixed on the portion is shown. Figure 2b A top view of the portion of the first carrier 102 is shown, which has a rectangular shape. Thus, the first carrier 102 has a plurality of portions as shown. Figure 2b In one embodiment, the first carrier 102 has a square shape with a size of 700 millimeters (mm) x 700 millimeters (mm), which is much larger than a conventional wafer with a diameter of 8 inches or 12 inches. Thus, the panel-level method S10 has a higher productivity than a conventional wafer-level method. It should be understood that the first carrier 102 can also have other shapes, such as a rectangular or a circular shape. The first thermal release tape 104 can almost completely cover the carrier upper surface 1022 of the first carrier 102 to improve the productivity.

[0036] Figures 3a to 3h Step S104 of the panel-level method S10 is shown, which is to bond semiconductor dies and vertical structures onto the first carrier 102 and the first thermal release tape 104. The first thermal release tape 104 has sufficient adhesion at room temperature to fix the semiconductor dies and vertical structures at appropriate positions on the first carrier 102. Figure 3aA cross-sectional view is shown with a plurality of low-side semiconductor dies 202 and a plurality of high-side semiconductor dies 204 bonded to respective predetermined locations on the first carrier 102 and the first thermal release tape 104. The terms "low-side" and "high-side" refer to the lower voltage side and the higher voltage side, respectively. Thus, the low-side semiconductor dies 202 and the high-side semiconductor dies 204 will be electrically coupled to a lower voltage end (input or output) and a higher voltage end (input or output), respectively, of a power module. The low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be metal oxide semiconductor field effect transistors (MOSFETs) made of silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). Specifically, the low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be bonded in a face-down manner, i.e., with low-side active faces 2022 of the low-side semiconductor dies 202 and high-side active faces 2042 of the high-side semiconductor dies 204 in contact with a carrier upper surface 1022 of the first thermal release tape 104 and the first carrier 102. The low-side semiconductor dies 202 and the high-side semiconductor dies 204 have low-side inactive faces 2024 and high-side inactive faces 2044, respectively, opposite the low-side active faces 2022 and the high-side active faces 2042. The low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be configured to have the same die thickness, such that the low-side active faces 2022 and the low-side inactive faces 2024 of the low-side semiconductor dies 202 are coplanar with the high-side active faces 2042 and the high-side inactive faces 2044 of the high-side semiconductor dies 204, respectively.

[0037] The low-side semiconductor dies 202 and the high-side semiconductor dies 204 have low-side pre-vias 2026 and high-side pre-vias 2046 at the low-side active faces 2022 and the high-side active faces 2042, respectively. The low-side pre-vias 2026 and the high-side pre-vias 2046 can be filled with a conductive material, such as copper (Cu) or titanium / copper (Ti / Cu) composite, to become low-side filled vias 2028 and high-side filled vias 2048 of the low-side semiconductor dies 202 and the high-side semiconductor dies 204, respectively. Thus, functional circuitry of the low-side semiconductor dies 202 and the high-side semiconductor dies 204 can be routed from contact pads at the low-side active faces 2022 and the high-side active faces 2042 of the low-side semiconductor dies 202 and the high-side semiconductor dies 204, respectively, through the low-side filled vias 2028 and the high-side filled vias 2048.

[0038] The low-side semiconductor die 202 and the high-side semiconductor die 204 are obtained by dicing a low-side semiconductor wafer (not shown) received (from a customer) and a high-side semiconductor wafer (not shown) received (from a customer), respectively. The received low-side semiconductor wafer and the received high-side semiconductor wafer have functional circuitry on their respective active surfaces. They can be silicon (Si) wafers, silicon carbide (SiC) wafers, or gallium nitride (GaN) wafers; their inactive surfaces are made of the same semiconductor material. Therefore, after dicing, the active surfaces of the received low-side semiconductor wafer and the received high-side semiconductor wafer form a low-side active surface 2022 and a high-side active surface 2042, respectively, which have the functional circuitry of the low-side semiconductor die 202 and the high-side semiconductor die 204, respectively; simultaneously, the inactive surfaces of the received low-side semiconductor wafer and the received high-side semiconductor wafer form a low-side inactive surface 2024 and a high-side inactive surface 2044, respectively. Additionally, the received low-side semiconductor wafer and the received high-side semiconductor wafer may each have a conductive layer on their inactive surfaces. After dicing, these conductive layers remain on the low-side inactive surface 2024 and the high-side inactive surface 2044, respectively. These conductive layers will serve as external interconnect layers 248 in subsequent processes.

[0039] The vertical structure can take various forms. For example, the vertical structure can first be fabricated as a separate sheet and then bonded to the first carrier 102 and the first heat-release membrane 104. Alternatively, the vertical structure can be bonded as a group, that is, multiple vertical structures can be bonded as a whole to the first carrier 102 and the first heat-release membrane 104 in a single process. Figure 3a In the illustrated embodiment, the vertical structure may include a plurality of copper (Cu) pillars 206 bonded to the first carrier 102 and the first heat release zone 104, which are first fabricated as individual wafers and then bonded to the periphery of the low-side semiconductor die 202 and the high-side semiconductor die 204. The copper pillars 206 have a front surface 2062 aligned with the low-side active surface 2022 / high-side active surface 2042, and a rear surface 2064 aligned with the low-side inactive surface 2024 / high-side inactive surface 2044. Specifically, the front surface 2062 of the copper pillars 206 is in contact with the carrier upper surface 1022 of the first heat release zone 104 and the first carrier 102. Therefore, the front surface 2062 of the copper pillars 206 is coplanar with the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204. Simultaneously, the copper pillar 206 has a pillar height (measured between the front surface 2062 and the rear surface 2064) greater than the die thickness of the low-side semiconductor die 202 and the high-side semiconductor die 204. Figure 3aIn the illustrated embodiment, for each semiconductor package 200, the copper pillars 206 include two first copper pillars 2072 located on the lower side, and a second copper pillar 2074 located between the two first copper pillars 2072, which is perpendicular to... Figure 3a The directions shown coincide. Similarly, copper pillar 206 also includes two third copper pillars 2076 located on the high side, and a fourth copper pillar 2078 located between the two third copper pillars 2076, which is perpendicular to... Figure 3a The directions shown coincide.

[0040] In such Figure 3b In another embodiment shown, the vertical structure may include a plurality of molded interconnect substrate (MIS) units 252. The MIS units 252 are first fabricated as individual wafers and then bonded to the periphery of the low-side semiconductor die 202 and the high-side semiconductor die 204. Figure 3b The top left corner shows an enlarged view of the MIS cell 252. The MIS cell 252 also includes multiple interconnected wiring layers 2522 for electrical conduction; and insulating portions 2524 for insulating the wiring layers 2522 within the MIS cell 252. The wiring layers 2522 can be made of any conductive material, such as copper. Compared to copper pillars 206, the MIS cell 252 consumes less copper, thus reducing the weight of the semiconductor package 200. Similarly, the MIS cell 252 has a front MIS surface 2526, which is coplanar with the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204. The MIS cell 252 has an MIS height (measured between the front MIS surface 2526 and the rear MIS surface 2528 of the MIS cell 252), which is greater than the die thickness of the low-side semiconductor die 202 and the high-side semiconductor die 204. Figure 3b The enlarged view also shows that the wiring layers 2522 of the MIS unit 252 have a first wiring layer 2522a and a second wiring layer 2522b at the front surface 2526 and the rear surface 2528 of the MIS, respectively. In particular, the first wiring layer 2522a and the second wiring layer 2522b are exposed from the insulating portion 2524 of the MIS unit 252.

[0041] In such Figure 3c In another embodiment shown, the vertical structure may include a plurality of molded via substrate (MVS) units 254. The MVS units 254 are first fabricated as individual wafers and then bonded to the periphery of the low-side semiconductor die 202 and the high-side semiconductor die 204. Figure 3cAn enlarged view of the MVS cell 254 is shown in the upper left corner. The MVS cell 254 further includes a plurality of conductive vias 2542 for electrical conduction, and insulating portions 2544 for insulating the conductive vias 2542 within the MVS cell 254. The conductive vias 2542 can be made of any conductive material, such as copper (Cu). Similar to the MIS cell 252, the MVS cell 254 consumes less copper, thus reducing the weight of the semiconductor package 200. It is also shown that the MVS cell 254 has an MVS front surface 2546 that is coplanar with the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204. The MVS cell 254 has an MVS height (measured between the MVS front surface 2546 and an MVS back surface 2548 of the MVS cell 254) that is greater than the die thickness of the low-side semiconductor die 202 and the high-side semiconductor die 204. The MIS cell 252 and the MVS cell 254 have the same function as the copper pillar 206. For simplicity of description, the subsequent processes will be described using the copper pillar 206 only. It should be understood, however, that the subsequent processes are also applicable to the MIS cell 252 and the MVS cell 254.

[0042] As shown in another embodiment, Figures 3d to 3g the vertical structure can include a metal frame 256 that is bonded in a set. Figure 3d and Figure 3e showing a cross-sectional view and a top view, respectively, the metal frame 256 includes an array of metal cells 257, as shown by the dashed rectangles in Figure 3d and Figure 3e The metal frame 256 can be a lead frame that is commercially available, or formed by etching or mechanically stamping a sheet or a slab of metal, as desired. The sheet to be patterned can be made of a single metal or an alloy, such as copper. The surface of the sheet can be partially or completely coated with a second metal, such as nickel and / or gold, to protect the sheet from environmental erosion, such as oxidation. In some embodiments, the thickness of the sheet is not less than the die thickness of the semiconductor dies 202, 204. As shown in Figure 3e the sheet is patterned to include two identical metal cells 257, and each metal cell 257 has the same rectangular outer profile. This design is exemplary only, however, and the number of metal cells 257 is not limited to two, and can be set as desired. The shape of the metal cells 257 can be rectangular or other shapes.

[0043] The metal frame 256 includes a plurality of connection pads 2562 disposed inward of the outer profile edge of the metal frame 256, or other locations as desired. The connection pads 2562 are connected by a connection strip 2564 formed of the metal that was not etched away from the metal sheet. The connection strip 2564 is reserved during the patterning of the metal sheet to ensure that certain features, such as the connection pads 2562, formed by the patterning of the metal sheet are connected to the outer profile edge of the metal frame 256, thereby ensuring that the features patterned on the metal frame 256 do not deform or even fall off during the transfer of the metal frame 256. Preferably, the metal piece is first secured to the temporary support 258 for patterning, and after the patterning is complete, the metal frame 256 is transferred to the first carrier 102 and the first heat release tape 104 via the temporary support 258. However, it will be appreciated that the connection pads 2562 can also be bonded to the temporary support 258 individually; however, it will be appreciated that the connection pads 2562 can be bonded to the temporary support 258 individually and do not need to be reserved during the etching or mechanical stamping of the metal piece.

[0044] The metal frame 256 includes a plurality of voids, including a first void 2572 and a second void 2574, for receiving the high-side semiconductor die 204 and the low-side semiconductor die 202, respectively, in subsequent processes (as shown in Figure 3g The connection strip 2564 is shown removed along the cut line on the temporary support 258, such that the connection pads 2562 are individually separated but remain fixed to the temporary support 258. Figure 3f The connection strip 2564 is shown removed along the cut line on the temporary support 258, such that the connection pads 2562 are individually separated but remain fixed to the temporary support 258.

[0045] Figure 3g A cross-sectional view is shown in which the metal unit 257 on the temporary support 258 is flipped over and faces the first carrier 102 and the first heat release tape 104. In particular, the metal unit 257 is precisely positioned relative to the first carrier 102 and the first heat release tape 104 such that the first void 2572 and the second void 2574 of the metal unit 257 are aligned with and receive the high-side semiconductor die 204 and the low-side semiconductor die 202. Although Figure 3g Although only one metal unit 257 is shown in the cross-sectional view, it will be appreciated that all of the metal units 257 on the temporary support 258 are flipped over and bonded to the first carrier 102 and the first heat release tape 104 as a whole.

[0046] Figure 3hThe low-side semiconductor dies 202 and high-side semiconductor dies 204 are arranged according to the design of the semiconductor package 200 (as shown by the dashed rectangle). In one embodiment, the semiconductor package 200 has one set of 8 low-side semiconductor dies 202 on the left side (low-side) of the figure and another set of 8 high-side semiconductor dies 204 on the right side (high-side) of the figure. It should be understood that the design of the semiconductor package 200 can be changed to have other numbers of low-side semiconductor dies 202 and / or high-side semiconductor dies 204. As shown, this portion of the first carrier 102 and the corresponding first heat release strip 104 has 12 semiconductor packages 200 arranged in a 3-by-4 matrix. It should be understood that more semiconductor packages 200 (e.g., hundreds or even thousands) can be bonded on the entire first carrier 102 and corresponding first heat release strip 104 while subsequent processes are performed to increase production rate.

[0047] Figure 4 A step S106 of the panel-level method S10 is shown, which is forming a molding layer 208 for encapsulating the low-side semiconductor dies 202, high-side semiconductor dies 204, and copper pillars 206 to form a molded panel 210. The low-side inactive faces 2024 of the low-side semiconductor dies 202, the high-side inactive faces 2044 of the high-side semiconductor dies 204, and the back surfaces 2064 of the copper pillars 206 are completely encapsulated in the molding layer 208; while the low-side active faces 2022 of the low-side semiconductor dies 202, the high-side active faces 2042 of the high-side semiconductor dies 204, and the front surfaces 2062 of the copper pillars 206 are not encapsulated due to the contact with the first heat release strip 104 and the carrier upper surface 1022 of the first carrier 102. Specifically, the molding layer 208 has a first molding face 2082 in contact with the first heat release strip 104 and the carrier upper surface 1022 of the first carrier 102. Thus, the first molding face 2082 is coplanar with the low-side active faces 2022 of the low-side semiconductor dies 202, the high-side active faces 2042 of the high-side semiconductor dies 204, and the front surfaces 2062 of the copper pillars 206. The molding layer 208 can be formed by any molding compound through any suitable method, for example, using Sumitomo G730 through a compression molding process.

[0048] Figures 5a to 5c A step S108 of the panel-level method S10 is shown, which is thinning the molding layer 208 to a desired thickness of the molded panel 210. In one embodiment, the step S108 can be divided into two sub-steps. Figure 5a A cross-sectional view of the first sub-step is shown, in which a first top portion 2086a of the molding layer 208 is removed by a grinding device 212 (as shown by the dashed line). The grinding device 212 is configured to grind the first top portion 2086a of the molding layer 208 to a desired thickness of the molded panel 210. In one embodiment, the grinding device 212 is configured to grind the first top portion 2086a of the molding layer 208 to a thickness of 100-200 pm. It should be understood that the grinding device 212 can be configured to grind the first top portion 2086a of the molding layer 208 to any suitable thickness. Figure 5aThe first sub-step is shown in a cross-sectional view in FIG. 6A. The back surface 2064 of the copper pillar 206 can be left and exposed from the molding layer 208; while the low-side inactive face 2024 of the low-side semiconductor die 202 and the high-side inactive face 2044 of the high-side semiconductor die 204 are still encapsulated. The first sub-step can be performed in a fast manner to improve productivity. Then, Figure 5b The second sub-step is shown in a cross-sectional view in FIG. 6B, i.e., further removing the second top portion 2086b of the molding layer 208 (as shown in the dashed rectangle) from the molding layer 208. Accordingly, after the second sub-step, the molding layer 208 has a second molding face 2084. Specifically, the low-side inactive face 2024 of the low-side semiconductor die 202 and the high-side inactive face 2044 of the high-side semiconductor die 204 are exposed from the second molding face 2084 of the molding layer 208. Correspondingly, in the second sub-step, a top portion 2066 of the copper pillar 206 (as shown in the dashed square) is also removed by the grinding device 212, so as to form a new back surface 2064' and to be exposed from the second molding face 2084 of the molding layer 208. The second sub-step is performed slower than the first sub-step to avoid damaging the low-side inactive face 2024 of the low-side semiconductor die 202 and the high-side inactive face 2044 of the high-side semiconductor die 204. The second sub-step is also referred to as "lapping" of the molding layer 208. Preferably, the thickness of the second top portion 2086b is smaller than the thickness of the first top portion 2086a to improve productivity. Figure 5b A top view of a portion of the molding panel 210 is shown in FIG. 6C, in which the low-side inactive face 2024 of the low-side semiconductor die 202, the high-side inactive face 2044 of the high-side semiconductor die 204, and the new back surface 2064' of the copper pillar 206 are exposed from the second molding face 2084 of the molding layer 208. Figure 5a Figure 5c

[0049] Figures 6 to 8 A step S110 of the panel-level method S10 is shown in FIG. 7A, i.e., forming a backside build-up layer 220 at the back surface 2104 of the molding panel 210. The back surface 2104 includes the low-side inactive face 2024 of the low-side semiconductor die 202, the high-side inactive face 2044 of the high-side semiconductor die 204, the new back surface 2064' of the copper pillar 206, and the second molding face 2084 of the molding layer 208. Figure 6 A cross-sectional view is shown in FIG. 7B, in which a backside seed layer 222 is formed on the back surface 2104 of the molding panel 210. The backside seed layer 222 is electrically coupled to the copper pillar 206 at the new back surface 2064'. The backside seed layer 222 can be formed by any conductive material through any suitable method. In one embodiment, the backside seed layer 222 is formed by titanium / copper (Ti / Cu) composite material through sputtering. Then, Figure 7 ​​A cross-sectional view is shown, showing a back-side redistribution layer (RDL) 224 formed on the back-side seed layer 222. The back-side RDL 224 can be formed from any conductive material by any suitable method. In one embodiment, the back-side RDL 224 is formed from copper (Cu) by electroplating. The back-side RDL 224 can also be patterned by any suitable method (e.g., photolithography). Therefore, copper pillars 206 are electrically coupled to the back-side RDL 224 to allow current / signal passage. Subsequently, Figure 8 A cross-sectional view is shown, showing the formation of a back-side dielectric layer 226 for encapsulating the back-side RDL 224. The back-side dielectric layer 226 can be formed of any dielectric material, such as molding compounds, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or other materials with similar insulating and structural properties. Then, in a polishing process, a top portion 2266 of the back-side dielectric layer 226 is removed by a polishing apparatus 212. Figure 8 (As shown by the dashed rectangle in the diagram), this is used to expose the back-side RDL 224 from the back-side dielectric layer 226. Therefore, the back-side build layer 220 includes the back-side RDL 224 and the back-side dielectric layer 226. Preferably, the polishing process also gives the upper surface 2204 of the back-side build layer 220 a substantially flat structure, thereby facilitating subsequent processes in step S112. The upper surface 2204 includes the upper surface 2244 of the back-side RDL 224 and the upper surface 2264 of the back-side dielectric layer 226.

[0050] Figure 9 and Figure 10 The step S112 of the panel-level method S10 is shown, which involves transferring the molded panel 210 with the back-side building layer 220 to the second carrier 106. Figure 9 A cross-sectional view of a molded panel 210 with a back-side build-up layer 220 is shown. Since the first heat release band 104 loses its adhesiveness at high temperatures, the back-side build-up layer 220 can be separated from the first carrier 102 at high temperatures. Therefore, the front surface 2102 of the molded panel 210 is exposed from the first carrier 102 and the first heat release band 104. The front surface 2102 of the molded panel 210 includes the low-side active surface 2022 of the low-side semiconductor die 202, the high-side active surface 2042 of the high-side semiconductor die 204, the front surface 2062 of the copper pillar 206, and the first molding surface 2082 of the molding layer 208. Subsequently, Figure 10A cross-sectional view is shown, the molding panel 210 with the backside build-up layer 220 is flipped over and mounted onto the second carrier 106 and the second heat release tape 108. As mentioned above, the molding panel 210 has a substantially flat configuration, thus the molding panel 210 can be mounted on the second carrier 106 and the second heat release tape 108 quite stably. Meanwhile, the second heat release tape 108 has sufficient tackiness at room temperature to fix the molding panel 210 with the backside build-up layer 220 at a proper position on the carrier upper surface 1062 of the second carrier 106. The low-side pre-vias 2026 of the low-side semiconductor dies 202, the high-side pre-vias 2046 of the high-side semiconductor dies 204, and the front surface 2062 of the copper pillars 206 are exposed from the first molding surface 2082 of the molding layer 208.

[0051] Figures 11 to 16 A step S114 of the panel-level method S10 is shown, i.e. forming a frontside build-up layer 230 on the front surface 2102 of the molding panel 210. Figure 11 A cross-sectional view is shown, a first frontside seed layer 232 is conformally formed following the contour of the low-side pre-vias 2026 of the low-side semiconductor dies 202, the high-side pre-vias 2046 of the high-side semiconductor dies 204, the front surface 2062 of the copper pillars 206, and the first molding surface 2082 of the molding layer 208. The first frontside seed layer 232 can be made of any conductive material by any suitable method. In one embodiment, the first frontside seed layer 232 is made of titanium / copper (Ti / Cu) composite material by sputtering. In this way, the first frontside seed layer 232 is electrically coupled to the front surface 2062 of the copper pillars 206. After forming the first frontside seed layer 232, a die location check (DLC) process can be performed for checking whether the low-side semiconductor dies 202 and the high-side semiconductor dies 204 are bonded to their predetermined positions. If not, the DLC process will collect the real positions of the low-side semiconductor dies 202 and the high-side semiconductor dies 204 in the molding panel 210.

[0052] Figure 12A cross-sectional view is shown. The low-side pre-via 2026 of the low-side semiconductor die 202 and the high-side pre-via 2046 of the high-side semiconductor die 204 are filled with a conductive material and are transformed into a low-side filled via 2028 and a high-side filled via 2048, respectively, in accordance with the true positions of the low-side semiconductor die 202 and the high-side semiconductor die 204. Then, a first front-side redistribution layer (RDL) 234 is formed on the front surface 2102 of the molding panel 210. The first front-side RDL 234 can be made of any conductive material, such as metal, by any suitable method. Preferably, the first front-side RDL 234 is made of copper (Cu) by electroplating. As a result, the first front-side RDL 234 is electrically coupled to the low-side filled via 2028 of the low-side semiconductor die 202, the high-side filled via 2048 of the high-side semiconductor die 204, and the front surface 2062 of the copper pillar 206. As a result, the functional circuitry of the low-side semiconductor die 202 and the high-side semiconductor die 204 is routed from the contact pads at the low-side active surface 2022 of the low-side semiconductor die 202 and the high-side active surface 2042 of the high-side semiconductor die 204, respectively, through the first front-side RDL 234 and the copper pillar 206 to the back-side RDL 224 of the back-side build-up layer 220. Alternatively, the filling of the low-side pre-via 2026 of the low-side semiconductor die 202 and the high-side pre-via 2046 of the high-side semiconductor die 204 can be skipped if the low-side semiconductor die 202 and the high-side semiconductor die 204 are not bonded to the first carrier 102 and the first heat release tape 104, respectively, as described above. Figures 3a to 3d The low-side pre-via 2026 of the low-side semiconductor die 202 and the high-side pre-via 2046 of the high-side semiconductor die 204 can be filled prior to the bonding of the low-side semiconductor die 202 and the high-side semiconductor die 204 to the first carrier 102 and the first heat release tape 104, respectively. As a result, the filling of the low-side pre-via 2026 of the low-side semiconductor die 202 and the high-side pre-via 2046 of the high-side semiconductor die 204 can be skipped at this point.

[0053] Figure 13 A cross-sectional view is shown. A first front-side dielectric layer 236 is formed for encapsulating the first front-side RDL 234. The first front-side dielectric layer 236 can be made of any dielectric material, such as molding compound, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or other materials with similar insulating and structural properties. The first front-side dielectric layer 236 can be formed by any suitable method, such as the compression molding process of Sumitomo G730. Preferably, the first front-side dielectric layer 236 is formed by a thin film lamination process for controlling the first front-side dielectric layer 236 at a specific first thickness, such as 100 micrometers (pm). Prior to the formation of the first front-side dielectric layer 236, the first front-side seed layer 232 can be removed by any suitable method, such as chemical etching, for ensuring electrical isolation between the first front-side RDL 234. As a result, a front-side build-up layer 230 is formed including the first front-side RDL 234 and the first front-side dielectric layer 236.

[0054] Figure 14A cross-sectional view is shown in which a plurality of recesses 238 are formed in the first front side dielectric layer 236. The recesses 238 can be formed by any suitable panel level method, such as laser drilling, photolithography, photoimageable, etc., depending on the design of the semiconductor package 200. For photolithography or photoimageable techniques, the first front side dielectric layer 236 can be made of a solder mask material or a photoimageable dielectric material for forming the recesses 238 in the first front side dielectric layer 236. The solder mask material can include a resin (e.g., epoxy, polyurethane, acrylic), a hardener, a filler, a dye, and a UV reactive substance, etc. Preferably, the solder mask material includes TAIYO PSR-4000 series material. Thus, a portion of the first front side RDL 234 is exposed from the first front side dielectric layer 236 by the recesses 238. Then, a second front side seed layer 242 is conformally formed by following the contours of the recesses 238 and the upper surface 2364 of the first front side dielectric layer 236. The second front side seed layer 242 can be formed of any conductive material by any suitable method. In one embodiment, the second front side seed layer 242 is formed of a titanium / copper (Ti / Cu) composite by sputtering. Thus, the second front side seed layer 242 is electrically coupled to the first front side RDL 234. Figure 15 A cross-sectional view is shown in which the recesses 238 are filled by a method such as electroplating with a conductive material such as copper (Cu) or titanium / copper (Ti / Cu) composite, and are accordingly transformed into filled recesses 240. Then, a second front side redistribution layer (RDL) 244 is formed on the filled recesses 240 and the second front side seed layer 242. The second front side RDL 244 can be formed of any conductive material such as a metal by any suitable method. Preferably, the second front side RDL 244 is formed of copper (Cu) by electroplating. Thus, the second front side RDL 244 is electrically coupled to the first front side RDL 234 by the filled recesses 240.

[0055] Figure 16A cross-sectional view is shown, forming a second front-side dielectric layer 246 for encapsulating the second front-side RDLs 244. The second front-side dielectric layer 246 can be made of any dielectric material, such as a molding compound, silicon dioxide (Si02), silicon nitride ((Si3N4), silicon oxynitride (SiON), aluminum oxide (AI2O3), or other materials with similar insulating and structural properties. The second front-side dielectric layer 246 can be formed by any suitable method, such as a compression molding process or a thin film lamination process. Subsequently, the second front-side dielectric layer 246 can be subjected to a grinding process by the grinding device 212 to remove a top portion 2462 of the second front-side dielectric layer 246, thereby reducing the second front-side dielectric layer 246 to a specific second thickness according to the design of the semiconductor package 200. Thus, the front-side build-up layer 230 shown herein has a first layer including the first front-side RDLs 234 and the first front-side dielectric layer 236; a second layer including the second front-side RDLs 244 and the second front-side dielectric layer 246; and the fill recess 240 for electrically coupling the first layer and the second layer. It is understood that the front-side build-up layer 230 can further include more other layers identical or similar to the first layer or the second layer, and more other fill recesses identical or similar to the fill recess 240, for electrically coupling the more other layers. Prior to forming the second front-side dielectric layer 246, the second front-side seed layer 242 is removed by any suitable method, such as a chemical etching, to ensure electrical isolation between the second front-side RDLs 244.

[0056] Figure 17 A step S116 of the panel-level method S10 is shown, i.e., the molding panel 210 having the back-side build-up layer 220 and the front-side build-up layer 230 (e.g., including the first layer and the second layer as described above) can be separated from the second carrier 106 and the second thermal release tape 108, since the second thermal release tape 108 can lose its tackiness at a higher temperature. Thus, the back-side build-up layer 220 is exposed from the second carrier 106 and the second thermal release tape 108.

[0057] Figures 18a to 18d A first embodiment of steps S118 and S120 of the panel-level method S10 is shown. This step S118 is optional and thus can be skipped. For example, as shown in the semiconductor package 200 of FIG. 2B, the back-side RDLs 222 can be directly formed on the back surface 2104 of the molding panel 210. Figures 22a to 22d and Figure 34b The semiconductor package 200 is shown in FIG. 2B, where the external connection layer 248 is directly formed on the back surface 2104 of the molding panel 210. Figure 18a A cross-sectional view is shown, the molding panel 210 having the back-side build-up layer 220 and the front-side build-up layer 230 (e.g., including the first layer and the second layer as described above) is cut into a plurality of sub-panels 250 along saw lines, which are smaller in size than the molding panel 210. In one embodiment, the sub-panels 250 are 212 millimeters (mm) x 216 mm in size. Figure 18bThe sub-panel 250 is shown in a top view having six semiconductor packages 200 arranged in a 2-by-3 matrix. It should be understood that the sub-panel 250 can also have other numbers and arrangements of semiconductor packages 200. Then, Figure 18c A cross-sectional view of the sub-panel 250 is shown. On the scale of the sub-panel 250, an external connection layer 248 is formed on the exposed backside RDL 224 at the backside dielectric layer 226 of the backside build-up layer 220 from the backside. The external connection layer 248 can be formed from any conductive material, such as metal, by any suitable method to form a surface finish for providing a flat surface for input / output (I / O). The surface finish can be made from a single layer of metal, such as tin, or a single layer of metal composite, such as nickel / gold. Alternatively, the surface finish can also be made from multiple layers. In some embodiments, the surface finish is made from Electroless Nickel Immersion Gold (ENIG) having two layers of metal surface coating, where the first layer of nickel can be formed using an electroless plating chemical reaction; and then a very thin layer of gold is plated on top of the nickel layer. In other embodiments, the surface finish can be made from Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) by depositing electroless nickel plating, followed by electroless palladium plating, and finally immersion gold flash. Preferably, the external connection layer 248 is formed from silver (Ag) by electroplating to form the surface finish. The surface finish is chemically compatible with I / O to improve the stability of the connection. The thickness of the surface finish can be in the range of 1 micrometer (pm) to 10 micrometers (pm), preferably, in the range of 1 micrometer (pm) to 5 micrometers (pm), or more preferably, in the range of 1 micrometer (pm) to 3 micrometers (pm). Finally, Figure 18d A cross-sectional view is shown. Depending on the design of the semiconductor package 200, the sub-panel 250 with the external connection layer 248 is further singulated into individual semiconductor packages 200 along saw lines.

[0058] Figure 19a and 19b An embodiment 260 of the semiconductor package 200 obtained from the panel-level method S10 is shown. Figure 19aA cross-sectional view of embodiment 260 is shown, in which all interconnections within semiconductor package 200 are formed by direct copper, i.e. interconnections between contact pads and low-side filled vias 2028 of low-side semiconductor dies 202 and high-side filled vias 2048 of high-side semiconductor dies 204, interconnections between low-side filled vias 2028 and high-side filled vias 2048 and first front-side RDLs 234 of front-side build-up layer 230, interconnections between first front-side RDLs 234 of front-side build-up layer 230 and copper pillars 206, and interconnections between copper pillars 206 and back-side RDLs 224 of back-side build-up layer 220, respectively. The direct copper also includes interconnections between first front-side RDLs 234 and second front-side RDLs 244 of front-side build-up layer 230 through filled grooves 240 in front-side build-up layer 230. Thus, functional circuits of low-side semiconductor dies 202 and high-side semiconductor dies 204 are led out from contact pads at low-side active faces 2022 and high-side active faces 2042 to back-side RDLs 224 of back-side build-up layer 220 at low-side inactive faces 2024 of low-side semiconductor dies 202 and high-side inactive faces 2044 of high-side semiconductor dies 204, respectively; and further led out to external devices, e.g. Figure 23a and 23b substrate 110 (e.g. a Direct Bonded Copper (DBC) substrate or a ceramic substrate) or a PCB (not shown). The direct copper interconnections have the advantages of fast switching, high frequency, and can withstand high voltage and large current. Thus, semiconductor package 200 is suitable for high-efficiency power modules. In addition, the direct copper interconnections also enhance the heat dissipation of semiconductor package 200, thereby making the operation of power module 100 more reliable, especially at high temperatures.

[0059] Figure 19b A top view of embodiment 260 is shown, in which semiconductor package 200 has a package size of 37 millimeters (mm) x 23 millimeters (mm), in which 8 low-side semiconductor dies 202 are arranged in a matrix of 2 columns and 4 rows, located at the right side (low-side) of the figure; and 8 high-side semiconductor dies 204 are also arranged in a matrix of 2 columns and 4 rows, located at the left side (high-side) of the figure. Figure 19a A cross-sectional view of embodiment 260 is shown, in which all interconnections within semiconductor package 200 are formed by direct copper, i.e. interconnections between contact pads and low-side filled vias 2028 of low-side semiconductor dies 202 and high-side filled vias 2048 of high-side semiconductor dies 204, interconnections between low-side filled vias 2028 and high-side filled vias 2048 and first front-side RDLs 234 of front-side build-up layer 230, interconnections between first front-side RDLs 234 of front-side build-up layer 230 and copper pillars 206, and interconnections between copper pillars 206 and back-side RDLs 224 of back-side build-up layer 220, respectively. The direct copper also includes interconnections between first front-side RDLs 234 and second front-side RDLs 244 of front-side build-up layer 230 through filled grooves 240 in front-side build-up layer 230. Thus, functional circuits of low-side semiconductor dies 202 and high-side semiconductor dies 204 are led out from contact pads at low-side active faces 2022 and high-side active faces 2042 to back-side RDLs 224 of back-side build-up layer 220 at low-side inactive faces 2024 of low-side semiconductor dies 202 and high-side inactive faces 2044 of high-side semiconductor dies 204, respectively; and further led out to external devices, e.g. Figure 19bsemiconductor package 200 also has other arrangements of 8 low-side semiconductor dies 202 and 8 high-side semiconductor dies 204. It should also be understood that the semiconductor package 200 can also have other numbers of low-side semiconductor dies 202 and high-side semiconductor dies 204. The layout of the semiconductor package 200 is also shown here as a metal oxide semiconductor field effect transistor (MOSFET). Where the copper pillars 206 have two first copper pillars 2072 and one second copper pillar 2074 for two low-side sources and one low-side gate of the low-side semiconductor dies 202. The copper pillars 206 also have two third copper pillars 2076 and one fourth copper pillar 2078 for two high-side sources and one high-side gate of the high-side semiconductor dies 204. Meanwhile, the external connection layers 248 have one low-side external connection layer 2482 covering the low-side inactive faces 2024 of the low-side semiconductor dies 202, and one high-side external connection layer 2484 covering the high-side inactive faces 2044 of the high-side semiconductor dies 204, for low-side drains and high-side drains, respectively. The external connection layers 248 also have a first external connection layer 2486 and a second external connection layer 2487 electrically connected to the two first copper pillars 2072 and the one second copper pillar 2074 of the copper pillars 206, respectively. The external connection layers 248 also have a third external connection layer 2488 and a fourth external connection layer 2489 electrically connected to the two third copper pillars 2076 and the one fourth copper pillar 2078 of the copper pillars 206, respectively. In addition, Figure 19b It is also shown that the semiconductor package 200 has low-side gate current paths 2092 of the same length between all of the low-side semiconductor dies 202 and the second copper pillars 2074 as low-side gates; and high-side gate current paths 2094 of another length between all of the high-side semiconductor dies 204 and the fourth copper pillars 2078 as high-side gates. Thus, the semiconductor package 200 can be precisely controlled at the same time, i.e., to go to the “ON” state or the “OFF” state at the same time. The lengths of the low-side gate current paths 2092 and the high-side gate current paths 2094 can be the same or different. It should be understood that the semiconductor package 200 can also have other layouts for the low-side sources, low-side gates, and low-side drains, and other layouts for the high-side sources, high-side gates, and high-side drains. Variations in the layout of the semiconductor package 200 are also within the scope of the present disclosure.

[0060] Figure 20A second embodiment of steps S118 and S120 of the panel-level method S10 is shown. In contrast to the first embodiment described above (on the scale of sub-panels 250), the molded panel 210 is not segmented into sub-panels 250. Instead, forming the external connection layer 248 on the backside RDL 224 exposed at the backside dielectric layer 226 of the backside build-up layer 220 is performed on the scale of the molded panel 210. Then, the molded panel 210 (with the backside build-up layer 220, the frontside build-up layer 230, and the external connection layer 248) is cut directly into individual semiconductor packages 200 along the saw lines according to the design of the semiconductor package 200.

[0061] Figures 21a to 21c Further embodiments 270, 280, 290 of the semiconductor package 200 obtained from the panel-level method S10 are shown. Similar to embodiment 260, all embodiments 270, 280, and 290 have a backside build-up layer 220 and a frontside build-up layer 230. Figure 21a A cross-sectional view of embodiment 270 is shown. In contrast to embodiment 260, the frontside build-up layer 230 of embodiment 270 has only a first layer, but no second layer as described above. It is to be understood, however, that other embodiments with a frontside build-up layer 230 having 3 layers, 4 layers, or more layers are within the scope of the present disclosure. Figure 21b A cross-sectional view of embodiment 280 is shown. In contrast to embodiment 260, the frontside build-up layer 230 of embodiment 280 has no second frontside dielectric layer 246. Accordingly, the second frontside RDL 244 is not encapsulated. Figure 21c A cross-sectional view of embodiment 290 is shown. In contrast to embodiment 260, embodiment 290 has an external connection dielectric layer 249 for encapsulating the external connection layer 248; at the same time, the frontside build-up layer 230 has no second layer, and thus the recess 240 is exposed from the first frontside dielectric layer 236.

[0062] Figures 22a to 22d Further embodiments 300, 310, 320, and 330 of the semiconductor package 200 obtained from the panel-level method S10 are shown. In contrast to embodiment 260, embodiments 300, 310, 320, and 330 have no backside build-up layer 220; accordingly, the external connection layer 248 is formed directly on the back surface 2104 of the molded panel 210. Figure 22aA cross-sectional view of embodiment 300 is shown. Compared to embodiment 260, in embodiment 300, the low-side outer connection layer 2482 is in contact with the low-side inactive face 2024 of the low-side semiconductor die 202; the high-side outer connection layer 2484 is in contact with the high-side inactive face 2044 of the high-side semiconductor die 204; the first outer connection layer 2486 is in contact with the first copper pillar 2072, the second outer connection layer 2487 is in contact with the second copper pillar 2074, the third outer connection layer 2488 is in contact with the third copper pillar 2076, and the fourth outer connection layer 2489 is in contact with the fourth copper pillar 2078. Alternatively, if the accepted low-side semiconductor wafer and the accepted high-side semiconductor wafer have the conductive layer on their inactive wafer faces, respectively, as described above. That is, the process of forming the outer connection layer 248 can be skipped because the conductive layer on the accepted low-side semiconductor wafer and the accepted high-side semiconductor wafer will be retained and used as the outer connection layer 248 described above. Figure 22b A cross-sectional view of embodiment 310 is shown. Compared to embodiment 300, in embodiment 310, the front-side build-up layer 230 does not have the second front-side dielectric layer 246; therefore, the second front-side RDL 244 is exposed. Figure 22c A cross-sectional view of embodiment 320 is shown. Compared to embodiment 310, in embodiment 320, the front-side build-up layer 230 does not have the second layer; therefore, the fill-in recess 240 is exposed from the first front-side dielectric layer 236. Figure 22d A cross-sectional view of embodiment 330 is shown. Compared to embodiment 320, embodiment 330 also has an outer connection dielectric layer 249 encapsulating the outer connection layer 248; while the fill-in recess 240 is also exposed from the first front-side dielectric layer 236.

[0063] Figures 23a to 25b A step S122 of the panel-level method S10 is shown, which is to prepare a substrate 110 (e.g., a direct copper bonding (DBC) substrate or a ceramic substrate) having an outer connection mechanism 112. The substrate 110 can be made of any insulating material, such as a ceramic material, aluminum oxide (AI2O3), silicon nitride (Si3N4), aluminum nitride (AIN), or HPS (doped about 9% ZrO2 or zirconia toughened alumina (ZTA)). Figure 23aA cross-sectional view of the substrate 110 is shown, which has an alternating current (AC) conductive layer 1112, a first conductive layer 1102, a second conductive layer 1104, a third conductive layer 1106, a fourth conductive layer 1108, and a direct current (DC) conductive layer 1114, which are separated from each other, in order from left to right. The conductive layers 1112, 1102, 1104, 1106, 1108, 1114 can be made of any conductive material, such as metal, which is surface finished by any suitable method for providing a flat surface for input / output (I / O) connections. The surface finish can be made of a single layer of metal, such as tin, or a single layer of metal composite, such as nickel / gold. Alternatively, the surface finish can also be made of multiple layers. In some embodiments, the surface finish is made of Electroless Nickel Immersion Gold (ENIG) with two layers of metal surface coating, in which a first layer of nickel can be formed using an electroless plating chemical reaction; and then a very thin layer of gold is plated on top of the nickel layer. In other embodiments, the surface finish can be made of Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) by depositing electroless nickel plating, followed by electroless palladium plating, and finally immersion gold flash plating. Preferably, the conductive layers 1112, 1102, 1104, 1106, 1108, 1114 are formed by electroplating silver (Ag) to form the surface finish. The surface finish is chemically compatible with I / O connections to improve the stability of the connections. The thickness of the surface finish can be in the range of 1 micrometer (pm) to 10 micrometers (pm), preferably, in the range of 1 micrometer (pm) to 5 micrometers (pm), or more preferably, in the range of 1 micrometer (pm) to 3 micrometers (pm). Figure 23b A top view of the substrate 110 is shown as described in Figure 23a In one embodiment, for a semiconductor package 200 with a package size of 37 millimeters (mm) x 23 millimeters (mm), the substrate 110 can have a substrate size of 57 millimeters (mm) x 42 millimeters (mm) accordingly. The substrate 110 has a substrate thickness that can make the substrate 110 rigid enough to carry the semiconductor package 200. In one embodiment, the substrate thickness of the substrate 110 can be about 3 millimeters (mm). It can be appreciated that the substrate size and the substrate thickness can vary depending on the design of the power module 100; all variations are within the scope of the present disclosure. Figure 23b Further shown, the substrate 110 has a low-side wiring 1116 and a high-side wiring 1118 electrically coupled to the first conductive layer 1102 and the fourth conductive layer 1108, respectively.

[0064] In one embodiment, Figure 24a A top view of the external connection mechanism 112 is shown, which includes one alternating current (AC) copper clip 1122 on the left (high side) of the figure; and two direct current positive (DC+) copper clips 1124 and one direct current negative (DC-) copper clip 1126 on the right (low side) of the figure. Figure 24b A cross-sectional view of the external connection mechanism 112 along Figure 24a the cross-sectional line AA in FIG. 1 is shown. The copper clips 1122, 1124, 1126 have the same or similar structure, in which the first portion 114 has a substantially flat configuration, the third portion 118 has another substantially flat configuration, and the second portion 116 has a Z-shaped configuration. The second portion 116 firmly connects the first portion 114 and the third portion 118 to make the external connection mechanism 112 into a monolithic structure.

[0065] Figure 25a and Figure 25b The top view and the cross-sectional view, respectively, show that the external connection mechanism 112 can be coupled to the substrate 110 by coupling the alternating current (AC) copper clip 1122 to the AC conductive layer 1112, and coupling the DC+ copper clip 1124 and the DC- copper clip 1126 to the DC conductive layer 1114, respectively. Specifically, the coupling must create the first conductive junction 120 between the substrate 110 and the external connection mechanism 112. The coupling can be made by any suitable method, including conductive adhesives (e.g., epoxy-silver pastes). Preferably, the coupling is made by silver sintering, which uses silver (Ag) particles and high-temperature sintering to make the first conductive junction 120 between the substrate 110 and the external connection mechanism 112 electrically conductive and robust.

[0066] Therefore, the power module 100 can be used as an inverter that converts DC to AC. The DC+ copper clip 1124 and the DC- copper clip 1126 can be electrically connected to the positive and negative terminals of a direct current (DC) power source (e.g., a battery or other power storage device), respectively, as input terminals. Meanwhile, the alternating current (AC) copper clip 1122 is electrically connected to an alternating current (AC) appliance (e.g., a motor) as an output terminal. The function of the inverter is implemented by the semiconductor package 200, in which the input terminals are configured to electrically couple the DC power source to the low-side semiconductor dies 202; and the output terminal is configured to electrically couple the high-side semiconductor dies 204 to the AC appliance. Therefore, the power module 100 converts low-voltage DC power from the DC power source to high-voltage AC power for use by the AC appliance.

[0067] Alternatively, the power module 100 can also be used as a rectifier to convert AC to DC. The AC copper clip 1122 is electrically connected to an AC power source (e.g. household power grid) as an input; while the DC+ copper clip 1124 and the DC- copper clip 1126 are electrically connected to the positive and negative poles of a DC storage device or battery, respectively, as outputs. Thus, high voltage AC power from the AC power source is converted by the power module 100 to low voltage DC power to supply the DC storage device. It is understood that the power module 100 shown in FIG. 25 is just one embodiment of the power module 100, and other designs of the power module 100 are also included within the scope of the present disclosure.

[0068] Figures 26a to 27a One embodiment of the step S124 of the panel-level method S10 and one embodiment 400 of the power module 100 are shown. Figure 26a and Figure 26bThe semiconductor package 200 is mounted and coupled to the substrate 110 by coupling the first and second external connection layers 2486, 2487 to the fourth conductive layer 1108, coupling the low-side external connection layer 2482 to the third conductive layer 1106, coupling the high-side external connection layer 2484 to the second conductive layer 1104, and coupling the third and fourth external connection layers 2488, 2489 to the fourth conductive layer 1108, as shown in cross-sectional and top views, respectively. Similarly, the coupling must form the second conductive joint 122 between the substrate 110 and the semiconductor package 200. The coupling can be made by any suitable method, including conductive adhesives (e.g., epoxy-silver pastes). Preferably, the coupling is made by silver sintering, as described above. Since all of the low-side external connection layer 2482, the high-side external connection layer 2484, the first and second external connection layers 2486, 2487, the third and fourth external connection layers 2488, 2489, the first conductive layer 1102, the second conductive layer 1104, the third conductive layer 1106, the fourth conductive layer 1108, and the second conductive joint 122 are formed of conductive material, the functional circuitry of the low-side semiconductor die 202 and the high-side semiconductor die 204 will be routed from the low-side external connection layer 2482 and the high-side external connection layer 2484 of the semiconductor package 200, through the second conductive joint 122, to the second conductive layer 1104 and the third conductive layer 1106 of the substrate 110, respectively. The embodiment 260 is shown as the semiconductor package 200, but it should be understood that other embodiments described above can also be mounted and coupled to the substrate 110 as the semiconductor package 200. Furthermore, since the second conductive layer 1104 and the third conductive layer 1106 of the substrate 110, and the low-side external connection layer 2482 and the high-side external connection layer 2484 of the external connection layers 248, are formed with a surface finish as described above, which has a very flat surface, the second conductive joint 122 will be more robust and reliable, particularly when it is formed of the same conductive material, preferably silver plating.

[0069] Figure 27aA cross-sectional view is shown, where the monolithic signal lead 138 is mounted and coupled to the substrate 110. The coupling must create a third conductive joint 124 between the substrate 110 and the monolithic signal lead 138. Specifically, the monolithic signal lead 138 has a lead height that is greater than the package thickness of the semiconductor package 200. The monolithic signal lead 138 can be made of any conductive material, such as metal. Preferably, the monolithic signal lead 138 is made of copper (Cu) and is referred to as a copper lead. The monolithic signal lead 138 is electrically coupled to a gate driver (not shown) that controls the performance of the power module 100, such as the switching between the "ON" and "OFF" states of a power inverter. It should be understood that the monolithic signal lead 138 can be mounted prior to mounting the semiconductor package 200 to the substrate 110. As such, the power module 100 is formed as shown in an embodiment 400 that can be suitable for various power modules 100, such as a half-bridge inverter. Figure 27a An embodiment 400 of the power module 100 is shown, which can be suitable for various power modules 100, such as a half-bridge inverter.

[0070] Figure 27b An optional step S126 of the panel-level method S10 and another embodiment 410 of the power module 100 is shown, where a heat sink is attached to the substrate 110 in the embodiment 400 to form another embodiment 410 of the power module 100. Figure 27b A cross-sectional view is shown, where the heat sink 150 is used as one embodiment of the heat sink device that is attached to the bottom surface 1110 of the substrate 110 for more effective dissipation of heat generated by the semiconductor package 200.

[0071] Figure 28a and 28b An embodiment 420 of the power module 100 is shown, where the optional step S128 of the panel-level method S10 is performed after the embodiment 400 shown in steps S124 and Figure 27a the mounting of the monolithic signal lead 138 and the semiconductor package 200 to the substrate 110, Figure 28a A cross-sectional view is shown, where a module molding layer 140 is formed to encapsulate the substrate 110, the monolithic signal lead 138, the semiconductor package 200, and a portion of the external connection mechanism 112 coupled to the substrate 110. The module molding layer 140 can be formed from an insulating material, such as a molding material, by any suitable method. Then, a grinding process is performed on the module molding layer 140 by a grinding device 212 to expose a top portion 1382 of the monolithic signal lead 138 from the module molding layer 140, while a bottom portion 1384 of the monolithic signal lead 138 remains encapsulated in the module molding layer 140. At this point, Figure 28b A cross-sectional view is shown, where the embodiment 420 is formed after the optional step S128 is performed.

[0072] Figure 29An optional step S126 of the panel-level method S10 is shown to be performed on the embodiment 420, thereby forming another embodiment 430 of the power module 100. As above, the heat dissipating device (e.g., the heat sink 150) is attached to the substrate 110 to enhance the dissipation of heat generated from the semiconductor package 200. Figure 29 A cross-sectional view of the embodiment 430 is shown.

[0073] Figure 30a and 30b Another optional step S130 of the panel-level method S10 and an embodiment 440 of the power module 100 are shown. Unlike the embodiment 420, the embodiment 440 does not include the integral signal lead 138. Figure 30a A cross-sectional view is shown, in which a plurality of first signal leads 130 are mounted and coupled to the power module 100 and positioned around the semiconductor package 200. The first signal leads 130 can be formed of any electrically conductive material, such as metal. Preferably, the first signal leads 130 are formed of copper (Cu). Similarly, the third conductive joint 124 must be formed between the substrate 110 and the first signal leads 130. Specifically, the first signal leads 130 have another lead height, which is greater than the package thickness of the semiconductor package 200. After the module molding layer 140 is formed, a grinding process is performed on the module molding layer 140 by the grinding device 212, such that the lead upper surfaces 132 of the first signal leads 130 are exposed from the module molding layer 140.

[0074] Figure 30b A cross-sectional view is shown, in which a plurality of second signal leads 134 can be coupled to the plurality of first signal leads 130, respectively, by any suitable method, such as mechanically coupling the first signal leads 130 and the second signal leads 134 using fasteners 142. For example, the first signal leads 130 and the second signal leads 134 have inner threads and outer threads, respectively, which cooperate with each other to enable the first signal leads 130 and the second signal leads 134 to be mechanically secured together. The first signal leads 130 and the second signal leads 134 can be made of any electrically conductive material, such as metal. Preferably, the first signal leads 130 and the second signal leads 134 are made of copper (Cu); accordingly, their combination is referred to as copper pins. The first signal leads 130 and the second signal leads 134 are electrically coupled to a gate driver (not shown), which controls the performance of the power module 100, such as the switching between the "ON" state and the "OFF" state of the power inverter. Here, the embodiment 440 of the power module 100 as shown is formed. Figure 30b

[0075] Figure 30c ​An optional step S126 of performing a panel-level method S10 on embodiment 440 is shown, resulting in another embodiment 450 of power module 100. As above, the heat dissipating device (e.g. heat sink 150) is attached to substrate 110 at this stage for enhanced dissipation of heat generated from semiconductor package 200. Figure 30c A cross-sectional view of embodiment 450 is shown. For embodiments 400 to 450 of power module 100 as described above, semiconductor package 200 is mounted in a face-up manner, i.e. low-side active face 2022 of low-side semiconductor die 202 and high-side active face 2042 of high-side semiconductor die 204 face away from substrate 110. As a result, external connection layer 248 at backside build-up layer 220 has to be exposed for contact with substrate 110. In embodiments 290 and 330, semiconductor package 200 cannot be mounted in the face-up manner as external connection layer 248 is completely encapsulated in external connection dielectric layer 249.

[0076] In contrast to the face-up manner, semiconductor package 200 can also be mounted in a face-down manner, i.e. low-side active face 2022 of low-side semiconductor die 202 and high-side active face 2042 of high-side semiconductor die 204 face towards substrate 110. Figures 31a to 33b Further embodiments 460, 470, 480, 490, 500 and 510 of power module 100 are shown, wherein embodiment 290 of semiconductor package 200 is mounted in the face-up manner. In contrast to the face-up manner, the face-down manner brings semiconductor package 200 into direct contact with substrate 110, enhancing heat dissipation of semiconductor package 200 to substrate 110 as most of the heat is generated by the functional circuitry of semiconductor dies (e.g. low-side semiconductor die 202 and high-side semiconductor die 204). It is to be understood that embodiment 330 of semiconductor package 200 can also be mounted in the face-up manner.

[0077] Figure 31a A cross-sectional view of embodiment 460 is shown, which corresponds to embodiment 400, except that embodiment 290 of semiconductor package 200 is mounted in the face-down manner. Figure 31b A cross-sectional view of embodiment 470 is shown, which corresponds to embodiment 410, wherein heat sink 150 is attached to substrate 110.

[0078] Figure 32a A cross-sectional view of embodiment 480 is shown, which corresponds to embodiment 420, except that embodiment 290 of semiconductor package 200 is mounted in the face-down manner. Figure 32b A cross-sectional view of embodiment 490 is shown, which corresponds to embodiment 430, wherein heat sink 150 is attached to substrate 110.

[0079] Figure 33aA cross-sectional view of Embodiment 500 is shown, which corresponds to Embodiment 440, except that Embodiment 290 of the semiconductor package 200 is mounted face down. Figure 33b A cross-sectional view of embodiment 510 is shown, corresponding to embodiment 450, wherein the heat sink 150 is attached to the substrate 110. It should be understood that, although not shown, other embodiments of the power module 100 are also within the scope of this disclosure, namely by mounting other embodiments of the semiconductor package 200 onto the substrate 110, such as embodiments 280, 310 and 320 (which may also be mounted in the above-described upward configuration).

[0080] Figure 34a and 34b Two other embodiments 340 and 350 of the semiconductor package 200 are shown. From similar... Figure 13 Starting with the molded panel 210 shown (with a back-side build layer 220 and a front-side build layer 230), where the back-side RDL 224 is completely encapsulated within the back-side dielectric layer 226, if the first front-side dielectric layer 236 is made of a solder mask or photoimageable dielectric material, then the first thickness of this first front-side dielectric layer 236 is much smaller than that described above (e.g., 100 micrometers (μm)). In some embodiments, the first thickness is approximately 10 micrometers (μm), such as... Figure 34a As shown. Then, a pattern is formed using photolithography or photoimageable techniques, such as... Figure 14 The groove 238 shown exposes the first front-side RDL from the first front-side dielectric layer 236. Therefore, the groove 238 has a depth substantially equal to the first thickness of the first front-side dielectric layer 236, for example, approximately 10 micrometers (μm). As described above, in subsequent processes, including step S116, after separating the molded panel 210 from the second carrier 106 and the second heat-release film 108; and step S120, dividing the molded panel 210 into embodiment 340 of the semiconductor package 200, the groove 238 remains unfilled. Figure 34a A cross-sectional view of embodiment 340 thus produced is shown, in which the groove 238 remains unfilled. Similarly, for embodiment 350, the groove 238 also remains unfilled in the subsequent process. Embodiment 350 differs from embodiment 340 in that it does not have a back-side building layer 220; therefore, the external connecting layer 248 is formed directly on the rear surface 2104 of the molded panel 210. Figure 34b A cross-sectional view of the resulting embodiment 350 is shown, in which the groove 238 remains unfilled.

[0081] Figure 35aand 35b Another embodiment of step S124 of the panel-level method S10 is shown, which employs an embodiment 340 of the semiconductor package 200 to fabricate an embodiment 520 of the power module 100. Figure 35a A cross-sectional view is shown, in which the embodiment 340 is mounted in a face-down manner on and coupled to the substrate 110, with the recess 238 being unfilled. Figure 35b A cross-sectional view is shown, in which during the formation of the second conductive joint 122 between the substrate 110 and the embodiment 340 of the semiconductor package 200, a conductive adhesive (e.g., epoxy-silver pastes) enters and fills the recess 238 as silver sintering. In particular, the conductive adhesive (e.g., epoxy-silver pastes) has an adhesive thickness that is greater than the depth of the recess 238. For example, when the first thickness of the first front-side dielectric layer 236 is less than or about 10 micrometers (pm), the adhesive thickness of the conductive adhesive can be in the range of 10 to 20 micrometers (pm), or preferably about 14 micrometers (pm). Thus, in the embodiment 340 of the semiconductor package 200, the filled recess 240 is electrically coupled to the first front-side RDL 234 of the front-side build-up layer 230. Instead of the conductive adhesive (e.g., epoxy-silver pastes) and silver sintering process described above, solder materials, such as solder balls, can also be employed to fill the recess 238 through a solder reflowing process. Similarly, the solder has a solder thickness that is greater than the depth of the recess 238. For example, when the first thickness of the first front-side dielectric layer 236 is less than or about 10 micrometers (pm), the solder thickness can be in the range of 10 to 20 micrometers (pm), or preferably about 14 micrometers (pm). Similar to the description above for the embodiment 340 of the semiconductor package 200, the solder also enters and fills the recess 238 in the solder reflowing process. It should be understood that the embodiment 350 in which the recess 238 remains unfilled can also be mounted in a face-down manner, and then the recess 238 is filled during the formation of the second conductive joint 122.

[0082] Figure 36a and 36b Other embodiments 530, 540 of the power module 100 are shown, which have a liquid cooling system as another embodiment of the heat dissipation device. Figure 36a A cross-sectional view of the embodiment 530 of the power module 100 is shown, in which the semiconductor package 200 is mounted in a face-up manner on the substrate 110, with the first liquid cooling system 160 directly or indirectly (e.g., through an intermediate component 162, such as a heat dissipation metal layer) coupled to the semiconductor package 200. Figure 36aThe first liquid cooling system 160 is attached to the module molding layer 140 (as shown) while the second liquid cooling system 164 is also attached to the bottom surface 1110 of the substrate 110 for replacing the heat sink 150, thereby effectively dissipating the heat generated by the semiconductor package 200. Figure 36b A cross-sectional view is shown, the semiconductor package 200 is mounted onto the substrate 110 in a face-down manner. Similarly, the first liquid cooling system 160 is attached to the module molding layer 140 (as shown) while the second liquid cooling system 164 is also attached to the bottom surface 1110 of the substrate 110 for replacing the heat sink 150, thereby effectively dissipating the heat generated by the semiconductor package 200. Figure 36b A cross-sectional view is shown, the semiconductor package 200 is mounted onto the substrate 110 in a face-down manner. Similarly, the first liquid cooling system 160 is attached to the module molding layer 140 (as shown) while the second liquid cooling system 164 is also attached to the bottom surface 1110 of the substrate 110 for replacing the heat sink 150, thereby effectively dissipating the heat generated by the semiconductor package 200. Figure 36a ) or the external connection dielectric layer 249 (as shown) of the semiconductor package 200. Figure 36b ) or the external connection dielectric layer 249 (as shown) of the semiconductor package 200.

[0083] The present disclosure can be implemented in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the foregoing embodiments are to be considered in all respects only as illustrative and not restrictive, the scope of the disclosure being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein. In this application, unless otherwise stated, the terms "comprise", "comprises" and "comprising" are used in their open-ended, or "inclusive", sense, meaning that they include the listed elements but also permit the inclusion of additional, unrecited elements.

[0084] This patent application claims priority to Singapore application 10202303517V, the filing date of which is December 14, 2023, the disclosure of which is incorporated herein in its entirety.

Claims

1. A semiconductor package for a power module, characterized by, comprising: at least one high-side semiconductor die having a high-side active side and a high-side inactive side; at least one low-side semiconductor die having a low-side active side and a low-side inactive side; a plurality of vertical structures surrounding the at least one high-side semiconductor die and the at least one low-side semiconductor die, wherein each vertical structure has a front surface aligned with the high-side active side and the low-side active side, and a back surface aligned with the high-side inactive side and the low-side inactive side; a molding layer encapsulating the at least one high-side semiconductor die and the at least one low-side semiconductor die, and the plurality of vertical structures; a front-side build-up layer coupled to the high-side active side of the at least one high-side semiconductor die and the low-side active side of the at least one low-side semiconductor die, and the front surfaces of the vertical structures; a back-side build-up layer coupled to the high-side inactive side of the at least one high-side semiconductor die and the low-side inactive side of the at least one low-side semiconductor die, and the back surfaces of the vertical structures; and an external connection layer coupled to the back-side build-up layer. The vertical structures comprise a plurality of copper pillars, a plurality of molded interconnect substrate units, or a plurality of molded through via substrate units, or the vertical structures comprise a combination of any two or three of the copper pillars, the molded interconnect substrate units, and the molded through via substrate units.

2. The semiconductor package of claim 1, wherein 3. The semiconductor package of claim 1, wherein the high-side active side of the high-side semiconductor die, the low-side active side of the low-side semiconductor die, and the front surfaces of the vertical structures are exposed from a first molding surface of the molding layer; and the high-side inactive side of the high-side semiconductor die, the low-side inactive side of the low-side semiconductor die, and the back surfaces of the vertical structures are exposed from a second molding surface of the molding layer. The front-side build-up layer further comprises a front-side redistribution layer electrically coupled to the high-side active side of the high-side semiconductor die, the low-side active side of the low-side semiconductor die, and the front surfaces of the vertical structures; and 4. The semiconductor package of claim 1, wherein a front-side dielectric layer encapsulating the front-side redistribution layer. The back-side build-up layer further comprises: a back-side redistribution layer electrically coupled to the back surfaces of the vertical structures; and a back-side dielectric layer encapsulating the back-side redistribution layer.

5. The semiconductor package of claim 1, wherein 6. The semiconductor package of claim 1, wherein the at least one high-side semiconductor die comprises eight silicon carbide high-side metal-oxide-semiconductor field-effect transistors electrically coupled to a high-side gate; and the at least one low-side semiconductor die comprises eight silicon carbide low-side metal-oxide-semiconductor field-effect transistors electrically coupled to a low-side gate. The external connection layer comprises a low-side external connection layer in contact with the inactive side of the at least one low-side semiconductor die for a low-side drain; a high-side external connection layer in contact with the inactive side of the at least one high-side semiconductor die for a high-side drain; a first external connection layer in contact with a plurality of first copper pillars for a low-side source; 7. The semiconductor package of claim 6, wherein a second external connection layer in contact with a second copper pillar for a low-side gate; and a third external connection layer in contact with a third copper pillar for a high-side gate. ​ ​ ​ a third external connection layer in contact with a third copper pillar, serving as a high-side source; and a fourth external connection layer in contact with a fourth copper pillar, serving as a high-side gate.

8. A power module, characterized by comprising: a semiconductor package having at least one high-side semiconductor die and at least one low-side semiconductor die; a substrate on which the semiconductor package is mounted, wherein functional circuitry of the at least one low-side semiconductor die and at least one high-side semiconductor die is electrically led out of the substrate; an external connection mechanism coupled to the substrate for electrically leading out the power module; and at least one signal lead mounted on the substrate.

9. The power module of claim 8, wherein the at least one signal lead comprises a unitary signal lead, or a combination of a first signal lead and a second signal lead.

10. The power module of claim 9, wherein, further comprising: a module molding layer encapsulating the semiconductor package and the at least one signal lead, wherein a portion of the at least one signal lead is exposed from the module molding layer.

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