Chip packaging integrated structure for improving gate oxide stability of device
By connecting a bidirectional TVS diode in parallel between the gate and source/emitter of a MOSFET or IGBT chip, combined with the freewheeling protection of an FRD chip, the problem of easy gate oxide breakdown in traditional packaging structures is solved, and the device's high resistance to voltage surges and ESD is improved.
Patent Information
- Application Number
- CN202422985673.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-12-04
AI Technical Summary
Traditional packaging structures cannot effectively protect the gate oxide of MOSFET and IGBT devices, making them prone to gate oxide breakdown failure under high voltage surges, which in turn leads to ESD and EAS failures.
A bidirectional TVS diode is connected in parallel between the gate and source/emitter of a MOSFET or IGBT chip. Taking advantage of its characteristic of being lower than the chip's breakdown voltage, it preferentially breaks down to protect the gate oxide. Combined with an FRD chip, it provides a freewheeling path and enhances the device's resistance to voltage surges.
It improves the gate oxide stability of MOSFET and IGBT products, enhances ESD resistance, avoids gate oxide breakdown and EAS failure, and improves the voltage surge withstand level of the devices.
Smart Images
Figure CN223527181U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor packaging, especially to a chip packaging integrated structure for improving device gate oxide stability. BACKGROUND
[0002] With the development of power devices towards miniaturization and light weight, the requirements for power supply are also getting higher and higher, especially the integration, functionality and space occupation of devices on PCB (printed circuit board) are put forward higher requirements. MOSFET (metal-oxide-semiconductor field effect transistor) and IGBT (insulated gate bipolar transistor) as important components on power supply PCB, they play a key role in the field of power electronics. The voltage surge resistance of MOSFET and IGBT is crucial to the reliability of the device. The traditional packaging structure may not provide sufficient protection, resulting in the possibility of gate oxide breakdown failure of MOSFET or IGBT under high voltage surge, thus easily causing ESD (electrostatic discharge) and EAS (electrical surge) failure and other problems. SUMMARY
[0003] The utility model aims at overcoming the technical problem of poor gate oxide voltage surge resistance of MOSFET and IGBT products in the prior art, and provides a chip packaging integrated structure for improving device gate oxide stability.
[0004] The utility model provides a chip packaging integrated structure for improving device gate oxide stability, comprising a bidirectional TVS diode, a MOSFET chip or an IGBT chip, the bidirectional TVS diode is connected in parallel between the G pole and the E pole of the IGBT chip or between the G pole and the S pole of the MOSFET chip.
[0005] Wherein, the breakdown voltage of the bidirectional TVS diode is lower than the gate breakdown voltage of the IGBT chip or the MOSFET chip, therefore, the bidirectional TVS diode is preferentially broken down when voltage abnormal working condition occurs, thereby improving the gate oxide voltage surge resistance of MOSFET and IGBT products, and the breakdown of the bidirectional TVS diode is recoverable and will not cause substantial damage.
[0006] The bidirectional TVS diode can absorb transient large pulse voltage in both positive and negative directions, and clamp the voltage to a predetermined level, which can be applied to DC, AC circuit and occasions requiring positive and negative pole protection at the same time, and is used for suppressing transient voltage. The bidirectional TVS diode has a breakdown voltage V BR , a clamping voltage V RWM and a high current region clamping voltage V CL The distinction of the three parameters can protect other devices from the influence of surge in a relatively wide range of voltage parameters. BR RWM CL The distinction of the three parameters can protect other devices from the influence of surge in a relatively wide range of voltage parameters.
[0007] Optionally, when the bidirectional TVS diode is connected in parallel between the G terminal and the E terminal of the IGBT chip; the chip packaging integrated structure further comprises an FRD chip connected in parallel between the C terminal and the E terminal of the IGBT chip. The FRD chip provides a freewheeling channel to protect the IGBT chip.
[0008] Preferably, the back of the bidirectional TVS diode is stacked in the E terminal pad area of the IGBT chip, and the front of the bidirectional TVS diode is electrically connected to the G terminal of the IGBT chip through an external circuit. This is used to reduce the space occupied by the structure and improve the integration of the structure.
[0009] The external circuit can be a separate lead or a combination of a lead and a pin.
[0010] Preferably, the chip packaging integrated structure further comprises a frame, the frame has a first pin and a third pin, and the IGBT chip and the FRD chip are packaged in the frame.
[0011] The C terminal of the IGBT chip and the cathode of the FRD chip are bonded to the pad of the frame to form an electrical connection.
[0012] The G terminal of the IGBT chip is electrically connected to the first pin through a first lead, and the front of the bidirectional TVS diode is electrically connected to the first pin through a second lead. At this time, the first lead, the first pin, and the second lead constitute the external circuit.
[0013] The E terminal of the IGBT chip is electrically connected to the third pin through a third lead, and the anode of the FRD chip is electrically connected to the third pin through a fourth lead.
[0014] Optionally, when the bidirectional TVS diode is connected in parallel between the G terminal and the S terminal of the MOSFET;
[0015] The back of the bidirectional TVS diode is stacked in the S terminal pad area of the MOSFET chip, and the front of the bidirectional TVS diode is electrically connected to the G terminal of the IGBT chip through an external circuit. This is used to reduce the space occupied by the structure and improve the integration of the structure.
[0016] Preferably, the chip packaging integrated structure further comprises a frame, the frame has a first pin and a third pin, and the MOSFET chip is packaged in the frame.
[0017] The D terminal of the MOSFET chip is bonded to the pad of the frame to form an electrical connection.
[0018] The G pole of the MOSFET chip is electrically connected with the first pin through a first lead wire, and the positive pole of the bidirectional TVS diode is electrically connected with the first pin through a second lead wire, so that the first lead wire, the first pin and the second lead wire form the external circuit.
[0019] The S pole of the MOSFET chip is electrically connected with the third pin through a third lead wire.
[0020] Compared with the prior art, the chip packaging integrated structure has the advantages that:
[0021] 1. The chip packaging integrated structure for improving the stability of device gate oxide is provided, and the bidirectional TVS diode chip is connected in parallel between the G pole and the S pole of the MOSFET chip or between the G pole and the E pole of the IGBT chip, so that the stability of device gate oxide is improved, the gate oxide voltage impact resistance of the MOS or IGBT product is enhanced, the gate oxide breakdown failure is not prone to occur, the ESD resistance of the device is improved, and the EAS failure is not prone to occur. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 FIG. 1 is a circuit structure schematic diagram of a chip packaging integrated structure corresponding to an IGBT chip according to the embodiment 1 of the utility model.
[0023] Figure 2 FIG. 2 is a circuit structure schematic diagram of a chip packaging integrated structure corresponding to a MOSFET chip according to the embodiment 1 of the utility model.
[0024] Figure 3 FIG. 3 is a packaging structure schematic diagram of the chip packaging integrated structure corresponding to the IGBT chip according to the embodiment 1 of the utility model.
[0025] Figure 4 FIG. 4 is a packaging structure schematic diagram of the chip packaging integrated structure corresponding to the MOSFET chip according to the embodiment 1 of the utility model.
[0026] Markings in the drawing:
[0027] 1-bidirectional TVS diode; 2-MOSFET chip; 21-S pole pad area; 3-IGBT chip; 31-E pole pad area; 4-FRD chip; 5-frame; 51-first pin; 52-second pin; 53-third pin; 54-first lead wire; 55-second lead wire; 56-third lead wire; 57-fourth lead wire. DETAILED DESCRIPTION
[0028] The utility model will be described in further detail below in connection with specific embodiments. However, this should not be understood as limiting the scope of the above-mentioned subject matter of the utility model to the following embodiments only, and any technology realized based on the content of the utility model falls within the scope of the utility model.
[0029] In addition, the terms "first", "second", "third", and the like appearing in the description are merely used to distinguish the same or similar components and should not be understood as emphasizing or implying the relative importance of the specific components.
[0030] In addition, in the description of the technical solutions of the utility model, unless otherwise explicitly specified / limited / limited, the terms "provided", "installed", "connected", "connected", "provided", "laid", "arranged" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected, such as welding, riveting, bolting, screwing, etc. The connection means commonly used in the art. Such connection can be mechanical connection, electrical connection or communication connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be connected inside two elements.
[0031] As shown in Figures 1-4 A chip packaging integrated structure for improving the stability of the gate oxide of a device, comprising a bidirectional TVS diode 1, a MOSFET chip 2 or an IGBT chip 3, wherein the MOSFET chip 2 has a G pole (gate), an S pole (source) and a D pole (drain), and the IGBT chip 3 has a G pole (gate), a C pole (collector) and an E pole (emitter).
[0032] The bidirectional TVS diode 1 is connected in parallel between the G pole and the E pole of the IGBT chip or between the G pole and the S pole of the MOSFET chip 2.
[0033] Embodiment 1
[0034] For the chip packaging integrated structure in which the bidirectional TVS diode 1 is connected in parallel between the G pole and the E pole of the IGBT chip, it further comprises an FRD (fast recovery diode) chip for reverse current conduction of the IGBT chip, reducing the possibility of damage to the IGBT chip in the circuit by reverse voltage.
[0035] For the circuit structure of the chip packaging integrated structure, as shown in Figure 1 The bidirectional TVS diode 1 is connected in parallel between the G pole and the E pole of the IGBT chip, and the FRD chip 4 is connected in parallel between the C pole and the E pole of the IGBT chip.
[0036] For the packaging structure of the chip packaging integrated structure, as shown in Figure 3As shown, the chip packaging integrated structure further includes a frame 5 having a first pin 51, a second pin 52, and a third pin 53, wherein the second pin 52 is a connection structure of the frame 5 itself and does not form a connection with the circuit.
[0037] The back of the bidirectional TVS diode 1 chip is stacked above the E pole pad area 31 of the IGBT chip through solder to achieve electrical connection, the G pole of the IGBT chip forms electrical connection with the first pin 51 of the frame 5 through the first lead wire 54, and the front of the bidirectional TVS diode 1 chip forms electrical connection with the first pin 51 of the frame 5 through the second lead wire 55. At this time, the bidirectional TVS diode 1 and the G pole and the E pole of the IGBT chip form a parallel relationship through the chip stacking scheme; the E pole of the IGBT chip forms electrical connection with the third pin 53 of the frame 5 through the third lead wire 56, the cathode of the FRD chip 4 is adhered to the PAD (pad) of the frame 5 through solder to form electrical connection, and the anode of the FRD chip 4 forms electrical connection with the third pin 53 of the frame 5 through the fourth lead wire 57. At this time, the FRD chip 4 and the C pole and the E pole of the IGBT chip form a parallel relationship.
[0038] Through the implementation scheme, the gate voltage impact resistance of the IGBT chip is enhanced, gate oxide breakdown failure is not easy to occur, the ESD resistance of the device is improved, can be improved from several hundred volts to several thousand volts, and EAS failure is not easy to occur.
[0039] Embodiment 2
[0040] For the chip packaging integrated structure in which the bidirectional TVS diode 1 is connected in parallel between the G pole and the S pole of the MOSFET chip 2, the MOSFET chip 2 is built-in with a diode, and reverse current continuation is not required for the MOSFET chip 2, so the FRD chip 4 can be excluded.
[0041] For the circuit structure of the chip packaging integrated structure, as shown in Figure 2 The bidirectional TVS diode 1 is connected in parallel between the G pole and the S pole of the MOSFET chip 2.
[0042] For the packaging structure of the chip packaging integrated structure, as shown in Figure 4 The chip packaging integrated structure further includes a frame 5 having a first pin 51, a second pin 52, and a third pin 53, wherein the second pin 52 is a connection structure of the frame 5 itself and does not form a connection with the circuit.
[0043] The back of the bidirectional TVS diode 1 chip is stacked on the S electrode pad area 21 of the MOSFET chip 2 through solder to realize electrical connection, the G electrode of the MOSFET chip 2 is electrically connected with the first pin 51 of the frame 5 through the first lead wire 54, and the front of the bidirectional TVS diode 1 chip is electrically connected with the first pin 51 of the frame 5 through the second lead wire 55, at this time, the bidirectional TVS diode 1 and the G electrode and the S electrode of the MOSFET chip 2 form a parallel relationship through the chip stacking scheme; the S electrode of the MOSFET chip 2 is electrically connected with the third pin 53 of the frame 5 through the third lead wire 56. The D electrode of the MOSFET chip 2 is adhered on the PAD of the frame 5 through solder to realize electrical connection.
[0044] The implementation scheme makes the gate voltage impact resistance of the MOSFET chip enhanced, the gate oxide breakdown failure is not easy to occur, the ESD resistance of the device is improved, can be improved from several hundred volts to several thousand volts, and the EAS failure is not easy to occur.
[0045] The above only describes the preferred embodiment of the utility model, and does not limit the utility model, and any modification, equivalent replacement and improvement within the spirit and principle of the utility model should be included in the protection scope of the utility model.
Claims
1. A chip packaging integrated structure for improving the gate oxide stability of a device, characterized in that, The bidirectional TVS diode (1) is connected in parallel between the G pole and the E pole of the IGBT chip (3) or between the G pole and the S pole of the MOSFET chip (2).
2. The chip package integrated structure for improving the stability of the gate oxide of a device according to claim 1, wherein, The bidirectional TVS diode (1) is connected in parallel between the G pole and the E pole of the IGBT chip (3). The FRD chip (4) is further included, which is connected in parallel between the C pole and the E pole of the IGBT chip (3).
3. The chip package integrated structure for improving the stability of the gate oxide of a device according to claim 2, wherein, The back of the bidirectional TVS diode (1) is stacked on the E pole pad area (31) of the IGBT chip (3), and the front of the bidirectional TVS diode (1) is electrically connected with the G pole of the IGBT chip (3) through an external circuit.
4. The chip package integrated structure for improving the stability of the gate oxide of a device according to claim 3, wherein, The frame (5) is further included, which has a first pin (51) and a third pin (53), and the IGBT chip (3) and the FRD chip (4) are packaged in the frame (5). The C pole of the IGBT chip (3) and the cathode of the FRD chip (4) are bonded to the pad of the frame (5). The G pole of the IGBT chip (3) is electrically connected with the first pin (51) through a first lead (54), and the front of the bidirectional TVS diode (1) is electrically connected with the first pin (51) through a second lead (55). The E pole of the IGBT chip (3) is electrically connected with the third pin (53) through a third lead (56), and the anode of the FRD chip (4) is electrically connected with the third pin (53) through a fourth lead (57).
5. The chip package integrated structure for improving the stability of the gate oxide of a device according to claim 1, wherein, The bidirectional TVS diode (1) is connected in parallel between the G pole and the S pole of the MOSFET chip (2). The back of the bidirectional TVS diode (1) is stacked on the S pole pad area (21) of the MOSFET chip (2), and the front of the bidirectional TVS diode (1) is electrically connected with the G pole of the IGBT chip (3) through an external circuit.
6. The chip package integrated structure for improving the stability of the gate oxide of a device according to claim 5, wherein, The frame (5) is further included, which has a first pin (51) and a third pin (53), and the MOSFET chip (2) is packaged in the frame (5). The D pole of the MOSFET chip (2) is bonded to the pad of the frame (5). The G pole of the MOSFET chip (2) is electrically connected with the first pin (51) through a first lead (54), and the front of the bidirectional TVS diode (1) is electrically connected with the first pin (51) through a second lead (55). The S pole of the MOSFET chip (2) is electrically connected with the third pin (53) through a third lead (56).