Impact current suppression circuit suitable for power load characteristics

Abstract

The utility model discloses an impulse current suppression circuit suitable for power supply load characteristics, which belongs to the technical field of power supply circuits, and comprises a direct current power supply, a filter and an anti-reverse-connection slow start circuit, the anti-reverse-connection slow start circuit comprises two NMOS (N-channel metal oxide semiconductor) tubes V2 and V3 which are connected in parallel, two voltage-regulator tubes V1 and V4, resistors R1 to R4 and capacitors C1 and C2, wherein the capacitor C1 and the resistor R1 are connected in series to form a time-delay circuit, the input end of the time-delay circuit is connected to the positive electrode of the filter, and the output end of the time-delay circuit is connected to the NMOS tube V2; the set resistance value of a resistor R1 is increased in the time delay circuit, and the resistor R1 is used for receiving the filtered direct-current voltage and prolonging the time of starting the voltage, so that the time delay conduction time of the NMOS tube V2 is prolonged, and the impact current suppression is realized; on the basis of an existing slow start circuit, parameters are adjusted, the resistance for controlling and driving the MOS tube to open a loop is increased, the current is reduced, the opening time of the MOS tube is effectively prolonged, and the current spike pulse is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of impact current suppression circuit suitable for power load characteristic, belong to power circuit technical field. BACKGROUND

[0002] Impact current suppression circuit can effectively suppress the impact current of power-on moment, and return to rated current within a certain time, and has important role in power load characteristic LDC101 test.LDC101 test requires that impact current is not greater than 6 times rated current and returns to rated current within 10ms, and the recovery rated current time is much smaller than the requirement of 100ms specified in GJB181B, and the condition is strict.

[0003] The existing impact current suppression circuit uses slow start circuit, and because filter is in front stage of slow start circuit, there is large capacitor at filter input end, voltage slowly rises in circuit fast power-on moment, and does not transient, according to power conservation principle, large current spike pulse is generated on input power line, and the time of returning to rated current is greater than 10ms, not meeting the requirement of power load characteristic LDC101. UTILITY MODEL CONTENT

[0004] The utility model aims at overcoming the deficiency in prior art, and provides an impact current suppression circuit suitable for power load characteristic, which adjusts parameters, increases the resistance of control drive MOS pipe opening loop, reduces current, effectively increases MOS pipe opening time and reduces current spike pulse on the basis of existing slow start circuit.

[0005] To achieve the above-mentioned purpose, the utility model is implemented by the following technical scheme:

[0006] In the first aspect, the utility model provides an impact current suppression circuit suitable for power load characteristic, which comprises:

[0007] DC power supply, which is used for outputting DC voltage;

[0008] Filter, which is used for receiving DC voltage input by DC power supply and outputting filtered DC voltage;

[0009] Anti-reverse connection slow start circuit, which comprises two NMOS tubes V2 and V3 connected in parallel, two voltage stabilizing tubes V1 and V4, resistors R1-R4 and capacitors C1 and C2, wherein:

[0010] It comprises two NMOS tubes V2 and V3, two voltage stabilizing tubes V1 and V4, resistors R1-R4 and capacitors C1 and C2, wherein:

[0011] One end of resistor R1 and resistor R4 is connected to the positive electrode of filter respectively;

[0012] The other end of the resistor R1 is connected to the one end of the voltage stabilizing tube V1, the capacitor C1 and the resistor R2 respectively, the other end of the voltage stabilizing tube V1 and the capacitor C1 is connected to the S end of the NMOS tube V2, the other end of the resistor R2 is connected to the G end of the NMOS tube V2;

[0013] The other end of the resistor R4 is connected to the one end of the voltage stabilizing tube V4, the capacitor C2 and the resistor R3 respectively, the other end of the voltage stabilizing tube V4 and the capacitor C2 is connected to the S end of the NMOS tube V3, the other end of the resistor R3 is connected to the G end of the NMOS tube V3; and the voltage stabilizing tube V4 is grounded;

[0014] The D end of the NMOS tube V2 and the D end of the NMOS tube V3 are connected to each other, and the S end of the NMOS tube V2 is connected to the negative electrode of the filter;

[0015] The setting resistance value of the resistor R1 in the first delay circuit is increased, which is used for receiving the filtered direct current voltage, prolonging the time of the opening voltage, thereby prolonging the delay conduction time of the NMOS tube V2, and realizing the impact current suppression.

[0016] Further, the filter is used for receiving 18V-32V direct current power input, and filtering through the filter.

[0017] Further, the delay conduction of the NMOS tube V2 is realized by the following way: the opening voltage of the G and S ends of the NMOS tube V2 slowly rises, and the delay time τ is calculated according to the following formula:

[0018] τ=R1xC1 (1);

[0019] Wherein R1 is the resistance value of the resistor R1, and C1 is the capacitance value of the capacitor C1.

[0020] Further, in the first delay circuit, the impact current is represented by the following formula:

[0021] I=dQ / dt (2);

[0022] Wherein I is the impact current, Q is the charge quantity, and t is the time of the current passing through.

[0023] Wherein Q=C1U1; C1 is the capacitance value of the capacitor C1, and U1 is the voltage value between the two ends of the capacitor C1.

[0024] Further, it further includes a current limiting resistor R5, one end of the current limiting resistor R5 is connected to the negative electrode of the filter, and the other end is connected to the common end of the NMOS tube V2 and the NMOS tube V3.

[0025] Further, the current limiting resistor is an ohmic power resistor.

[0026] Compared with the prior art, the utility model has the beneficial effects that:

[0027] 1. The utility model provides a kind of impact current suppression circuit suitable for power load characteristic, by adjusting parameter on the basis of existing slow start circuit, increase the resistance of control drive MOS pipe opening loop, reduce current, effectively increase MOS pipe opening time, reduce current peak pulse;

[0028] 2, the utility model increases a current limiting resistor at the two ends of MOS pipe, the time less than 10ms back to rated current, meet power load characteristic LDC101 requirement. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is a kind of impact current suppression circuit suitable for power load characteristic of the utility model embodiment schematic diagram. DETAILED DESCRIPTION

[0030] The utility model is further described below in conjunction with the drawings. The following embodiments are only used to more clearly illustrate the technical scheme of the utility model, and cannot limit the protection scope of the utility model.

[0031] In the description of the utility model, it needs to be understood that the orientation or positional relationship indicated by terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the utility model. In addition, the terms "first", "second" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features limited by "first", "second" and the like can explicitly or implicitly include one or more features. In the description of the utility model, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0032] In the description of the utility model, it is necessary to explain, unless there is definite stipulation and limitation, the term "installation", "link", "connection" should do broad sense understanding, for example, can be fixed connection, also can be detachable connection, or integrally connected;Can be mechanical connection, also can be electrical connection;Can be directly connected, also can be indirectly connected through intermediate medium, can be the intercommunication of two elements inside.For ordinary skilled person in the art, the specific meaning of the above-mentioned term in the utility model can be understood through specific circumstances.

[0033] Embodiment 1, this embodiment introduces a kind of impact current suppression circuit suitable for power load characteristic, suitable for power load characteristic LDC101 test.The circuit as shown in Figure 1

[0034] Impact current suppression circuit is mainly composed of filter, anti-reverse connection slow start circuit, current-limiting resistance etc.Product in power load characteristic LDC101 test, the moment of fast power-on, because the input and output end capacitance value of filter is larger, pulse current is generated on power positive line, NMOS slowly opens, and impact current is effectively inhibited.Current-limiting resistance R5 further limits the size of current in the moment of power-on, can be back to within rated current within 10ms.

[0035] Filter:

[0036] Voltage is 18V~32V DC power input to filter, after filtering in capacitor, differential mode, common mode inductance filtering, relevant high, low frequency interference signals can be effectively filtered out, guarantee the electromagnetic compatibility characteristics of product meet the test requirements.

[0037] Anti-reverse connection slow start circuit:

[0038] Anti-reverse connection slow start circuit is composed of two NMOS V2, V3, two voltage stabilizing tubes V1, V4, resistance R1~4, capacitor C1~C2, and the circuit is symmetrical structure, wherein:

[0039] The one end of resistance R1, resistance R4 is connected to the positive pole of filter respectively;

[0040] The other end of resistance R1 is connected to voltage stabilizing tube V1, capacitor C1 and one end of resistance R2 respectively, the other end of voltage stabilizing tube V1, capacitor C1 is connected to the S end of NMOS V2, the other end of resistance R2 is connected to the G end of NMOS V2;

[0041] The other end of resistance R4 is connected to voltage stabilizing tube V4, capacitor C2 and one end of resistance R3 respectively, the other end of voltage stabilizing tube V4, capacitor C2 is connected to the S end of NMOS V3, the other end of resistance R3 is connected to the G end of NMOS V3;And voltage stabilizing tube V4 is grounded; ​

[0042] The D end of the NMOS tube V2 and the D end of the NMOS tube V3 are connected to each other, and the S end of the NMOS tube V2 is connected to the negative electrode of the filter;

[0043] The capacitor C1 and the resistor R1 constitute a delay circuit, the direct current positive electrode of the filter passes through the resistors R1 and R2, the capacitor C1, the voltage stabilizing tube V1, and slowly forms an opening voltage, and finally reaches a value consistent with the voltage of the voltage stabilizing tube, and is input to the G and S ends of the NMOS tube V2.

[0044] The opening voltage at the G and S ends of the NMOS tube V2, that is, the voltage between the voltage stabilizing tubes V1, slowly rises, and the resistance values of R2 and R3 are small and can be ignored, and the rising time is shown in the following formula (1).

[0045] τ=R1×C1 (1);

[0046] Wherein R1 is the resistance value of the resistor R1, and C1 is the capacitance value of the capacitor C1.

[0047] The resistor R1 is optimally designed compared with the existing circuit, and the resistance value is increased to further prolong the opening voltage time.

[0048] In this process, the MOS tube is unsaturated and saturated according to the opening voltage.

[0049] The MOS tube is delayed to conduct, effectively reduces the slope of the external power supply voltage in the time domain, and the time from 0 to high level is lengthened, and when the charge amount is unchanged, the impact current is reduced. The impact current is shown in formula (2).

[0050] I=dQ / dt (2);

[0051] Wherein I is the impact current, Q is the charge amount, and t is the time through which the current passes.

[0052] Wherein Q=C1U1; C1 is the capacitance value of the capacitor C1, and U1 is the voltage value between the two ends of the capacitor C1.

[0053] Current limiting resistor:

[0054] One end of the current limiting resistor R5 is connected to the negative electrode of the filter, and the other end is connected to the common end of the NMOS tube V2 and the NMOS tube V3. The current limiting resistor R5 is a power resistor with an ohmic resistance value. At the moment of power-on, according to Ohm's law, the impact current is shown in the following formula (3).

[0055] I=U / R (3);

[0056] Wherein U is the voltage applied to the current limiting resistor R5, and R is the resistance value of the current limiting resistor R5.

[0057] Under the condition of constant voltage, the resistance string enters the negative line loop, and the current is further reduced. When the impact current falls, the load resistance increases due to the increase of the load power resistance R5, the current consumption time of energy storage is shortened, and the rated current can be returned within 10ms.

[0058] The embodiment adjusts parameters on the basis of the existing slow start circuit, increases the resistance of the circuit for controlling and driving the MOS tube to open, reduces the current, effectively increases the opening time of the MOS tube, and reduces the current sharp pulse; a current limiting resistance is added to the two ends of the MOS tube, and the time for returning to the rated current is less than 10ms. The requirement of the power load characteristic LDC101 is met.

[0059] The above is only the preferred embodiment of the present application, and it should be pointed out that for ordinary skilled persons in the technical field, several improvements and deformations can be made without departing from the technical principles of the present application, and these improvements and deformations should also be regarded as the protection range of the present application.

Claims

1. An inrush current suppressing circuit suitable for power load characteristics, characterized by, The application relates to a DC power supply, a filter and a reverse connection prevention and slow start circuit. The DC power supply is used for outputting a DC voltage. The filter is used for receiving the DC voltage input by the DC power supply and outputting a filtered DC voltage. The reverse connection prevention and slow start circuit comprises two NMOS tubes V2 and V3, two voltage stabilizing tubes V1 and V4, resistors R1 to R4 and capacitors C1 and C2. One end of the resistor R1 and one end of the resistor R4 are respectively connected to the positive pole of the filter. The other end of the resistor R1 is respectively connected to the voltage stabilizing tube V1, the capacitor C1 and one end of the resistor R2, the other end of the voltage stabilizing tube V1 and the capacitor C1 is connected to the S end of the NMOS tube V2, and the other end of the resistor R2 is connected to the G end of the NMOS tube V2. The other end of the resistor R4 is respectively connected to the voltage stabilizing tube V4, the capacitor C2 and one end of the resistor R3, the other end of the voltage stabilizing tube V4 and the capacitor C2 is connected to the S end of the NMOS tube V3, and the other end of the resistor R3 is connected to the G end of the NMOS tube V3; and the voltage stabilizing tube V4 is grounded. The D end of the NMOS tube V2 and the D end of the NMOS tube V3 are connected to each other, and the S end of the NMOS tube V2 is connected to the negative pole of the filter. The resistor R1 is used for receiving the filtered DC voltage, prolonging the opening voltage time, prolonging the delay conduction time of the NMOS tube V2 and realizing impact current suppression.

2. The inrush current suppression circuit adapted for power load characteristics according to claim 1, wherein, The filter is used for receiving the DC power supply input of 18V-32V and filtering through the filter.

3. The inrush current suppression circuit adapted for power load characteristics of claim 1, wherein, The delay conduction of the NMOS tube V2 is realized by slowly rising the opening voltage at the G and S ends of the NMOS tube V2, and the delay time tau is calculated according to the following formula: tau=R1xC1 (1); Wherein R1 is the resistance value of the resistor R1, and C1 is the capacitance value of the capacitor C1.

4. The inrush current suppression circuit adapted for power load characteristics of claim 1, wherein, The impact current is represented by the following formula: I=dQ / dt (2); Wherein I is the impact current, Q is the charge quantity, and t is the time through by the current. Wherein Q=C1U1; C1 is the capacitance value of the capacitor C1, and U1 is the voltage value at the two ends of the capacitor C1.

5. The inrush current suppression circuit adapted for power load characteristics of claim 1, wherein, The application further comprises a current limiting resistor R5, one end of the current limiting resistor R5 is connected to the negative pole of the filter, and the other end of the current limiting resistor R5 is connected to the common end of the NMOS tube V2 and the NMOS tube V3.

6. The inrush current suppression circuit suitable for power load characteristics according to claim 5, wherein, The current limiting resistor is an ohmic power resistor.

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