Parallel interleaved BUCK circuit and BUCK converter
By using synchronous interleaved control of parallel interleaved BUCK circuits and adjusting the duty cycle of the control chip using optocouplers and resistor voltage dividers, the problems of high cost and large current ripple of interleaved parallel BUCK circuits are solved, thereby improving circuit reliability and reducing cost.
Patent Information
- Application Number
- CN202422781708.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2034-11-14
AI Technical Summary
Existing interleaved parallel BUCK circuits are expensive, have large current ripple, and low reliability.
A parallel interleaved BUCK circuit is adopted. Through the synchronous interleaved control of the first and second threshold detection units and control chips U1 and U2, the parallel setting of the step-down chopper unit, and the use of optocouplers and resistor voltage dividers to adjust the duty cycle of the control chip, synchronous interleaved signal control is achieved.
It effectively reduces current ripple, improves circuit reliability, reduces costs, and eliminates the need for a microcontroller.
Smart Images
Figure CN223527977U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of BUCK circuit especially relates to a parallel staggered BUCK circuit and BUCK converter. BACKGROUND
[0002] With the improvement of power electronic device power level, the voltage and current stress of power device of converter is required more and more high, in order to comply with this trend, power semiconductor manufacturer develops to the direction of large capacity, puts the device of large on -state current, low on -state resistance in the market, such as CoolMos. Device manufacturer applies the mode of using several low capacity MOSFET in parallel when designing circuit to expand capacity. Parallel circuit is usually used to reduce the stress requirement of device.
[0003] For example, in the staggered parallel BUCK circuit, the MOS tube of each converter is staggered on, that is, the turn-on time in the switching cycle is staggered for a certain time, so that the current flowing in each converter also presents a staggered state. The advantage of this method is that it can reduce the effective value of input current ripple and output capacitor ripple current, and improve the power level of the circuit. However, controlling the staggered conduction of the MOS tube of each converter is usually realized by a single-chip microcomputer, which has high cost, and the staggered parallel BUCK circuit has the problems of large current ripple and low reliability in operation. SUMMARY
[0004] In view of the deficiencies in the prior art, the utility model provides a parallel staggered BUCK circuit and BUCK converter, which solves the problems of high cost, large current ripple and low reliability in the prior art.
[0005] At least one embodiment of the utility model provides a parallel staggered BUCK circuit, comprising: a first threshold detection unit, a second threshold detection unit, a first control chip U1, a second control chip U2, a target output end VOUT, a first voltage reduction chopping unit and a second voltage reduction chopping unit, wherein,
[0006] The first voltage reduction chopping unit and the second voltage reduction chopping unit are arranged in parallel, and the target output end VOUT is a common output end of the first voltage reduction chopping unit and the second voltage reduction chopping unit.
[0007] The input end of the first threshold detection unit is connected with the target output end VOUT, so as to output a preset level when the voltage of the target output end VOUT exceeds a preset voltage; the output end of the first threshold detection unit is connected with the pulse width modulation pin of the first control chip U1, so as to reduce the duty cycle of the signal of the output pin of the first control chip U1 when the preset level is output; and the synchronous clock input pin of the first control chip U1 also receives a first clock signal.
[0008] The input end of the second threshold detection unit is connected with the target output end VOUT, so as to output a preset level when the voltage of the target output end VOUT exceeds a preset voltage; the output end of the second threshold detection unit is also connected with the pulse width modulation pin of the second control chip U2, so as to reduce the duty cycle of the signal of the output pin of the second control chip U2 when the preset level is output; and the synchronous clock input pin of the second control chip U2 also receives a second clock signal.
[0009] The first clock signal and the second clock signal are synchronously staggered.
[0010] The output pin of the first control chip U1 is connected with the control end of the first voltage reduction chopping unit, and the output pin of the second control chip U2 is connected with the control end of the second voltage reduction chopping unit.
[0011] The technical scheme disclosed by the utility model has at least the following beneficial effects:
[0012] In the above circuit, when in use, the input voltage is output to the target output end VOUT after being reduced by the first voltage reduction chopping unit and the second voltage reduction chopping unit, at this time,
[0013] When the target output end VOUT passes through the first threshold detection unit, if the target output end VOUT is greater than the preset voltage, at this time, the first threshold detection unit outputs a preset level to the pulse width modulation pin of the first control chip U1, and then controls the pulse width, i.e. the duty cycle, of the output pin of the first control chip U1, so as to reduce the working duty cycle of the first voltage reduction chopping unit, thereby reducing the voltage of the target output end VOUT; similarly, when the target output end VOUT passes through the second threshold detection unit, if the target output end VOUT is greater than the preset voltage, at this time, the second threshold detection unit outputs a preset level to the pulse width modulation pin of the second control chip U2, and then controls the pulse width, i.e. the duty cycle, of the output pin of the second control chip U2, so as to reduce the working duty cycle of the second voltage reduction chopping unit, thereby stabilizing the voltage of the target output end VOUT.
[0014] The first control chip U1 and the second control chip U2 are controlled by the first clock signal and the second clock signal which are staggered synchronously, so that the output pins of the first control chip U1 and the second control chip U2 can be controlled by the staggered signals synchronously.
[0015] The control ends of the first voltage reduction chopper unit and the second voltage reduction chopper unit in the circuit receive pulses synchronously, so that the whole circuit has the characteristics similar to a single voltage reduction chopper unit.
[0016] In the parallel staggered BUCK circuit provided in one of the embodiments of the utility model, the first threshold detection unit comprises a first power supply VCC_1, a resistor R1, a resistor R4, a resistor R5, a first controllable precision voltage source U3 and a first optical coupler OT4, wherein,
[0017] The target output end VOUT is connected to the common end through the resistor R4 and the resistor R5 in sequence, and the target output end VOUT is connected to the reference end of the first controllable precision voltage source U3 through the resistor R4.
[0018] The first power supply VCC_1 is connected to the common end through the resistor R1, the anode end and the cathode end of the first optical coupler OT4, the cathode end and the anode end of the first controllable precision voltage source U3 in sequence.
[0019] The pulse width modulation pin of the first control chip U1 is connected to the common end through the collector and the emitter of the first optical coupler OT4 in sequence.
[0020] The technical scheme provided by the utility model has at least the following beneficial effects:
[0021] The voltage signal suitable for the reference end of the first controllable precision voltage source U3 can be received by the voltage division of the resistor R4 and the resistor R5 on the target output end VOUT.
[0022] After the target output end VOUT is greater than the preset voltage, the reference end of the first controllable precision voltage source U3 receives a corresponding voltage, thereby pulling down the voltage of the cathode end of the first controllable precision voltage source U3, so that the voltage between the anode end and the cathode end of the first optocoupler OT4 increases, thereby making the collector and the emitter of the first optocoupler OT4 conductive, and finally making the pulse width modulation pin of the first control chip U1 access the common end, thereby pulling down the signal of the pin, and through the pull-down of the pulse width modulation pin of the first control chip U1, the duty cycle of the signal output by the output pin of the first control chip U1 can be finally reduced.
[0023] In the parallel interleaved BUCK circuit provided in one of the embodiments of the utility model, the first threshold detection unit further comprises a first voltage loop, the first voltage loop comprises a resistor R2 and a capacitor C8, wherein,
[0024] The cathode end of the first controllable precision voltage source U3 is further connected with the reference end of the first controllable precision voltage source U3 through the resistor R2 and the capacitor C8 connected in series.
[0025] The technical scheme provided by the utility model has at least the following beneficial effects:
[0026] The first voltage loop can be used for loop control adjustment compensation.
[0027] In the parallel interleaved BUCK circuit provided in one of the embodiments of the utility model, the circuit further comprises a second voltage loop, the second voltage loop comprises a resistor R3 and a capacitor C7, wherein,
[0028] The pulse width modulation pin of the first control chip U1 is further connected with the common end through the resistor R3 and the capacitor C7 connected in series.
[0029] The technical scheme provided by the utility model has at least the following beneficial effects:
[0030] The second voltage loop can be used for loop control adjustment compensation.
[0031] In the parallel interleaved BUCK circuit provided in one of the embodiments of the utility model, the circuit further comprises a capacitor C1 and a capacitor C4, wherein,
[0032] The input end DC1 of the first voltage reduction chopper unit is connected with the common end through the capacitor C1, and the input end DC2 of the second voltage reduction chopper unit is connected with the common end through the capacitor C4.
[0033] The technical scheme provided by the utility model has at least the following beneficial effects:
[0034] The capacitor C1 and the capacitor C4 can be used to filter the input voltage of the input end DC1 of the first voltage reduction chopper unit and the input end DC2 of the second voltage reduction chopper unit.
[0035] In the parallel staggered BUCK circuit provided in one of the embodiments of the utility model, the first voltage reduction chopper unit comprises an input end DC1, a MOS tube Q2, a diode D3, an inductor L2 and a capacitor C2, wherein,
[0036] The input end DC1 is connected with the target output end VOUT in sequence through the drain and source of the MOS tube Q2, the inductor L2 and the target output end VOUT, the source of the MOS tube Q2 is also connected with the common end through the cathode and anode of the diode D3, the gate of the MOS tube Q2 is connected with the output pin of the first control chip U1, and the target output end VOUT is connected with the common end through the capacitor C2;
[0037] The second voltage reduction chopper unit comprises an input end DC2, a MOS tube Q1, a diode D1, an inductor L1 and a capacitor C5, wherein,
[0038] The input end DC2 is connected with the target output end VOUT in sequence through the drain and source of the MOS tube Q1, the inductor L1 and the target output end VOUT, the source of the MOS tube Q1 is also connected with the common end through the cathode and anode of the diode D1, the gate of the MOS tube Q1 is connected with the output pin of the second control chip U2, and the target output end VOUT is connected with the common end through the capacitor C5.
[0039] In the parallel staggered BUCK circuit provided in one of the embodiments of the utility model, the second threshold detection unit comprises a second power supply VCC_2, a resistor R6, a resistor R9, a resistor R10, a second controllable precision voltage source U4 and a second optical coupler OT3, wherein,
[0040] The target output end VOUT is connected with the common end in sequence through the resistor R9 and the resistor R10, and the target output end VOUT is connected with the reference end of the second controllable precision voltage source U4 through the resistor R9;
[0041] The second power supply VCC_2 is connected with the common end in sequence through the resistor R6, the anode end and the cathode end of the second optical coupler OT3, the cathode end and the anode end of the second controllable precision voltage source U4;
[0042] The pulse width modulation pin of the second control chip U2 is connected with the common end in sequence through the collector and the emitter of the second optical coupler OT3.
[0043] The technical scheme provided by the utility model has at least the following beneficial effects:
[0044] Similarly, the second controllable precision voltage source U4 reference end can receive a suitable voltage signal by the voltage division of the target output end VOUT through the resistance R9 and the resistance R10.
[0045] After the target output end VOUT is greater than the preset voltage, the reference end of the second controllable precision voltage source U4 receives a corresponding voltage, thereby pulling down the voltage of the cathode end of the second controllable precision voltage source U4, so that the voltage between the anode end and the cathode end of the second optocoupler OT3 increases, thereby making the collector and the emitter of the second optocoupler OT3 conductive, and finally making the pulse width modulation pin of the second control chip U2 access the common end, thereby pulling down the signal of the pin, and through the pull-down of the pulse width modulation pin of the second control chip U2, the duty cycle of the signal output by the output pin of the second control chip U2 can be finally reduced.
[0046] In a parallel interleaved BUCK circuit provided in one of the embodiments of the present application, the second threshold detection unit further comprises a third voltage ring, the third voltage ring comprising a resistance R7 and a capacitor C10, wherein,
[0047] The cathode end of the second controllable precision voltage source U4 is further connected to the reference end of the second controllable precision voltage source U4 through the resistance R7 and the capacitor C10 connected in series.
[0048] In a parallel interleaved BUCK circuit provided in one of the embodiments of the present application, the circuit further comprises a fourth voltage ring, the fourth voltage ring comprising a resistance R8 and a capacitor C9, wherein,
[0049] The pulse width modulation pin of the second control chip U2 is further connected to the common end through the resistance R8 and the capacitor C9 connected in series.
[0050] The technical scheme provided by the present application has at least the following beneficial effects:
[0051] The third voltage ring and the fourth voltage ring are both used for loop control adjustment compensation.
[0052] The present application also provides a BUCK converter, wherein the converter is configured with a parallel interleaved BUCK circuit as described above. BRIEF DESCRIPTION OF DRAWINGS
[0053] Figure 1 Part of the circuit diagram of the parallel interleaved BUCK circuit of the present application;
[0054] Figure 2 Part of the circuit diagram of the parallel interleaved BUCK circuit of the present application;
[0055] Figure 3The utility model relates to a partial circuit diagram of parallel staggered BUCK circuit.
[0056] In the drawing, the component list of each sign represented is as follows:
[0057] S1, first threshold detection unit, S2, second threshold detection unit, S3, first step-down chopper unit, S4, second step-down chopper unit. DETAILED DESCRIPTION
[0058] The principles and characteristics of the utility model are described below in combination with the drawings, and the examples are only used to explain the utility model and not used to limit the scope of the utility model.
[0059] The utility model provides a kind of parallel staggered BUCK circuit, please combine Figure 1 、 Figure 2 And Figure 3 It is shown, including: first threshold detection unit S1, second threshold detection unit S2, first control chip U1, second control chip U2, target output end VOUT, first step-down chopper unit S3 and second step-down chopper unit S4, wherein, the first control chip U1 and the second control chip U2 are both LM5020 chip, the 1 foot of first control chip U1 and second control chip U2 is input power supply pin VIN, 2 feet are feedback pin VFB, 3 feet are pulse width modulation COMP, 4 feet are chip power supply VCC, 5 is output pin OUT, 6 feet are chip ground pin GND, 7 feet are input undervoltage pin UVLO, 8 feet are current detection pin CS, 9 feet are oscillation frequency setting / synchronous clock input pin RT, 10 feet SS soft start;
[0060] The first step-down chopper unit S3 and the second step-down chopper unit S4 are arranged in parallel, and the target output end VOUT is the common output end of the first step-down chopper unit S3 and the second step-down chopper unit S4.
[0061] The target output end VOUT is connected with the input end of the first threshold detection unit S1, so as to output preset level when the voltage of the target output end VOUT exceeds preset voltage, in the embodiment, the preset level is low level, the output end of the first threshold detection unit S1 is connected with the pulse width modulation pin COMP of the first control chip U1, so as to reduce the duty cycle of the output pin OUT signal of the first control chip U1 when outputting preset level, and the synchronous clock input pin RT of the first control chip U1 also receives first clock signal through filter capacitor C6.
[0062] The target output end VOUT is connected with the input end of the second threshold detection unit S2, so as to output a preset level when the voltage of the target output end VOUT exceeds a preset voltage. The output end of the second threshold detection unit S2 is also connected with the pulse width modulation pin COMP of the second control chip U2, so as to reduce the duty cycle of the output pin OUT signal of the second control chip U2 when the preset level is output. The synchronous clock input pin RT of the second control chip U2 also receives a second clock signal through the filter capacitor C11.
[0063] The first clock signal and the second clock signal are synchronously staggered by 180°.
[0064] The output pin OUT of the first control chip U1 is connected with the control end of the first voltage reduction chopping unit S3, and the output pin OUT of the second control chip U2 is connected with the control end of the second voltage reduction chopping unit S4.
[0065] In the above circuit, when used, the input voltage is output to the target output end VOUT after being reduced by the first voltage reduction chopping unit S3 and the second voltage reduction chopping unit S4. At this time,
[0066] When the target output end VOUT passes through the first threshold detection unit S1, if the target output end VOUT is greater than a preset voltage, at this time, the first threshold detection unit S1 outputs a preset level to the pulse width modulation pin COMP of the first control chip U1, and then controls the pulse width of the output pin OUT of the first control chip U1, that is, the duty cycle, so as to realize the reduction of the working duty cycle of the first voltage reduction chopping unit S3, so as to reduce the voltage of the target output end VOUT. Similarly, when the target output end VOUT passes through the second threshold detection unit S2, if the target output end VOUT is greater than a preset voltage, at this time, the second threshold detection unit S2 outputs a preset level to the pulse width modulation pin COMP of the second control chip U2, and then controls the pulse width of the output pin OUT of the second control chip U2, that is, the duty cycle, so as to realize the reduction of the working duty cycle of the second voltage reduction chopping unit S4, so as to stabilize the voltage of the target output end VOUT.
[0067] Since the synchronous clock input pin RT of the first control chip U1 and the second control chip U2 receives the synchronously staggered first clock signal and the second clock signal, the synchronously staggered signal control of the output pin OUT of the first control chip U1 and the second control chip U2 can be realized.
[0068] The control end of the first voltage reduction chopper unit S3 and the second voltage reduction chopper unit S4 in the circuit receives a pulse in synchronization, so that the whole circuit has a characteristic similar to a single voltage reduction chopper unit, and the circuit works in synchronization at the same frequency to eliminate current ripple to the maximum extent. The switching signal of the control end of the first voltage reduction chopper unit S3 and the second voltage reduction chopper unit S4 is staggered by 180°, which greatly reduces the current ripple and improves the reliability of the circuit. Meanwhile, the circuit does not need to use a single-chip microcomputer, thereby reducing the corresponding cost.
[0069] Specifically, the first threshold detection unit S1 comprises a first power supply VCC_1, a resistor R1, a resistor R4, a resistor R5, a first controllable precision voltage source U3 and a first optical coupler OT4, wherein,
[0070] The target output end VOUT is connected to the common end through the resistor R4 and the resistor R5 in sequence, and the target output end VOUT is connected to the reference end of the first controllable precision voltage source U3 through the resistor R4.
[0071] The first power supply VCC_1 is connected to the common end through the resistor R1, the anode end and the cathode end of the first optical coupler OT4, the cathode end and the anode end of the first controllable precision voltage source U3 in sequence.
[0072] The pulse width modulation pin COMP of the first control chip U1 is connected to the common end through the collector and the emitter of the first optical coupler OT4 in sequence.
[0073] The voltage signal suitable for the reference end of the first controllable precision voltage source U3 is obtained through the voltage division of the target output end VOUT by the resistor R4 and the resistor R5.
[0074] After the target output end VOUT is greater than the preset voltage, the reference end of the first controllable precision voltage source U3 receives the corresponding voltage, thereby reducing the voltage at the cathode end of the first controllable precision voltage source U3, increasing the voltage between the anode end and the cathode end of the first optical coupler OT4, thereby making the collector and the emitter of the first optical coupler OT4 conductive, and finally making the pulse width modulation pin COMP of the first control chip U1 connected to the common end, thereby reducing the signal of the pin. By reducing the pulse width modulation pin COMP of the first control chip U1, the duty cycle of the signal output by the output pin OUT of the first control chip U1 can be finally reduced.
[0075] Specifically, the first threshold detection unit S1 further comprises a first voltage ring, and the first voltage ring comprises a resistor R2 and a capacitor C8.
[0076] The cathode end of the first controllable precision voltage source U3 is also connected to the reference end of the first controllable precision voltage source U3 through the series connection of the resistor R2 and the capacitor C8.
[0077] The first voltage ring can be used for loop control adjustment compensation.
[0078] Specifically, the circuit further comprises a second voltage ring, the second voltage ring comprising a resistor R3 and a capacitor C7, wherein,
[0079] The pulse width modulation pin COMP of the first control chip U1 is also connected to the common end through the series connection of the resistor R3 and the capacitor C7.
[0080] The second voltage ring can be used for loop control adjustment compensation.
[0081] Specifically, the circuit further comprises a capacitor C1 and a capacitor C4, wherein,
[0082] The input end DC1 of the first buck chopper unit S3 is connected to the common end through the capacitor C1, and the input end DC2 of the second buck chopper unit S4 is connected to the common end through the capacitor C4.
[0083] The capacitor C1 and the capacitor C4 can be used to filter the input voltage of the input end DC1 of the first buck chopper unit S3 and the input end DC2 of the second buck chopper unit S4.
[0084] Specifically, the first buck chopper unit S3 comprises an input end DC1, a MOS tube Q2, a diode D3, an inductor L2, and a capacitor C2, wherein,
[0085] The input end DC1 is connected to the target output end VOUT through the drain and source of the MOS tube Q2, the inductor L2 in sequence, the source of the MOS tube Q2 is also connected to the common end through the cathode and anode of the diode D3, the gate of the MOS tube Q2 is connected to the output pin OUT of the first control chip U1, and the target output end VOUT is connected to the common end through the capacitor C2.
[0086] The second buck chopper unit S4 comprises an input end DC2, a MOS tube Q1, a diode D1, an inductor L1, and a capacitor C5, wherein,
[0087] The input end DC2 is connected to the target output end VOUT through the drain and source of the MOS tube Q1, the inductor L1 in sequence, the source of the MOS tube Q1 is also connected to the common end through the cathode and anode of the diode D1, the gate of the MOS tube Q1 is connected to the output pin OUT of the second control chip U2, and the target output end VOUT is connected to the common end through the capacitor C5.
[0088] Specifically, the second threshold detection unit S2 comprises a second power supply VCC_2, a resistor R6, a resistor R9, a resistor R10, a second controllable precision voltage source U4 and a second optocoupler OT3, wherein,
[0089] The target output end VOUT is connected to the common end through the resistor R9 and the resistor R10 in sequence, and the target output end VOUT is connected to the reference end of the second controllable precision voltage source U4 through the resistor R9.
[0090] The second power supply VCC_2 is connected to the common end through the resistor R6, the anode end and the cathode end of the second optocoupler OT3, the cathode end and the anode end of the second controllable precision voltage source U4 in sequence.
[0091] The pulse width modulation pin COMP of the second control chip U2 is connected to the common end through the collector and the emitter of the second optocoupler OT3 in sequence.
[0092] Similarly, the voltage signal suitable for the reference end of the second controllable precision voltage source U4 can be received by the voltage division of the target output end VOUT through the resistor R9 and the resistor R10.
[0093] After the target output end VOUT is greater than the preset voltage, the reference end of the second controllable precision voltage source U4 receives the corresponding voltage, thereby reducing the voltage of the cathode end of the second controllable precision voltage source U4, increasing the voltage between the anode end and the cathode end of the second optocoupler OT3, thereby making the collector and the emitter of the second optocoupler OT3 conductive, and finally making the pulse width modulation pin COMP of the second control chip U2 connected to the common end, thereby reducing the signal of the pin, and finally realizing the reduction of the duty cycle of the signal output by the output pin OUT of the second control chip U2 by reducing the pulse width modulation pin COMP of the second control chip U2.
[0094] Specifically, the second threshold detection unit S2 further comprises a third voltage ring, and the third voltage ring comprises a resistor R7 and a capacitor C10, wherein,
[0095] The cathode end of the second controllable precision voltage source U4 is further connected to the reference end of the second controllable precision voltage source U4 through the resistor R7 and the capacitor C10 connected in series.
[0096] Specifically, the circuit further comprises a fourth voltage ring, and the fourth voltage ring comprises a resistor R8 and a capacitor C9, wherein,
[0097] The pulse width modulation pin COMP of the second control chip U2 is further connected to the common end through the resistor R8 and the capacitor C9 connected in series.
[0098] The third voltage ring and the fourth voltage ring are used to loop control adjustment compensation.
[0099] In summary, the working process of the circuit includes:
[0100] In use, after the input voltage is stepped down by the first step-down chopping unit S3 and the second step-down chopping unit S4, the input voltage is output to the target output end VOUT.
[0101] When the target output end VOUT passes through the first threshold detection unit S1, the voltage of the target output end VOUT is divided by the resistor R4 and the resistor R5, so that the reference end of the first controllable precision voltage source U3 can receive a suitable voltage signal.
[0102] After the target output end VOUT is greater than the preset voltage, the reference end of the first controllable precision voltage source U3 receives a corresponding voltage, thereby pulling down the voltage at the cathode end of the first controllable precision voltage source U3, increasing the voltage between the anode end and the cathode end of the first optocoupler OT4, thereby making the collector and the emitter of the first optocoupler OT4 conductive, and finally making the pulse width modulation pin COMP of the first control chip U1 connected to the common end, thereby pulling down the signal of the pin, and by pulling down the pulse width modulation pin COMP of the first control chip U1, the duty cycle of the signal output by the output pin OUT of the first control chip U1 can be finally reduced.
[0103] Similarly, the voltage of the target output end VOUT is divided by the resistor R9 and the resistor R10, so that the reference end of the second controllable precision voltage source U4 can receive a suitable voltage signal.
[0104] After the target output end VOUT is greater than the preset voltage, the reference end of the second controllable precision voltage source U4 receives a corresponding voltage, thereby pulling down the voltage at the cathode end of the second controllable precision voltage source U4, increasing the voltage between the anode end and the cathode end of the second optocoupler OT3, thereby making the collector and the emitter of the second optocoupler OT3 conductive, and finally making the pulse width modulation pin COMP of the second control chip U2 connected to the common end, thereby pulling down the signal of the pin, and by pulling down the pulse width modulation pin COMP of the second control chip U2, the duty cycle of the signal output by the output pin OUT of the second control chip U2 can be finally reduced.
[0105] Since the synchronous clock input pin RT of the first control chip U1 and the second control chip U2 receives the first clock signal and the second clock signal which are 180° staggered, the synchronous staggered signal control of the output pin OUT of the first control chip U1 and the second control chip U2 can be realized.
[0106] At this time, the switch period of the first voltage reduction chopper unit S3 and the second voltage reduction chopper unit S4 is T, and the conduction time is TON, then the switch frequency is f1=1 / T, the switch conduction ratio D=Ton / T, the switch frequency of the two-way staggered parallel BUCK converter is f=2f1, according to whether the minimum peak current flowing through the inductor is 0, it can be divided into continuous conduction mode (CCM) and discontinuous conduction mode (DCM), for the convenience of analysis, it is assumed that the inductance charging and discharging is linear, L1=L2=L, all devices are ideal devices, and the converter works in CCM and DCM critical inductance;
[0107] From Lc=Vo(1-D) / 2Io*f, when L>Lc, the converter works in CCM, when L<Lc, the converter works in DCM, and the output voltage ripple of a single BUCK is calculated as Vo(1-D) / 8*L*C*f1*f1, and since the frequency of the inductor in the above circuit is twice the switch frequency, the output voltage ripple of the above circuit is Vo(VIN-Vo) / 32*L*C*f1*f1*VIN, it can be seen that the circuit can reduce the size of input and output current ripple.
[0108] The control end of the first voltage reduction chopper unit S3 and the second voltage reduction chopper unit S4 in the circuit receives synchronous pulses, so that the whole circuit characteristics are similar to a single voltage reduction chopper unit, in order to maximize eliminate current ripple, the circuit works synchronously at the same frequency, the control end switch signal of the first voltage reduction chopper unit S3 and the second voltage reduction chopper unit S4 is staggered by 180°, which greatly reduces the current ripple, reduces the heating of the device, improves the efficiency, improves the reliability of the circuit, and the circuit does not need to use a single-chip microcomputer, reduces the corresponding cost.
[0109] The application also provides a BUCK converter, wherein the converter is provided with the parallel staggered BUCK circuit.
[0110] In addition, the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" can be explicitly or implicitly included at least one of the features. In the description of the application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.
[0111] In the utility model, unless another definite provision and limitation, the term " install " " link " " connect " " fixed " and so on term should do broad sense understanding, for example, can be fixed connection, also can be detachable connection, or be integrated;Can be mechanical connection, also can be electrical connection;Can be direct connection, also can pass through intermediate medium indirectly connect, can be two element inside's intercommunication or two element's mutual action relationship, unless another definite limitation.For the ordinary skill in the art, can understand the concrete meaning of the above-mentioned term in the utility model according to specific circumstances.
[0112] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, the skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.
[0113] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and the skilled in the art can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A parallel interleaved BUCK circuit, characterized by, The circuit comprises a first threshold detection unit (S1), a second threshold detection unit (S2), a first control chip U1, a second control chip U2, a target output end VOUT, a first voltage reduction chopping unit (S3) and a second voltage reduction chopping unit (S4), wherein The first voltage reduction chopping unit (S3) and the second voltage reduction chopping unit (S4) are connected in parallel, and the target output end VOUT is a common output end of the first voltage reduction chopping unit (S3) and the second voltage reduction chopping unit (S4); The input end of the first threshold detection unit (S1) is connected to the target output end VOUT, so as to output a preset level when the voltage of the target output end VOUT exceeds a preset voltage; the output end of the first threshold detection unit (S1) is connected to the pulse width modulation pin of the first control chip U1, so as to reduce the duty cycle of the output pin signal of the first control chip U1 when the preset level is outputted; and the synchronous clock input pin of the first control chip U1 also receives a first clock signal; The input end of the second threshold detection unit (S2) is connected to the target output end VOUT, so as to output a preset level when the voltage of the target output end VOUT exceeds a preset voltage; the output end of the second threshold detection unit (S2) is also connected to the pulse width modulation pin of the second control chip U2, so as to reduce the duty cycle of the output pin signal of the second control chip U2 when the preset level is outputted; and the synchronous clock input pin of the second control chip U2 also receives a second clock signal; The first clock signal and the second clock signal are synchronously staggered; The output pin of the first control chip U1 is connected to the control end of the first voltage reduction chopping unit (S3), and the output pin of the second control chip U2 is connected to the control end of the second voltage reduction chopping unit (S4). The first threshold detection unit (S1) comprises a first power supply VCC_1, a resistor R1, a resistor R4, a resistor R5, a first controllable precision voltage source U3 and a first optocoupler OT4, wherein 2. The interleaved BUCK circuit according to claim 1, wherein, The target output end VOUT is connected to a common end through the resistor R4 and the resistor R5 in sequence, and the target output end VOUT is connected to the reference end of the first controllable precision voltage source U3 through the resistor R4; The first power supply VCC_1 is connected to a common end through the resistor R1, the anode end and the cathode end of the first optocoupler OT4, the cathode end and the anode end of the first controllable precision voltage source U3 in sequence; The pulse width modulation pin of the first control chip U1 is connected to a common end through the collector and the emitter of the first optocoupler OT4 in sequence. The first threshold detection unit (S1) further comprises a first voltage ring, and the first voltage ring comprises a resistor R2 and a capacitor C8, wherein 3. The interleaved BUCK circuit according to claim 2, wherein, The cathode end of the first controllable precision voltage source U3 is also connected to the reference end of the first controllable precision voltage source U3 through the resistor R2 and the capacitor C8 connected in series. The circuit further comprises a second voltage ring, and the second voltage ring comprises a resistor R3 and a capacitor C7, wherein 4. The interleaved BUCK circuit according to claim 3, wherein, The cathode end of the second controllable precision voltage source U4 is also connected to the reference end of the second controllable precision voltage source U4 through the resistor R3 and the capacitor C7 connected in series. The pulse width modulation pin of the first control chip U1 is also connected to the common terminal through the resistance R3 and the capacitor C7 in series.
5. The interleaved BUCK circuit according to claim 4, wherein, The circuit further comprises a capacitor C1 and a capacitor C4, wherein, The input terminal DC1 of the first voltage reduction chopper unit (S3) is connected to the common terminal through the capacitor C1, and the input terminal DC2 of the second voltage reduction chopper unit (S4) is connected to the common terminal through the capacitor C4.
6. The interleaved BUCK circuit according to claim 5, wherein, The first voltage reduction chopper unit (S3) comprises an input terminal DC1, a MOS tube Q2, a diode D3, an inductor L2 and a capacitor C2, wherein, The input terminal DC1 is connected to the target output terminal VOUT through the drain and source of the MOS tube Q2, the inductor L2 in sequence, and the source of the MOS tube Q2 is also connected to the common terminal through the cathode and anode of the diode D3, the gate of the MOS tube Q2 is connected to the output pin of the first control chip U1, and the target output terminal VOUT is connected to the common terminal through the capacitor C2; The second voltage reduction chopper unit (S4) comprises an input terminal DC2, a MOS tube Q1, a diode D1, an inductor L1 and a capacitor C5, wherein, The input terminal DC2 is connected to the target output terminal VOUT through the drain and source of the MOS tube Q1, the inductor L1 in sequence, and the source of the MOS tube Q1 is also connected to the common terminal through the cathode and anode of the diode D1, the gate of the MOS tube Q1 is connected to the output pin of the second control chip U2, and the target output terminal VOUT is connected to the common terminal through the capacitor C5.
7. The interleaved BUCK circuit according to claim 1, wherein, The second threshold detection unit (S2) comprises a second power supply VCC_2, a resistance R6, a resistance R9, a resistance R10, a second controllable precision voltage source U4 and a second optical coupler OT3, wherein, The target output terminal VOUT is connected to the common terminal through the resistance R9 and the resistance R10 in sequence, and the target output terminal VOUT is connected to the reference terminal of the second controllable precision voltage source U4 through the resistance R9; The second power supply VCC_2 is connected to the common terminal through the resistance R6, the anode terminal and the cathode terminal of the second optical coupler OT3, the cathode terminal and the anode terminal of the second controllable precision voltage source U4 in sequence; The pulse width modulation pin of the second control chip U2 is connected to the common terminal through the collector and the emitter of the second optical coupler OT3 in sequence.
8. The interleaved BUCK circuit according to claim 7, wherein, The second threshold detection unit (S2) further comprises a third voltage ring, and the third voltage ring comprises a resistance R7 and a capacitor C10, wherein, The cathode terminal of the second controllable precision voltage source U4 is also connected to the reference terminal of the second controllable precision voltage source U4 through the resistance R7 and the capacitor C10 in series.
9. The interleaved BUCK circuit according to claim 8, wherein, The circuit further comprises a fourth voltage ring, and the fourth voltage ring comprises a resistance R8 and a capacitor C9, wherein, The pulse width modulation pin of the second control chip U2 is also connected to the common terminal through the resistance R8 and the capacitor C9 in series.
10. A BUCK converter, characterized by, The converter is configured with a parallel interleaved BUCK circuit as claimed in any one of claims 1 to 9.