Semiconductor device

Abstract

The embodiment of the utility model discloses a semiconductor device. The semiconductor device includes: a substrate; the buffer layer is positioned on one side of the substrate; the channel layer is located on the side, away from the substrate, of the buffer layer; the barrier layer is positioned on one side, far away from the substrate, of the channel layer; the gate structure comprises a gate cap layer, a gate gradient insertion layer and a gate metal layer; the gate cap layer, the gate gradual change insertion layer and the gate metal layer are sequentially arranged in the direction from the substrate to the gate structure; the gate metal layer covers part of the gate gradient insertion layer; the source electrode is located on the side, away from the substrate, of the barrier layer. The drain electrode is located on the side, away from the substrate, of the barrier layer. According to the technical scheme of the embodiment of the utility model, the gate gradual change insertion layer is arranged between the gate cap layer and the gate metal layer of the gate structure, so that the gate withstand voltage is improved, the gate electric field distribution is improved, and the gate reliability is improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] Gallium nitride (GaN) and other wide-bandgap semiconductor materials are widely used in power electronics, automotive, and aerospace fields due to their excellent high-temperature performance, chemical stability, and electronic properties. High-electron-mobility transistors (HEMTs) of GaN exhibit superior properties such as high electron mobility, high-temperature resistance, high-voltage resistance, and strong radiation resistance due to the high-density two-dimensional electron gas at the heterojunction interface. Because GaN HEMTs use Schottky contacts, as the voltage applied to the gate gradually increases, most of the increase falls on the Schottky junction, resulting in a high electric field at the Schottky interface. However, after long-term high gate voltage stress, the Schottky junction degrades, affecting the gate electric field distribution and reducing gate reliability.

[0003] In existing technologies, gate doping is improved or an aluminum gallium nitride (AGaN) material with a higher bandgap than gallium nitride (GaN) is added to the top of the gate. However, the current gate metal compound is mainly titanium nitride (TiN). When TiN is deposited on AGaN, a reaction between titanium and aluminum occurs, forming particle clusters and reducing gate reliability. Utility Model Content

[0004] This invention provides a semiconductor device to improve gate withstand voltage, improve gate electric field distribution, and enhance gate reliability.

[0005] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising:

[0006] Substrate;

[0007] Buffer layer; the buffer layer is located on one side of the substrate;

[0008] Channel layer; the channel layer is located on the side of the buffer layer away from the substrate;

[0009] Barrier layer; the barrier layer is located on the side of the channel layer away from the substrate;

[0010] Gate structure; the gate structure includes a gate cap layer, a gate gradient insertion layer, and a gate metal layer; in the direction from the substrate to the gate structure, the gate cap layer, the gate gradient insertion layer, and the gate metal layer are sequentially disposed; the gate metal layer covers a portion of the gate gradient insertion layer;

[0011] Source electrode; the source electrode is located on the side of the barrier layer away from the substrate;

[0012] Drain; the drain is located on the side of the barrier layer away from the substrate.

[0013] Optionally, the gate gradual change insertion layer comprises an aluminum component gradual change insertion layer.

[0014] Optionally, in the direction of the substrate pointing to the gate structure, the aluminum component gradual change insertion layer comprises at least three layers of Al x Ga (1-x) N layers, wherein x gradually changes from 1 to 0.

[0015] Optionally, in the direction of the substrate pointing to the gate structure, the aluminum component gradual change insertion layer comprises at least three layers of Al x Ga (1-x) N layers, wherein x gradually changes from 0 to 1.

[0016] Optionally, each layer of Al x Ga (1-x) N layer in the aluminum component gradual change insertion layer comprises a first conductive type doped layer, or a second conductive type doped layer, or a co-doped layer.

[0017] Optionally, the first conductive type doped layer comprises a silicon doped layer; the second conductive type doped layer comprises a magnesium doped layer; and the co-doped layer comprises a silicon-magnesium co-doped layer.

[0018] Optionally, the gate cap layer comprises a gallium nitride layer doped with a second conductive type.

[0019] Optionally, in the direction of the substrate pointing to the gate structure, the thickness of the gate gradual change insertion layer is greater than or equal to 2nm and less than or equal to 30nm.

[0020] Optionally, the semiconductor device further comprises a nucleation layer; the nucleation layer is located between the substrate and the buffer layer.

[0021] Optionally, the semiconductor device further comprises a high resistance layer; the high resistance layer is located between the buffer layer and the channel layer.

[0022] The technical scheme of the embodiment of the utility model provides a kind of semiconductor device, including substrate, buffer layer, channel layer, barrier layer, gate structure, source electrode and drain, wherein, gate structure includes gate cap layer, gate gradual change insertion layer and gate metal layer, by inserting gate gradual change insertion layer between gate cap layer and gate metal layer, the electric field distribution of the side of gate cap layer close to gate metal layer can be improved, and the local stronger electric field due to high doping is weakened.Aluminum gallium nitride material with gradually changed components is set, the current collapse phenomenon of gate cap layer is improved, the gradual transition of electric field can be better realized, the problems such as charge accumulation and electric field concentration at interface are reduced, and gate reliability is improved.

[0023] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1 is a cross-sectional structure schematic diagram of a semiconductor device according to an embodiment of the present application;

[0026] Figure 2 is a cross-sectional structure schematic diagram of a gate gradual change insertion layer according to an embodiment of the present application;

[0027] Figure 3 is a cross-sectional structure schematic diagram of another semiconductor device according to an embodiment of the present application;

[0028] Figure 4 is a cross-sectional structure schematic diagram of another gate gradual change insertion layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the person in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", and the like in the description and in the claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the utility model described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to the clearly listed steps or units, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] In order to solve the problem that the Schottky will degrade after long-term high gate voltage stress, affect the gate electric field distribution and reduce the gate reliability, the utility model embodiment provides the following technical scheme:

[0032] Figure 1 It is a sectional structure schematic diagram of a semiconductor device according to the utility model embodiment. As shown in Figure 1 The semiconductor device includes: substrate 10;Buffer layer 20;Buffer layer 20 is located at one side of substrate 10;Channel layer 30;Channel layer 30 is located at the side of buffer layer 20 away from substrate 10;Potential barrier layer 40;Potential barrier layer 40 is located at the side of channel layer 30 away from substrate 10;Gate structure 50;Gate structure 50 includes gate cap layer 501, gate gradual insertion layer 502 and gate metal layer 503;In the direction of substrate 10 pointing to gate structure 50, gate cap layer 501, gate gradual insertion layer 502 and gate metal layer 503 are sequentially arranged;Gate metal layer 503 covers part of gate gradual insertion layer 502;Source 60;Source 60 is located at the side of potential barrier layer 40 away from substrate 10;Drain 70;Drain 70 is located at the side of potential barrier layer 40 away from substrate 10.

[0033] In the embodiment of the utility model, the substrate 10 is the basic support structure of the whole semiconductor device, the substrate 10 provides physical support for each layer material grown on it, and ensures the stability of the whole device structure. The material of the substrate 10 includes silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) and the like, and different application scenarios will select the appropriate material of the substrate 10 according to the requirements of thermal conductivity, lattice matching and the like. For example, the GaN material is selected as the substrate 10, and when used for growing the device structure based on GaN, due to the high matching of the lattice structure of the substrate 10 itself and the epitaxial layer material, the lattice mismatch defects in the epitaxial layer growth process can be effectively reduced. For example, in the embodiment of the utility model, when the GaN HEMT is prepared, the GaN substrate can make the aluminum gallium nitride (AlGaN) and the like barrier layer 40 and the channel layer 30 grow higher in quality, which is beneficial to form high-quality two-dimensional electron gas, so as to improve the electrical performance of the device.

[0034] The buffer layer 20 plays a transitional role. Due to the differences in the lattice constant, the thermal expansion coefficient and the like of the material of the substrate 10 and the material of the active layer to be grown thereon, the buffer layer 20 can alleviate the stress problem caused by the lattice mismatch, reduce the generation of defects and improve the crystal quality. At the same time, the buffer layer 20 is helpful to improve the electrical performance of the subsequent growth layer and the uniformity of the crystal growth. For example, when the GaN HEMT device is formed, by growing a buffer layer 20, the dislocation and the like defects can be reduced, and the performance of the device can be improved. The buffer layer 20 can be an aluminum nitride (AlN) buffer layer.

[0035] The channel layer 30 is the key channel for electron transmission. For example, in the embodiment of the utility model, the channel layer 30 will utilize the two-dimensional electron gas formed at the heterojunction interface to realize efficient electron transmission. For example, in the AlGaN / GaN heterojunction, when the GaN layer is used as the channel layer 30, the two-dimensional electron gas generated at the interface can make the electrons move quickly, so that the device has excellent characteristics such as high frequency and high speed.

[0036] The barrier layer 40 restricts and regulates the carrier behavior in the channel layer 30 by forming a specific potential structure. In the HEMT device, the heterojunction interface formed by the barrier layer 40 (such as AlGaN) and the channel layer 30 (such as GaN) can generate two-dimensional electron gas, the barrier layer 40 has a limiting effect on electrons, making the electrons move in a specific region of the channel layer 30, thereby affecting the threshold voltage, conduction characteristics and other electrical parameters of the device, which is helpful to realize precise control of the current and improve the switching speed and other performances of the device.

[0037] The gate cap layer 501 can be a magnesium-doped GaN layer. The gate cap layer 501 regulates the carrier concentration in the channel layer 30 by applying an electric field, thereby controlling the on-off state of the current between the source 60 and the drain 70. For example, when a suitable voltage is applied to the gate cap layer 501, the conduction state of the channel layer 30 can be changed, realizing the switching function of the device, and the on-off state of the current can be controlled by changing the electric field by applying the voltage.

[0038] In the direction X of the substrate 10 pointing to the gate structure 50, the gate gradual insertion layer 502 is inserted between the gate cap layer 501 and the gate metal layer 503. For example, above the gate cap layer 501, the gate gradual insertion layer 502 can include an aluminum nitride layer, an aluminum gallium nitride layer with decreasing aluminum component and increasing gallium component, and a weak P-type or weak N-type doped gallium nitride layer arranged in sequence. The gate gradual insertion layer 502 can improve the electric field distribution of the side of the gate cap layer 501 close to the gate metal layer 503, weaken the local strong electric field caused by high doping, and the component-gradual aluminum gallium nitride material can improve the clustering phenomenon of particles formed by the reaction of the gate metal layer 503 being titanium nitride and the aluminum gallium nitride material. In addition, there is no lattice polarization effect caused by component mutation. By arranging the gate gradual insertion layer 502, a wider potential barrier can be enhanced, and the current collapse phenomenon of the gate cap layer 501 can be improved, such as improving the gate breakdown effect caused by defect-assisted tunneling, or improving the gate breakdown effect caused by avalanche breakdown due to the recombination of electron-hole pairs at the top of the gate cap layer 501 caused by high electric field. The gate gradual insertion layer 502 can be grown in situ by a metal-organic chemical vapor deposition (MOCVD) process or a molecular-beam epitaxy (MBE) process and subjected to corresponding ion doping, or can be formed by alternating growth using MOCVD and MBE. By arranging the gate gradual insertion layer 502, the gradual transition of the electric field can be better realized, and problems such as charge accumulation and electric field concentration at the interface can be reduced, which helps to improve the stability and reliability of the semiconductor device. In the embodiments of the present application, the gate gradual insertion layer 502 can alleviate the non-uniformity of the electric field of the gate cap layer 501 under high-voltage and large-current working conditions, and improve the reliability of the gate cap layer 501. The gate metal layer 503 is used to connect with an external circuit, so as to facilitate the control of the gate electric field by applying an external voltage signal.

[0039] The source 60 is usually formed by a deposition metal process, and the source 60 is in good electrical connection with an external power supply, thereby ensuring normal input of current. The drain 70 is usually formed by a deposition metal process, and the drain 70 ensures normal output of current. In the embodiments of the present application, the semiconductor device further includes a passivation layer 80. The passivation layer 80 can be arranged to protect the semiconductor device from the external environment.

[0040] The technical scheme of the embodiment of the utility model provides a kind of semiconductor device, including substrate, buffer layer, channel layer, barrier layer, gate structure, source and drain, wherein, gate structure includes gate cap layer, gate gradual insertion layer and gate metal layer, by inserting gate gradual insertion layer between gate cap layer and gate metal layer, the electric field distribution of gate cap layer side close to gate metal layer can be improved, weaken local stronger electric field due to high doping.Besides, aluminum gallium nitride material with gradually changing composition is arranged to improve the current collapse phenomenon of gate cap layer, better realize the gradual transition of electric field, reduce the problems such as charge accumulation and electric field concentration at interface, and improve the reliability of gate.

[0041] On the basis of the above-mentioned utility model embodiment technical scheme, reference Figure 1 Optionally, the gate gradual insertion layer 502 includes an aluminum composition gradual insertion layer.

[0042] In the embodiment of the utility model, the gate gradual insertion layer 502 includes aluminum gallium nitride material with gradually changing aluminum composition. The gradually changing aluminum composition can be understood as gradually decreasing or gradually increasing the concentration of aluminum. The aluminum gallium nitride material with gradually changing aluminum composition can improve the current collapse phenomenon of the gate cap layer 501, better realize the gradual transition of electric field, reduce the problems such as charge accumulation and electric field concentration at interface, and improve the reliability of gate.

[0043] On the basis of the above-mentioned utility model embodiment technical scheme, reference Figure 1 Optionally, in the direction of the substrate 10 pointing to the gate structure 50, the aluminum composition gradual insertion layer includes at least three layers of Al x Ga (1-x) N layer, wherein x gradually changes from 1 to 0.

[0044] In the embodiment of the utility model, in the direction X of the substrate 10 pointing to the gate structure 50, the aluminum composition gradual insertion layer includes at least three layers of Al x Ga (1-x) N layer, and along the direction X of the substrate 10 pointing to the gate structure 50, the aluminum composition gradually changes. For example, in the direction X of the substrate 10 pointing to the gate structure 50, the aluminum composition gradual insertion layer includes three layers of Al x Ga (1-x) N layer, and sequentially x=1, i.e. the aluminum composition is 1, to form an AlN layer, then grow upward, set x=0.5, i.e. form an Al 0.5 Ga 0.5 N layer, grow again, set x=1, i.e. form a GaN layer.

[0045] Figure 2 is a cross-sectional structure schematic diagram of a gate gradual insertion layer according to the embodiment of the utility model. For example Figure 2As shown, the gate gradual-change insertion layer 502 includes four Al x Ga (1-x) N layers, where x gradually changes from 1 to 0. Exemplarily, the values of x are 1, 0.7, 0.3 and 0 in sequence, i.e. AlN layer, Al 0.7 Ga 0.3 N layer, Al 0.3 Ga 0.7 N layer and GaN layer are formed in sequence. In other optional embodiments of the present application, the gate gradual-change insertion layer 502 can also include more than four Al x Ga (1-x) N layers, where x gradually changes from 1 to 0. By setting the gate gradual-change insertion layer 502 with gradually changing aluminum component, the current collapse phenomenon of the gate cap layer 501 is improved, the gradual transition of the electric field can be better realized, the problems such as charge accumulation and electric field concentration at the interface are reduced, and the gate reliability is improved.

[0046] Figure 3 is another sectional structure schematic view of a semiconductor device provided by an embodiment of the present application. As shown in the figure, Figure 3 the semiconductor device also includes a substrate 10, a buffer layer 20, a channel layer 30, a barrier layer 40, a gate structure 50, a source 60, a drain 70 and a passivation layer 80; the gate structure 50 includes a gate cap layer 501, a gate gradual-change insertion layer 502 and a gate metal layer 503; and Figure 1 the difference between the semiconductor device shown in the figure is the gradual-change rule of the aluminum component in the gate gradual-change insertion layer 502. Optionally, in the direction X of the substrate 10 pointing to the gate structure 50, the aluminum component gradual-change insertion layer includes at least three Al x Ga (1-x) N layers, where x gradually changes from 0 to 1.

[0047] In an embodiment of the present application, in the direction X of the substrate 10 pointing to the gate structure 50, the aluminum component gradual-change insertion layer includes at least three Al x Ga (1-x) N layers, and along the direction X of the substrate 10 pointing to the gate structure 50, the aluminum component gradually changes from less to more. Exemplarily, in the direction X of the substrate 10 pointing to the gate structure 50, the aluminum component gradual-change insertion layer includes three Al x Ga (1-x) N layers, and in sequence, x=0, i.e. the aluminum component is 0, a GaN layer is formed, and then grows, x=0.5 is set, i.e. an Al 0.5 Ga 0.5 N layer is formed, and then grows, x=1 is set, i.e. an AlN layer is formed.

[0048] Figure 4 is another sectional structure schematic view of a gate gradual-change insertion layer provided by an embodiment of the present application. As shown in the figure,Figure 4 As shown, the gate gradual change insertion layer 502 includes four layers of Al x Ga (1-x) N layers, where x gradually changes from 0 to 1. For example, x takes values of 0, 0.3, 0.7 and 1 in turn, i.e. forming a GaN layer, an Al 0.3 Ga 0.7 N layer, an Al 0.7 Ga 0.3 N layer and an AlN layer in turn. In other optional embodiments of the present application, the gate gradual change insertion layer 502 can also include more than four layers of Al x Ga (1-x) N layers, where x gradually changes from 0 to 1. By setting the gate gradual change insertion layer 502 with gradually changing aluminum components, the current collapse phenomenon of the gate cap layer 501 is improved, the gradual transition of the electric field can be better achieved, the problems such as charge accumulation and electric field concentration at the interface are reduced, and the gate reliability is improved.

[0049] On the basis of the technical scheme of the above-mentioned embodiment of the present application, optionally, each layer of Al x Ga (1-x) N in the aluminum component gradual change insertion layer includes a first conductive type doped layer, or a second conductive type doped layer, or a co-doped layer. In optional embodiments of the present application, the first conductive type doped layer includes a silicon doped layer; the second conductive type doped layer includes a magnesium doped layer; and the co-doped layer includes a silicon-magnesium co-doped layer.

[0050] In the embodiment of the present application, the first conductive type doped layer can include a silicon element. The second conductive type doped layer can include a magnesium element. The co-doped layer can include a silicon element and a magnesium element. The aluminum component gradual change insertion layer includes multiple layers of Al x Ga (1-x) N, and each layer of Al x Ga (1-x) N includes a silicon doped element, a magnesium doped element or both elements. The formed aluminum component gradual change insertion layer can significantly improve the gate electric field distribution and improve the gate reliability.

[0051] On the basis of the technical scheme of the above-mentioned embodiment of the present application, with reference to Figure 1 Optionally, the gate cap layer 501 includes a second conductive type doped gallium nitride layer.

[0052] In the embodiment of the present application, the gate cap layer 501 includes a magnesium doped gallium nitride layer.

[0053] On the basis of the technical scheme of the above-mentioned embodiment of the present application, with reference to Figure 1Optionally, the thickness of the gate gradual insertion layer 502 is greater than or equal to 2nm and less than or equal to 30nm in the direction in which the substrate 10 points to the gate structure 50.

[0054] In the embodiment of the present application, the thickness of the gate gradual insertion layer 502 is limited to be greater than or equal to 2nm and less than or equal to 30nm when the gate gradual insertion layer 502 is prepared and formed, thereby improving the reliability and practicability of the semiconductor device.

[0055] On the basis of the technical scheme of the above-mentioned embodiment of the present application, reference is made to Figure 1 Optionally, the semiconductor device further comprises a nucleation layer 100; the nucleation layer 100 is located between the substrate 10 and the buffer layer 20.

[0056] In the embodiment of the present application, the nucleation layer 100 is arranged between the substrate 10 and the buffer layer 20, thereby providing a large number of suitable nucleation sites for subsequent thin film growth. The density and size of the crystal nucleus can also be controlled by adjusting the surface properties of the nucleation layer 100, such as roughness, etc. The nucleation layer 100 can also improve the thin film quality and improve the thin film uniformity.

[0057] On the basis of the technical scheme of the above-mentioned embodiment of the present application, reference is made to Figure 1 Optionally, the semiconductor device further comprises a high resistance layer 200; the high resistance layer 200 is located between the buffer layer 20 and the channel layer 30.

[0058] In the embodiment of the present application, the high resistance layer 200 is arranged between the buffer layer 20 and the channel layer 30, thereby preventing current leakage, reducing the electric field peak value, improving the anti-interference ability of the semiconductor device, and improving the stability of the semiconductor device.

[0059] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, in sequence or in different order, as long as the desired results of the technical scheme of the present application can be achieved, which is not limited herein.

[0060] The above detailed description does not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor device, characterized by, Comprise: a substrate; a buffer layer; the buffer layer is located on one side of the substrate; a channel layer; the channel layer is located on the side of the buffer layer away from the substrate; a barrier layer; the barrier layer is located on the side of the channel layer away from the substrate; a gate structure; the gate structure comprises a gate cap layer, a gate graded insertion layer and a gate metal layer; the gate cap layer, the gate graded insertion layer and the gate metal layer are sequentially arranged in the direction of the substrate pointing to the gate structure; the gate metal layer covers part of the gate graded insertion layer; a source electrode; the source electrode is located on the side of the barrier layer away from the substrate; a drain electrode; the drain electrode is located on the side of the barrier layer away from the substrate.

2. The semiconductor device according to claim 1, wherein The gate graded insertion layer comprises an aluminum component graded insertion layer.

3. The semiconductor device of claim 2, wherein, In a direction in which the substrate is directed towards the gate structure, the aluminium composition graded interlayer comprises at least three layers of AlxGa1-xN, wherein x is graded from 1 to 0. x Ga (1-x) N layers.

4. The semiconductor device of claim 2, wherein In a direction in which the substrate is directed towards the gate structure, the aluminum composition graded interlayer comprises at least three layers of AlxGa1-xN, wherein x is graded from 0 to 1. x Ga (1-x) N layer, wherein x is graded from 0 to 1.

5. The semiconductor device according to claim 3 or 4, wherein each layer Al in the aluminum composition graded insertion layer x Ga (1-x) The GaN layer includes a first conductivity type doped layer, or a second conductivity type doped layer, or a co-doped layer.

6. The semiconductor device of claim 5, wherein, The first conductive type doped layer comprises a silicon doped layer; the second conductive type doped layer comprises a magnesium doped layer; and the co-doped layer comprises a silicon-magnesium co-doped layer.

7. The semiconductor device of claim 6, wherein, The gate cap layer comprises a second conductive type doped gallium nitride layer.

8. The semiconductor device of claim 1, wherein In the direction of the substrate pointing to the gate structure, the thickness of the gate graded insertion layer is greater than or equal to 2 nm and less than or equal to 30 nm.

9. The semiconductor device of claim 1, wherein Further comprise: a nucleation layer; The nucleation layer is located between the substrate and the buffer layer.

10. The semiconductor device of claim 9, wherein, Further comprise: a high resistance layer; the high resistance layer is located between the buffer layer and the channel layer.

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