Hardware design circuit for preventing direct connection of upper and lower bridge arms of MOS (Metal Oxide Semiconductor) tube

Abstract

The utility model relates to the technical field of electronic circuit design, and discloses an AND gate circuit comprising an upper bridge arm MOS tube, a lower bridge arm MOS tube, AND gate chips, resistors and comparators, the AND gate chips comprise a first AND gate chip and a second AND gate chip, the comparators comprise a first comparator and a second comparator, the resistors comprise a first resistor and a second resistor, and the resistors comprise a second resistor and a third resistor. A driving input signal of the initial upper bridge arm MOS tube is connected with a first end pin and a second end pin of the first AND gate chip, and is connected with a third end anode pin of the first comparator and a first end pin of the first resistor. According to the hardware design circuit for preventing direct connection of the upper and lower bridge arms of the MOS tubes, the MOS tubes of the upper and lower bridge arms cannot enter an open tube state at the same time through an AND gate and a comparator design logic circuit, a protection circuit is formed on the hardware level, the output of the MOS tubes forms a safe state, and under the condition that a software program is out of control, the hardware design circuit is safe and reliable. The hardware design can effectively prevent the straight-through risk of the upper and lower bridge arm MOS.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit design technology, specifically a hardware design circuit to prevent the upper and lower bridge arms of a MOS transistor from being directly connected. Background Technology

[0002] MOSFET, short for Metal-Oxide-Semiconductor Field-Effect Transistor, is a semiconductor field-effect transistor. MOSFETs are characterized by high input impedance, fast switching speed, low noise, and low power consumption. They are used in power management, motor control, communication electronics, consumer electronics, and industrial control. MOSFETs are a very important semiconductor device, widely used in electronic devices across various fields.

[0003] Existing methods for preventing shoot-through of the upper and lower MOSFET bridge arms are all programmed in software. In the event of software malfunction or program crash, it is difficult to prevent the upper and lower MOSFET bridge arms from being in a safe state, which can easily lead to shoot-through damage of the upper and lower MOSFET bridge arms. Therefore, there is an urgent need for a hardware design circuit to prevent shoot-through of the upper and lower MOSFET bridge arms to solve the above problems. Utility Model Content

[0004] (a) Technical problems to be solved

[0005] To address the shortcomings of existing technologies, this utility model provides a hardware design circuit to prevent shoot-through of the upper and lower MOSFET bridge arms. This solves the problem that in the event of software malfunction or program crashes, it is difficult to prevent the upper and lower MOSFET bridge arms from being in a safe state, which can easily lead to shoot-through damage of the upper and lower MOSFET bridge arms.

[0006] (II) Technical Solution

[0007] The technical solution of this utility model to solve the above-mentioned technical problem is as follows: A hardware design circuit for preventing direct conduction between the upper and lower bridge arms of a MOSFET, including an upper bridge arm MOSFET, a lower bridge arm MOSFET, an AND gate chip, resistors, and comparators. The AND gate chip includes a first AND gate chip and a second AND gate chip. The comparator includes a first comparator and a second comparator. The resistor includes a first resistor and a second resistor. The initial upper bridge arm MOSFET drive input signal is connected to the first and second pins of the first AND gate chip and to the positive pin of the third terminal of the first comparator and the first pin of the first resistor. The output signal of the first AND gate chip is connected to the fourth terminal. The output pin is connected to the negative pin of the fourth terminal of the second comparator. The output pin of the first comparator is connected to the drive output signal of the upper bridge arm MOSFET and the pin of the second terminal of the first resistor. The initial drive input signal of the lower bridge arm MOSFET is connected to the pins of the first and second terminals of the second AND gate chip, the positive pin of the third terminal of the second comparator, and the pin of the first terminal of the second resistor. The output pin of the second AND gate chip is connected to the negative pin of the fourth terminal of the first comparator. The output pin of the second comparator is connected to the drive output signal of the lower bridge arm MOSFET and the pin of the second resistor.

[0008] The beneficial effects of this utility model are:

[0009] This hardware design circuit for preventing shoot-through of the upper and lower bridge arms of the MOSFET uses AND gates and comparators to design logic circuits that prevent the upper and lower bridge arm MOSFETs from entering the on state simultaneously. This forms a protection circuit at the hardware level, ensuring that the output is in a safe state. In the event of software program malfunction, the hardware design can effectively prevent the risk of shoot-through of the upper and lower bridge arm MOSFETs, forming a secondary protection mechanism to increase safety.

[0010] Based on the above technical solution, the present invention can be further improved as follows.

[0011] Furthermore, the VCC pins of the first and second comparators are respectively connected to the VCC pin at terminal 5, and the GND pins of the first and second comparators are respectively connected to the GND pin at terminal 2.

[0012] Furthermore, the VCC pins of the first and second AND gate chips are respectively connected to the VCC pin at terminal 5, and the GND pins of the first and second AND gate chips are respectively connected to the GND pin at terminal 3. Attached Figure Description

[0013] Figure 1 Structural design block diagram;

[0014] Figure 2 Schematic diagram of drive signal transmission. Detailed Implementation

[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0016] In the embodiments, by Figure 1-2 The present invention provides a hardware design circuit for preventing shoot-through between the upper and lower bridge arms of a MOSFET. The present invention includes the upper bridge arm MOSFET, the lower bridge arm MOSFET, an AND gate chip, a resistor, and a comparator. The AND gate chip includes a first AND gate chip and a second AND gate chip. The comparator includes a first comparator and a second comparator. The resistor includes a first resistor and a second resistor.

[0017] The initial upper arm MOS transistor drive input signal is connected to the first and second pins of the first AND gate chip, and to the positive pin of the third terminal of the first comparator and the first pin of the first resistor. The output signal of the first AND gate chip is connected to the negative pin of the fourth terminal of the second comparator. The output of the first comparator is connected to the drive output signal of the upper arm MOS transistor and to the second pin of the first resistor.

[0018] The initial lower bridge arm MOSFET drive input signal is connected to the first and second pins of the second AND gate chip, the third positive pin of the second comparator, and the first pin of the second resistor. The fourth output pin of the second AND gate chip is connected to the fourth negative pin of the first comparator. The first output pin of the second comparator is connected to the drive output signal of the lower bridge arm MOSFET and the second pin of the second resistor.

[0019] The VCC pins of the first and second AND gate chips are respectively connected to the VCC pin at terminal 5, and the GND pins of the first and second AND gate chips are respectively connected to the GND pin at terminal 3.

[0020] The VCC pins of the first and second comparators are connected to the VCC pin at terminal 5, and the GND pins of the first and second comparators are connected to the GND pin at terminal 2.

[0021] Specifically, refer to Figure 1The upper arm drive input signal is divided into two paths. One path is connected to the lower arm secondary transmission signal input interface after the upper arm primary transmission signal is transmitted, and compared with the lower arm drive input signal to generate the lower arm drive output signal. The other path is connected to the upper arm secondary transmission signal input interface and compared with the lower arm primary transmission signal to generate the upper arm drive output signal.

[0022] The lower arm drive input signal is divided into two paths. One path is connected to the upper arm secondary transmission signal input interface after passing through the lower arm primary transmission signal. It is compared with the upper arm drive input signal to generate the upper arm output signal. The other path is connected to the lower arm secondary transmission signal input interface and compared with the upper arm primary transmission signal to generate the lower arm drive output signal.

[0023] Product design and operation logic:

[0024] 1. When the upper bridge arm MOSFET drive signal input is low and the lower bridge arm MOSFET drive signal input is low, the third input pin of the first comparator is low, the third input pin of the second comparator is low, the output signal of the first AND gate is low and connected to the negative input pin of the fourth terminal of the second comparator, and the output signal of the second AND gate is low and connected to the negative input pin of the fourth terminal of the first comparator. At this time, the first comparator outputs the upper bridge arm MOSFET drive signal as low, and the second comparator outputs the lower bridge arm MOSFET drive signal as low.

[0025] 2. When the upper bridge arm MOSFET drive signal input is low and the lower bridge arm MOSFET drive signal input is high, the third input pin of the first comparator is low, the third input pin of the second comparator is high, the output signal of the first AND gate is low and connected to the negative input pin of the fourth terminal of the second comparator, and the output signal of the second AND gate is high and connected to the negative input pin of the fourth terminal of the first comparator. At this time, the first comparator outputs the upper bridge arm MOSFET drive signal as low, and the second comparator outputs the lower bridge arm MOSFET drive signal as high.

[0026] 3. When the upper bridge arm MOSFET drive signal input is high and the lower bridge arm MOSFET drive signal input is low, the third input pin of the first comparator is high and the third input pin of the second comparator is low. The output signal of the first AND gate is high and connected to the negative input pin of the fourth terminal of the second comparator. The output signal of the second AND gate is low and connected to the negative input pin of the fourth terminal of the first comparator. At this time, the first comparator outputs the upper bridge arm MOSFET drive signal as high and the second comparator outputs the lower bridge arm MOSFET drive signal as low.

[0027] 4. When the upper bridge arm MOSFET drive signal input is high and the lower bridge arm MOSFET drive signal input is high, the third input pin of the first comparator is high, the third input pin of the second comparator is high, the output signal of the first AND gate is high and connected to the negative input pin of the fourth terminal of the second comparator, and the output signal of the second AND gate is high and connected to the negative input pin of the fourth terminal of the first comparator. At this time, the first comparator outputs the upper bridge arm MOSFET drive signal as low, and the second comparator outputs the lower bridge arm MOSFET drive signal as low.

[0028] The corresponding truth table is as follows:

[0029] PWM_IN_H PWM_IN_L PWM_OUT_H PWM_OUT_L 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0

[0030] When the software becomes uncontrollable or the program malfunctions during the operation of the entire circuit, and four different logic levels occur, as shown in the truth table above, the drive signals for driving the upper and lower bridge arm MOSFETs will not simultaneously be at a high level, causing the upper and lower bridge arm MOSFETs to be in a shoot-through state.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0032] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A hardware design circuit for preventing shoot-through of the upper and lower bridge arms of a MOSFET, characterized in that: It includes an upper bridge arm MOSFET, a lower bridge arm MOSFET, an AND gate chip, a resistor, and a comparator. The AND gate chip includes a first AND gate chip and a second AND gate chip. The comparator includes a first comparator and a second comparator. The resistor includes a first resistor and a second resistor. The initial upper arm MOSFET drive input signal is connected to the first and second pins of the first AND gate chip, the third positive pin of the first comparator, and the first pin of the first resistor. The fourth output pin of the first AND gate chip is connected to the fourth negative pin of the second comparator. The first output pin of the first comparator is connected to the drive output signal of the upper arm MOSFET and the second pin of the first resistor. The initial lower bridge arm MOSFET drive input signal is connected to the first and second pins of the second AND gate chip, the third positive pin of the second comparator, and the first pin of the second resistor. The fourth output pin of the second AND gate chip is connected to the fourth negative pin of the first comparator. The first output pin of the second comparator is connected to the drive output signal of the lower bridge arm MOSFET and the second pin of the second resistor.

2. The hardware design circuit for preventing shoot-through of the upper and lower bridge arms of a MOS transistor according to claim 1, characterized in that: The VCC pins of the first and second AND gate chips are respectively connected to the VCC pin at terminal 5, and the GND pins of the first and second AND gate chips are respectively connected to the GND pin at terminal 3.

3. The hardware design circuit for preventing shoot-through of the upper and lower bridge arms of a MOS transistor according to claim 1, characterized in that: The VCC pins of the first and second comparators are connected to the VCC pin at terminal 5, and the GND pins of the first and second comparators are connected to the GND pin at terminal 2.

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