Super junction chip structure
By setting stress relief grooves in the scribing area of the superjunction chip, the warping and fracture problems caused by stress during the manufacturing process of the superjunction chip are solved, improving product yield and charge balance effect, and enhancing chip stability.
Patent Information
- Application Number
- CN202423068586.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-11-11
- Estimated Expiration
- 2034-12-11
AI Technical Summary
In the current manufacturing process of superjunction chips, warping and fracture can occur due to differences in material stress, affecting product yield and charge balance.
First and second stress relief grooves are provided in the scribing area of the superjunction chip, extending in different directions and with a length of one-quarter to three-fifths of the photolithography unit size, to release stress during annealing and prevent warping and breakage.
It effectively relieves stress, improves product yield, enhances chip manufacturing alignment, and improves charge balance and internal voltage stability.
Smart Images
Figure CN223540865U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor device technology, and in particular to a superjunction chip structure. Background Technology
[0002] There are two main methods for manufacturing superjunction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) chips. One method is ion implantation followed by epitaxial growth, where ions are implanted at the same location on the substrate, followed by epitaxial growth, and this process is repeated until a superjunction structure is formed through thermal diffusion. The other method uses a deep trench process, where trenches are etched, with the width and depth determined by the design, and filled with P-type polysilicon to form the superjunction structure.
[0003] However, the above processes introduce additional stress during material introduction. Furthermore, due to the different thermal expansion coefficients of various materials, the relative contraction or expansion of the materials during chip annealing also generates stress. Unexpected stress generated during chip manufacturing, if not effectively released or eliminated, can cause warping of the chip surface material, resulting in distorted or displaced chip alignment marks, leading to problems in subsequent process identification and product defects. In some cases, the presence of stress can even cause the chip to fracture directly during annealing. Utility Model Content
[0004] The purpose of this invention is to provide a superjunction chip structure that can effectively release the stress generated during the manufacturing process of superjunction chips, improve product yield, improve the alignment effect of chip manufacturing, and thus enhance the charge balance effect of the superjunction structure.
[0005] To address the aforementioned technical problems, embodiments of this utility model provide a superjunction chip structure, comprising:
[0006] The system comprises: a plurality of strip-shaped first scribe lines extending along a first direction, the plurality of first scribe lines arranged along a second direction; a plurality of strip-shaped second scribe lines extending along the second direction, the plurality of second scribe lines arranged along the first direction; the first direction being perpendicular to the second direction; and a plurality of photolithography units defined by the first scribe lines and the second scribe lines, at least two of the photolithography units constituting a photolithography region, the photolithography region being at least one, the photolithography unit being used to form a target device; each of the first scribe lines on opposite sides of the photolithography region having a first stress relief groove; each of the second scribe lines on opposite sides of the photolithography region having a second stress relief groove; wherein the extension length of the first stress relief groove in the first direction is one-quarter to three-fifths of the size of the photolithography unit in the first direction, and the extension length of the second stress relief groove in the second direction is one-quarter to three-fifths of the size of the photolithography unit in the second direction.
[0007] Compared to the prior art, in this embodiment of the invention, multiple strip-shaped first scribe lines extending along a first direction are arranged at intervals along a second direction, and multiple strip-shaped second scribe lines extending along the second direction are arranged at intervals along the first direction. These multiple first and second scribe lines define multiple photolithography units, and at least two photolithography units constitute a photolithography region. First stress relief grooves and second stress relief grooves are respectively provided on the first and second scribe lines at the edge of the photolithography region. The extension length of the first stress relief groove along the first direction is one-quarter to three-fifths of the dimension of the photolithography unit in the first direction, and the extension length of the second stress relief groove along the second direction is one-quarter to three-fifths of the dimension of the photolithography unit in the second direction. This arrangement allows the first and second stress relief grooves to provide deformation allowance. During annealing after the superjunction chip is filled with material, the stress generated by the superjunction chip causes the first and second stress relief grooves to deform, preventing overall deformation of the superjunction chip, and thus releasing stress through the first and second stress relief grooves. In addition, by reasonably setting the extension length of the first stress relief groove and the second stress relief groove, the overall strength of the superjunction chip can be maintained while ensuring the stability of the superjunction chip structure.
[0008] Optionally, the first stress relief grooves on opposite sides of the photolithography area are arranged along the first diagonal of the photolithography area, and the second stress relief grooves on opposite sides of the photolithography area are arranged along the second diagonal of the photolithography area.
[0009] Optionally, there are multiple first stress relief grooves, which are spaced apart along the second direction; and / or, there are multiple second stress relief grooves, which are spaced apart along the first direction.
[0010] Optionally, there are multiple first stress relief grooves and multiple second stress relief grooves. A first isolation wall is provided between two adjacent first stress relief grooves, and a second isolation wall is provided between two adjacent second stress relief grooves. The first isolation wall and / or the second isolation wall are set as alignment marks for chip fabrication.
[0011] Optionally, the first scribing area between two adjacent lithography units in the lithography area is provided with a first stress relief groove; and / or, the second scribing area between two adjacent lithography units is provided with a second stress relief groove.
[0012] Optionally, the extension length of the first stress relief groove in the first direction is one-third to one-half of the dimension of the photolithography unit in the first direction.
[0013] Optionally, the extension length of the second stress relief groove in the second direction is one-third to one-half of the dimension of the photolithography unit in the second direction.
[0014] Optionally, the first stress relief groove and / or the second stress relief groove are straight grooves; or, the first stress relief groove and / or the second stress relief groove are wavy grooves; or, the first stress relief groove and / or the second stress relief groove are zigzag grooves.
[0015] Optionally, the cross-sectional shape of the first stress relief groove perpendicular to the first direction is trapezoidal; or, the cross-sectional shape of the first stress relief groove perpendicular to the first direction is square; or, the cross-sectional shape of the first stress relief groove perpendicular to the first direction is semi-circular.
[0016] Optionally, the cross-sectional shape of the second stress relief groove perpendicular to the second direction is trapezoidal; or, the cross-sectional shape of the second stress relief groove perpendicular to the second direction is square; or, the cross-sectional shape of the second stress relief groove perpendicular to the second direction is semi-circular. Attached Figure Description
[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0018] Figure 1 This is a schematic diagram of a wafer according to an embodiment of the present invention;
[0019] Figure 2 This is a schematic diagram of the photolithography area in an embodiment of the present invention;
[0020] Figure 3 This is a schematic diagram showing that the stress relief groove is linear in an embodiment of this utility model;
[0021] Figure 4 This is a schematic diagram showing that the stress relief groove is curved in an embodiment of this utility model;
[0022] Figure 5 This is a schematic diagram showing that the stress relief groove in this embodiment of the present invention is a polygonal shape;
[0023] Figure 6 yes Figure 2 A cross-sectional view along line AA';
[0024] Figure 7 When the stress relief groove is a trapezoidal groove Figure 6 Enlarged view of region A in the middle;
[0025] Figure 8 When the stress relief groove is a square groove Figure 6 Enlarged view of region A in the middle;
[0026] Figure 9 When the stress relief groove is a semi-circular groove Figure 6 An enlarged schematic diagram of region A in the middle. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the various embodiments of this utility model will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this utility model to facilitate a better understanding of this application. However, the technical solutions claimed in the claims of this application can be implemented even without these technical details and with various variations and modifications based on the following embodiments.
[0028] In this embodiment of the invention, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are primarily for the purpose of better describing this invention and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation.
[0029] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this utility model according to the specific circumstances.
[0030] Furthermore, the terms "installation," "setting," "equipped with," "opening," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this utility model based on the specific circumstances.
[0031] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, elements, or components (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, elements, or components. Unless otherwise stated, "a plurality of" means two or more.
[0032] During the manufacturing process of superjunction chips, due to the differences in the physical and chemical properties of different materials, superjunction chips are prone to stress, which can cause warping or even breakage, resulting in product defects.
[0033] To address the aforementioned technical problems, one embodiment of this utility model provides a superjunction chip structure, comprising: a plurality of strip-shaped first scribe regions extending along a first direction, the plurality of first scribe regions being arranged along a second direction; a plurality of strip-shaped second scribe regions extending along the second direction, the plurality of second scribe regions being arranged along the first direction; the first direction being perpendicular to the second direction; and a plurality of photolithography units defined by the first scribe regions and the second scribe regions, at least two of the photolithography units constituting a photolithography region, the photolithography region being at least one, the photolithography unit being used to form a target device; each of the first scribe regions on opposite sides of the photolithography region is provided with a first stress relief groove; each of the second scribe regions on opposite sides of the photolithography region is provided with a second stress relief groove; wherein, the extension length of the first stress relief groove in the first direction is one-quarter to three-fifths of the size of the photolithography unit in the first direction, and the extension length of the second stress relief groove in the second direction is one-quarter to three-fifths of the size of the photolithography unit in the second direction.
[0034] The implementation details of the superjunction chip structure in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.
[0035] See Figure 1 and Figure 2 The superjunction chip 100 has multiple strip-shaped first scribe regions 110 and multiple strip-shaped second scribe regions 120. The first scribe regions 110 extend along a first direction X and are spaced apart along a second direction Y. The multiple second scribe regions 120 extend along the second direction Y and are spaced apart along the first direction X. The first direction X and the second direction Y are perpendicular to each other.
[0036] The aforementioned multiple first scribing regions 110 and second scribing regions 120 together define multiple photolithography units 130. These photolithography units are used to form the target device, or to form the basic functional structure of the target device. When the first scribing regions 110 and second scribing regions 120 are uniformly arranged, all photolithography units 130 are the same size; when the spacing between the first scribing regions 110 and / or the second scribing regions 120 is not uniform, the sizes of the different photolithography units 130 may also differ.
[0037] At least two photolithography units 130 constitute a photolithography region LA. Each photolithography region LA has a first scribe line area 110 on each side of its opposite sides, and a second scribe line area 120 on each side of its opposite sides, both equipped with second stress relief grooves 121. Specifically, each photolithography region LA is also defined by specific first scribe line areas 110 and second scribe line areas 120. Both first scribe line areas 110 defining specific photolithography regions LA are equipped with first stress relief grooves 111, and both second scribe line areas 120 defining corresponding photolithography regions LA are equipped with second stress relief grooves 121. With this configuration, for a photolithography region LA, stresses generated during chip manufacturing due to filling, annealing, etc., can be eliminated or released using the deformation allowance provided by the first stress relief grooves 111 and second stress relief grooves 121 through deformation, preventing warping of the photolithography region LA.
[0038] Furthermore, the extension length of the first stress relief groove 111 in the first direction X is 0.25 to 0.6 times the dimension of the photolithography unit 130 in the first direction X, and the extension length of the second stress relief groove 121 in the second direction Y is 0.25 to 0.6 times the dimension of the photolithography unit 130 in the second direction Y. Thus, by reasonably setting the extension lengths of the first stress relief groove 111 and the second stress relief groove 121, the overall strength of the superjunction chip 100 can be maintained while ensuring the overall structural stability of the superjunction chip 100, thus preventing breakage during the manufacturing process.
[0039] The widths of the first stress relief groove 111 and the second stress relief groove 121 can be adjusted adaptively according to actual conditions, and can be adjusted between 4 micrometers and 6 micrometers. If the width is too small, the processing difficulty will be large, and if the width is too large, it will significantly weaken the strength of the superjunction chip 100 and easily lead to the breakage of the superjunction chip 100. It should be noted that there are multiple superjunction chips 100 on the wafer 200.
[0040] In some feasible solutions, the photolithography region LA is tetrahedral in shape. The first stress relief grooves 111 on both sides of the photolithography region LA are located at the two ends of one of the diagonals (first diagonal) of the photolithography region LA, and the second stress relief grooves 121 on both sides of the photolithography region LA are located at the two ends of the other diagonal (second diagonal) of the photolithography region LA.
[0041] Optionally, the first stress relief grooves 111 on both sides can be located on the same side of the first diagonal or on different sides, and the second stress relief grooves 121 on both sides can be located on the same side of the second diagonal or on different sides. Preferably, the first stress relief grooves 111 on both sides are located on different sides, and the second stress relief grooves 121 on both sides are located on different sides.
[0042] In some feasible solutions, the first stress relief groove 111 extends in the first direction X for one-third to one-half the length of the photolithography unit 130 in the first direction X, and the second stress relief groove 121 extends in the second direction Y for one-third to one-half the length of the photolithography unit 130 in the second direction Y. This allows for a better balance between stress relief / elimination and the overall strength of the superjunction chip 100.
[0043] In some feasible solutions, there are multiple first stress relief grooves 111, and these multiple first stress relief grooves 111 are spaced apart along the second direction Y. This arrangement can eliminate or release greater stress.
[0044] Similarly, multiple second stress relief grooves 121 can be provided, and the multiple second stress relief grooves 121 are spaced apart along the first direction X. In this way, the stress that the superjunction chip 100 can eliminate or release can be further increased.
[0045] For example, there can be four first stress relief grooves 111 and four second stress relief grooves 121. Alternatively, the number of first stress relief grooves 111 and second stress relief grooves 121 can be set to other numbers, depending on the actual needs and processing difficulty.
[0046] In some feasible solutions, a first scribe line region 110 between any two adjacent scribe lines 130 in the scribe line region LA is provided with a first stress relief groove 111, and / or, a second scribe line region 120 between any two adjacent scribe lines 130 in the scribe line region LA is provided with a second stress relief groove 121. In this way, different regions within the superjunction chip 100 can all have a certain ability to eliminate or release stress, which can better improve the problems of warping and alignment mark deformation that occur during the processing of the superjunction chip 100.
[0047] It is understood that there may be multiple first stress relief grooves 111 provided in the first scribing area 110 between two adjacent photolithography units 130, and the multiple first stress relief grooves 111 are spaced apart along the second direction Y. There may also be multiple second stress relief grooves 121 provided in the second scribing area 120 between two adjacent photolithography units 130, and the multiple second stress relief grooves 121 are spaced apart along the first direction X.
[0048] It should be noted that when multiple first stress relief grooves 111 and second stress relief grooves 121 are provided, a first isolation wall 140 is provided between two adjacent first stress relief grooves 111, and a second isolation wall 150 is provided between two adjacent second stress relief grooves 121. The first isolation wall 140 and / or the second isolation wall 150 are used as alignment marks during chip fabrication. In other words, when the first stress relief grooves 111 and second stress relief grooves 121 are formed on the superjunction chip 100, the first isolation wall 140 and the second isolation wall 150 can be formed simultaneously, improving the manufacturing efficiency of the superjunction chip 100 while reducing manufacturing difficulty.
[0049] Furthermore, since the first stress relief groove 111 and the second stress relief groove 121 can effectively eliminate or release the stress generated during the processing of the superjunction chip 100, the first isolation wall 140 and the second isolation wall 150 will not be easily deformed or displaced due to profitability issues.
[0050] See Figure 3 In some feasible solutions, the first stress relief groove 111 and / or the second stress relief groove 121 are straight grooves. Straight grooves are easy to process and help reduce the processing difficulty of the superjunction chip 100.
[0051] See Figure 4 In other feasible solutions, the first stress relief groove 111 and / or the second stress relief groove 121 are curved grooves, such as arc-shaped grooves or wavy grooves. For example, setting them as wavy grooves can effectively eliminate or release stress in multiple directions, and the isolation wall formed by two adjacent wavy grooves is also wavy, with obvious geometric features, which is beneficial for achieving alignment during processing.
[0052] See Figure 5 In some feasible solutions, the first stress relief groove 111 and / or the second stress relief groove 121 are zigzag grooves, which can effectively eliminate or release stress in multiple directions and facilitate alignment during processing.
[0053] In some feasible solutions, the cross-sectional shape of the first stress relief groove 111 perpendicular to the first direction X is trapezoidal, which can be an isosceles trapezoid, a non-isosceles trapezoid, or a right trapezoid.
[0054] In some other feasible solutions, the first stress relief groove 111 has a square cross-sectional shape perpendicular to the first direction X.
[0055] In some feasible solutions, the cross-sectional shape of the first stress relief groove 111 perpendicular to the first direction X is a semi-circular shape.
[0056] Understandably, see Figure 6 and Figure 7 In some feasible solutions, the cross-sectional shape of the second stress relief groove 121 perpendicular to the second direction Y is trapezoidal. This trapezoid can be an isosceles trapezoid, a non-isosceles trapezoid, or a right trapezoid.
[0057] See Figure 8 In some other feasible solutions, the cross-sectional shape of the second stress relief groove 121 perpendicular to the second direction Y is square.
[0058] See Figure 9 In some feasible solutions, the cross-sectional shape of the second stress relief groove 121 perpendicular to the second direction Y is a semi-circular shape.
[0059] The cross-sectional shape of the first stress relief groove 111 and the second stress relief groove 121 can be any of the shapes mentioned above, or a combination of the above shapes. The first stress relief groove 111 and the second stress relief groove 121 can be grooves of the same shape or grooves of different shapes.
[0060] It should be noted that when the superjunction chip 100 is fabricated using ion implantation and epitaxial growth, the first stress relief trench 111 and the second stress relief trench 121 can be formed by marking and etching. When the superjunction chip 100 is fabricated using deep trench technology, the first stress relief trench 111 and the second stress relief trench 121 can be formed by trench etching.
[0061] In this embodiment of the invention, stress relief grooves are provided in the scribing area of the superjunction chip 100, thereby effectively eliminating or releasing the stress generated in the superjunction chip 100 during processing. This reduces the deformation or displacement of the alignment marks caused by stress, improving the alignment effect. Due to the improved alignment effect, the accuracy of material filling is enhanced, which improves the charge balance level of the superjunction structure, thereby improving the stability of the internal voltage of the superjunction structure during use.
[0062] The superjunction chip structure provided by the embodiments of this utility model has been described in detail above. Specific examples have been used in this article to illustrate the principle and implementation of this utility model. The above description of the embodiments is only for the purpose of helping to understand the idea of this utility model. There may be changes in the specific implementation and application scope. Therefore, the content of this specification should not be construed as a limitation of this utility model.
Claims
1. A superjunction chip structure, characterized in that, The superjunction chip includes: Multiple strip-shaped first scribed areas extending along a first direction, and the multiple first scribed areas arranged along a second direction; Multiple strip-shaped second scribed areas extending along the second direction, the multiple second scribed areas being arranged along the first direction; the first direction being perpendicular to the second direction; and, Multiple photolithography units defined by the first scribing area and the second scribing area, at least two of the photolithography units constitute a photolithography area, and there is at least one photolithography area. The photolithography units are used to form a target device. Each photolithography area has a first stress relief groove in the first scribing area on opposite sides. Each photolithography area has a second stress relief groove in the second scribing area on opposite sides. Wherein, the extension length of the first stress relief groove in the first direction is one-quarter to three-fifths of the size of the photolithography unit in the first direction, and the extension length of the second stress relief groove in the second direction is one-quarter to three-fifths of the size of the photolithography unit in the second direction.
2. The superjunction chip structure according to claim 1, characterized in that, The first stress relief grooves on opposite sides of the photolithography area are arranged along the first diagonal of the photolithography area, and the second stress relief grooves on opposite sides of the photolithography area are arranged along the second diagonal of the photolithography area.
3. The superjunction chip structure according to claim 1, characterized in that, The first stress relief groove is multiple and is spaced apart along the second direction; And / or, there are multiple second stress relief grooves, which are spaced apart along the first direction.
4. The superjunction chip structure according to claim 1, characterized in that, Both the first stress relief groove and the second stress relief groove are multiple, with a first isolation wall between two adjacent first stress relief grooves and a second isolation wall between two adjacent second stress relief grooves. The first isolation wall and / or the second isolation wall are set as alignment marks for chip fabrication.
5. The superjunction chip structure according to claim 1, characterized in that, A first stress relief groove is provided in the first scribing area between two adjacent lithography units in the lithography area; And / or, the second scribing area between two adjacent lithography units in the lithography area is provided with a second stress relief groove.
6. The superjunction chip structure according to any one of claims 1-5, characterized in that, The first stress relief groove extends in the first direction for one-third to one-half of the size of the photolithography unit in the first direction.
7. The superjunction chip structure according to any one of claims 1-5, characterized in that, The extension length of the second stress relief groove in the second direction is one-third to one-half of the dimension of the photolithography unit in the second direction.
8. The superjunction chip structure according to any one of claims 1-5, characterized in that, The first stress relief groove and / or the second stress relief groove are straight grooves; or, the first stress relief groove and / or the second stress relief groove are curved grooves; or, the first stress relief groove and / or the second stress relief groove are broken-line grooves.
9. The superjunction chip structure according to any one of claims 1-5, characterized in that, The first stress relief groove has a trapezoidal cross-sectional shape perpendicular to the first direction; or, the first stress relief groove has a square cross-sectional shape perpendicular to the first direction; or, the first stress relief groove has a semi-circular cross-sectional shape perpendicular to the first direction.
10. The superjunction chip structure according to any one of claims 1-5, characterized in that, The cross-sectional shape of the second stress relief groove perpendicular to the second direction is trapezoidal; or, the cross-sectional shape of the second stress relief groove perpendicular to the second direction is square; or, the cross-sectional shape of the second stress relief groove perpendicular to the second direction is semi-circular.