Automatic test system for surge suppressor

Abstract

The utility model provides an automatic test system for a surge suppressor. The automatic test system comprises a test system mainboard and a test tool daughter board, an MOSFET driving module, a signal isolation module, an STM32 microprocessor module, a relay IO module and a signal BUFFER buffer module are arranged on the test system mainboard, the output end of the STM32 microprocessor module is connected with the input end of the MOSFET driving module through the signal isolation module, the output end of the MOSFET driving module is connected with the input end of the surge suppressor, and the output end of the surge suppressor is connected with the input end of the relay IO module. The output end of the surge suppressor is connected with the input end of the relay IO module, the output end of the relay IO module is connected with the input end of the signal BUFFER buffer module, and the output end of the signal BUFFER buffer module is connected with the oscilloscope; the test tool daughter board is used for clamping the surge suppressor and is inserted into the test system mainboard. According to the automatic test system for the surge suppressor designed by the utility model, the rapid and reliable test of the performance parameters of the surge suppressor with the surge pulse width in the range of 20-200ms can be realized.

Description

Technical Field

[0001] This utility model belongs to the field of electronic component testing technology, specifically relating to an automated testing system for surge suppressors. Background Technology

[0002] Surge suppressors are front-end modules in power conversion products. They effectively protect equipment and sensitive components from damage, ensure that electrical equipment is not subjected to surge voltage impacts, and operate normally and uninterruptedly when surge voltages occur. Accurately measuring the performance parameters of surge suppressors is very important in component reliability analysis.

[0003] Due to the unique electrical performance parameters of devices, conventional testing methods and equipment are insufficient for conducting electrical performance parameter tests. Most power supplies used for testing have slow voltage rise and fall rates, often failing to meet the high-speed switching requirements of surge test pulses. Currently, traditional surge suppressor testing requires manual testing using specialized surge generating equipment, resulting in low efficiency and the risk of device damage due to operational errors. Utility Model Content

[0004] The purpose of this invention is to solve the problems of low testing efficiency and reliability of surge suppressors in the existing technology, and to provide an automated testing system for surge suppressors.

[0005] To achieve the above objectives, the technical solution provided by this utility model is as follows:

[0006] An automated testing system for surge suppressors is provided, including a test system motherboard and a test fixture daughterboard. The test system motherboard includes a MOSFET driver module, a signal isolation module, an STM32 microprocessor module, a relay I / O module, a signal buffer module, and an LDO module. The output of the STM32 microprocessor module is connected to the input of the MOSFET driver module via the signal isolation module. The output of the MOSFET driver module is connected to the input of the surge suppressor. The output of the surge suppressor is connected to the input of the relay I / O module. A portion of the outputs of the relay I / O module are connected to... The multimeter has one output connected to the input of a signal buffer module, and the output of the signal buffer module is connected to an oscilloscope. The LDO module is used to power the test system motherboard. The test system motherboard integrates two N-channel MOSFETs, and the MOSFET driver module is used to control the conduction and turn-off of the N-channel MOSFETs. The test system motherboard has input interfaces for connecting two power sources, electronic loads, and auxiliary power supplies. The test fixture daughterboard is equipped with test fixtures and test interfaces. The test fixtures are used to mount surge suppressors, and the test fixture daughterboard is inserted into the test system motherboard through the test interfaces.

[0007] Furthermore, the test system motherboard is equipped with an OLED display module to display the pulse time set on the test fixture daughterboard in real time.

[0008] Furthermore, the test system motherboard has multiple DF9-31S connectors for mounting MOSFET driver modules, STM32 microprocessor modules, and signal buffer modules, as well as DF9-51S connectors for mounting relay I / O modules.

[0009] Furthermore, the test fixture is equipped with spring pins. One end of the spring pin is used to contact the four pins of the surge suppressor installed in the test fixture, and the other end extends out of the bottom surface of the test fixture and is soldered to the pads on the test fixture sub-board.

[0010] Furthermore, the test interface is a 96-pin European connector, which is plugged into the test system motherboard.

[0011] Furthermore, the MOSFET driver module includes the TC4420 chip and the IR2104S chip.

[0012] Furthermore, the test fixture subboard is equipped with an encoder assembly and a tactile switch. The signals generated by the encoder assembly and the tactile switch are used to drive the STM32 microprocessor module to adjust the surge test pulse width and time unit.

[0013] The advantages of this utility model are:

[0014] This utility model designs an automated testing system for surge suppressors, used to test the performance parameters of surge suppressors. The entire system adopts a floating ground design and can switch the power source at high speed. Without the aid of a dedicated surge generating device, it can achieve surge suppressor performance parameter testing within the range of 20µs-200ms surge pulse width, thus improving the efficiency and reliability of surge suppressor testing. Attached Figure Description

[0015] The features and advantages of this invention will become more readily understood from the following description with reference to the accompanying drawings, which are not drawn to scale and some features are enlarged or reduced to show details of specific parts.

[0016] Figure 1 This is a schematic diagram of the mainboard of the surge suppressor test system in this embodiment of the present invention;

[0017] Figure 2 This is a circuit design schematic diagram of the left side of the motherboard of the test system in this embodiment of the present invention;

[0018] Figure 3This is a schematic diagram of the circuit design of the right side of the motherboard of the test system in this embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of the circuit design of the 96-pin test resource J9 on the left side of the motherboard of the test system in this embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram of the circuit design of the 96-pin test resource J10 on the right side of the motherboard of the test system in this embodiment of the present invention.

[0021] Figure 6 This is a schematic diagram of the circuit design of the MOS transistor drive circuit U1 on the motherboard of the test system in this embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of the circuit design of the LDO module U2 on the motherboard of the test system in this embodiment of the present invention;

[0023] Figure 8 This is a circuit design schematic diagram of the signal isolation module U4 and the OLED display module U6 on the motherboard of the test system in this embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of the circuit design of the relay IO module U7 on the motherboard of the test system in this embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of the circuit design of the signal buffer module U9 on the motherboard of the test system in this embodiment of the present invention.

[0026] Figure 11 This is a schematic diagram of the circuit design of the power source load terminal J11 on the motherboard of the test system in this embodiment of the present invention.

[0027] Figure 12 This is a schematic diagram of the design of the STM32 microprocessor module in this embodiment of the present invention;

[0028] Figure 13 This is a schematic diagram of the MOSFET driving module in an embodiment of this utility model;

[0029] Figure 14 This is a schematic diagram of the structure of the test fixture in an embodiment of this utility model;

[0030] Figure 15 This is a schematic diagram of the installation position of the spring pin in an embodiment of this utility model;

[0031] Figure 16 This is a schematic diagram of the surge suppressor in an embodiment of this utility model.

[0032] In the diagram: 10 - test fixture; 11 - spring pin; 20 - surge suppressor. Detailed Implementation

[0033] The present invention will now be described in detail with reference to the accompanying drawings and exemplary embodiments thereof. It should be noted that the following detailed description of the present invention is for illustrative purposes only and is not intended to limit the scope of the invention.

[0034] An automated testing system for surge suppressors includes a test system motherboard and a test fixture daughterboard;

[0035] like Figure 1 As shown, the test system motherboard is equipped with a MOSFET driver module, a signal isolation module, an STM32 microprocessor module, a relay I / O module, a signal buffer module, and an LDO module. The output of the STM32 microprocessor module is connected to the input of the MOSFET driver module via the signal isolation module. The output of the MOSFET driver module is connected to the input of the surge suppressor 20. The output of the surge suppressor 20 is connected to the input of the relay I / O module. Part of the output of the relay I / O module is connected to a digital multimeter, and another part of the output is connected to the input of the signal buffer module. The output of the signal buffer module is connected to an oscilloscope. The LDO module is used to power the test system motherboard.

[0036] The test system motherboard integrates two N-channel MOSFETs. The MOSFET driver module is used to control the high-speed turn-on and turn-off of the N-channel MOSFETs. The N-channel MOSFET model is IRFP260. The test system motherboard has input interfaces for connecting two power sources, electronic loads, and auxiliary power supplies.

[0037] The test fixture sub-board is equipped with a test fixture 10 and a test interface. The test fixture 10 is used to clamp the surge suppressor 20. The test fixture sub-board is inserted into the test system motherboard through the test interface.

[0038] like Figure 2 , 3 As shown in Figures 4 and 5, test interfaces J9 and J10 integrate the control signals and power source of the STM32 microprocessor module, electronic load, oscilloscope, and digital multimeter, and are compatible with the test interfaces on the test fixture daughterboard. The test interfaces on the test fixture daughterboard are 96-pin European connectors, which are male connectors. J9 and J10 on the test system motherboard are also 96-pin European connectors, which are female connectors. The male and female connectors work together to insert the test fixture daughterboard onto the test system motherboard.

[0039] like Figure 2 , 6As shown, U1 on the test system motherboard is the MOSFET driver module insertion port. The MOSFET driver module is used to switch the second power source with a range of 200V / 50A at high speed.

[0040] like Figure 2 , 7 As shown, U2 on the test system motherboard is an LDO module, which outputs a set of 15V / 12V / 5V / 3.3V DC voltages to power other module chips on the test system motherboard;

[0041] like Figure 2 , 8 As shown, U4 on the test system motherboard is the STM32 microprocessor module insertion port. The STM32 microprocessor module is used for precise control of the 20us-200ms switching pulse time. A dedicated signal isolation module was designed before connecting the STM32 microprocessor module, and the ADUM1400 isolation chip was selected to meet the floating ground design requirements of the test system motherboard.

[0042] like Figure 2 , 8 As shown, U6 on the motherboard of the test system is an OLED display module, which is used to display the pulse time set on the test fixture daughterboard in real time. The OLED display module displays the pulse time and related setting information of the STM32 microprocessor module in real time.

[0043] like Figure 3 , 9 As shown, U7 on the test system motherboard is the relay I / O module insertion port, connected to a DF9-51S connector for inserting relay I / O modules. The relay I / O module is a switch matrix with multiple sets of switches on the output port, used to switch different test circuits, allowing the output signal of surge suppressor 20 to switch between different test states. When the relay I / O module is switched to the oscilloscope test circuit, the surge test signal applied to the input terminal for 20us-200ms is suppressed, and the output signal is buffered by the signal buffer module before entering the oscilloscope, allowing for the testing of response time and surge suppression voltage parameters.

[0044] like Figure 3 , 10 As shown, U9 on the test system motherboard is the signal buffer module insertion port, which is connected to a DF9-31S connector for inserting the signal buffer module. The signal buffer module can drive the surge suppressor 20 to buffer the output signal before testing.

[0045] like Figure 3 , 11As shown, J11 on the test system motherboard is the input interface for two power sources, electronic loads, and auxiliary power. The power supply on the entire test system board is a floating ground design. VCCH is the high end of the second power source, VREF is the high end of the first power source, and the COM terminal is the voltage reference terminal of the test system motherboard.

[0046] In this embodiment, the STM32 microprocessor module generates a 20µs-200ms TTL switching signal, which is isolated by a signal isolation module and then input to the MOSFET driver module. Under the control of the isolated TTL switching signal, the MOSFET driver module performs high-speed switching of the power source, causing the power source to generate a surge test pulse with a maximum specification of 200V / 50A. The generated surge test pulse is applied to the input terminal of the surge suppressor 20 to test the device's ability to suppress surge voltage. The two power sources, the first power source and the second power source, are both in CV constant voltage mode. The first power source continuously outputs a DC voltage for testing the DC parameters of the surge suppressor 20; the second power source continuously outputs a DC voltage of another range for generating the surge test pulse. The MOSFET driver module, under the control of the STM32 microprocessor module, performs high-speed switching of the second power source. The electronic load is set to a specified current value in CC mode for testing the DC performance parameters of the surge suppressor 20 under specific load conditions. When the output signal of surge suppressor 20 is buffered by the signal buffer module after passing through the relay I / O module, it is sent to the oscilloscope to test the response time and surge suppression voltage parameters. When the relay I / O module switches the output signal of surge suppressor 20 to digital multimeter mode, parameters such as input-output voltage difference, output voltage, output current, and power consumption can be tested and calculated.

[0047] like Figure 12 As shown, the STM32 microprocessor module integrates an STM32 series processor, with the STM32F103C8T6 chip as the main controller. J5 in the STM32 microprocessor module is the SWD interface of the STM32F103C8T6 chip, used for programming and debugging the STM32F103C8T6 chip. J1 and J2 on the STM32 microprocessor module are DF9-31P board-to-board connectors, which are male connectors. The DF9-31S connector on the test system motherboard is a female connector. The two connectors work together to allow the STM32 microprocessor module to be inserted into the U4 interface on the test system motherboard.

[0048] like Figure 13As shown, the MOSFET driver module is designed using TC4420 and IR2104S chips. J1 and J2 of the MOSFET driver module are DF9-31P board-to-board connectors, which are male connectors. The DF9-31S connector on the test system motherboard is a female connector. The male and female connectors work together to allow the MOSFET driver module to be inserted into the U1 interface on the test system motherboard.

[0049] In this embodiment, each module adopts a modular insertion method, which is beneficial for later testing and debugging.

[0050] like Figure 14 , 15 As shown in Figure 16, the test fixture 10 is equipped with spring pins 11. The upper end of the spring pins 11 is used to contact the four pins of the surge suppressor 20 installed in the test fixture 10, and the lower end extends out of the bottom surface of the test fixture 10 and is soldered to the corresponding pads on the test fixture sub-board. The test interface on the test fixture sub-board consists of two 96-pin European connectors (male connectors) on both sides, which are connected to the J9 and J10 European slots (female connectors) of the test motherboard, respectively.

[0051] In this embodiment, the test fixture 10 is welded to the test tooling subplate, such as... Figure 14 As shown, the test fixture 10 uses a POGOPIN spring pin 11 contact design, with a maximum single pin load of 20A, and is compatible with 4-pin metal-sealed surge suppressors 20 with a pin pitch of 9.00mm. Figure 16 The surge suppressor 20 shown is mounted upside down inside the test fixture 10, with its four pins contacting the tips of the spring pins 11 inside the test fixture 10. During testing, the test fixture sub-board is inserted into the J9 and J10 ports on the test system motherboard via the test interface. The test fixture sub-board is equipped with an encoder assembly for adjusting the surge test pulse width and a touch button for switching the surge test pulse width time unit.

[0052] The automated testing system designed in this embodiment adopts a floating ground design, which can realize rapid and accurate testing of the performance parameters of surge suppressor 20 with surge pulse width in the range of 20us-200ms without the aid of dedicated surge generation equipment.

[0053] Finally, it should be noted that the features mentioned and / or shown in the above description of exemplary embodiments of the present invention can be combined in the same or similar manner with one or more other embodiments, combined with features in other embodiments, or substituted for corresponding features in other embodiments. These combined or substituted technical solutions should also be considered as included within the protection scope of the present invention.

Claims

1. An automated testing system for surge suppressors, characterized in that, This includes the test system motherboard and the test fixture daughterboard; The test system motherboard is equipped with a MOSFET driver module, a signal isolation module, an STM32 microprocessor module, a relay I / O module, a signal buffer module, and an LDO module. The output of the STM32 microprocessor module is connected to the input of the MOSFET driver module via the signal isolation module. The output of the MOSFET driver module is connected to the input of a surge suppressor. The output of the surge suppressor is connected to the input of the relay I / O module. Part of the output of the relay I / O module is connected to a digital multimeter, and another part of the output is connected to the input of the signal buffer module. The output of the signal buffer module is connected to an oscilloscope. The LDO module is used to power the test system motherboard. The test system motherboard integrates two N-channel MOSFETs, and the MOSFET driving module is used to control the conduction and turn-off of the N-channel MOSFETs; the test system motherboard is provided with an input interface for connecting two power sources, electronic loads and auxiliary power supplies. The test fixture sub-board is equipped with a test fixture and a test interface. The test fixture is used to clamp the surge suppressor, and the test fixture sub-board is inserted into the test system motherboard through the test interface.

2. The surge suppressor automated testing system according to claim 1, characterized in that, The test system motherboard is equipped with an OLED display module, which is used to display the pulse time set on the test fixture subboard in real time.

3. The surge suppressor automated testing system according to claim 1 or 2, characterized in that, The test system motherboard has multiple DF9-31S connectors for mounting the MOSFET driver module, STM32 microprocessor module, and signal buffer module, as well as DF9-51S connectors for mounting the relay I / O module.

4. The surge suppressor automated testing system according to claim 1 or 2, characterized in that, The test fixture is equipped with a spring pin. One end of the spring pin is used to contact the four pins of the surge suppressor installed in the test fixture, and the other end extends out of the bottom surface of the test fixture and is welded to the pad of the test fixture sub-board.

5. The surge suppressor automated testing system according to claim 1 or 2, characterized in that, The test interface is a 96-pin European connector, which is plugged into the motherboard of the test system.

6. The surge suppressor automated testing system according to claim 1 or 2, characterized in that, The MOSFET driving module includes a TC4420 chip and an IR2104S chip.

7. The surge suppressor automated testing system according to claim 1 or 2, characterized in that, The test fixture subboard is equipped with an encoder assembly and a tactile switch. The signals generated by the operation of the encoder assembly and the tactile switch are used to drive the STM32 microprocessor module to adjust the surge test pulse width and time unit.

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