Integrated circuit device

Abstract

An integrated circuit device includes a first substrate, an electrical integrated circuit (IC) structure disposed proximate a backside surface of the first substrate, and a photonic IC structure disposed proximate a backside surface of the electrical IC structure, wherein the first substrate includes an optical lens at a front side surface of the first substrate. The photonic integrated circuit structure includes a second substrate providing a backside surface of the photonic IC structure, a photodetector, a grating coupler, and a reverse grating coupler disposed on a front side surface of the second substrate, and a reflector disposed on the front side surface of the photonic IC structure. The grating coupler and the reverse grating coupler are configured to direct light from the optical lens and the backside surface of the second substrate, respectively, to the photodetector. The reflector is configured to direct light from the reverse grating coupler back to the reverse grating coupler.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit device and a method for manufacturing the same. Background Technology

[0002] One result of the continuous advancements in integrated circuit (IC) technology is the increasing integration of electrical and optical functions within a single IC device. To support this integration, the electrical functions (e.g., testing using circuit probes (CP)) and optical functions (e.g., using lasers for optical test inputs) of devices are tested before delivery to customers, reducing or eliminating the supply of non-functional or poorly performing integrated circuit devices. Utility Model Content

[0003] According to some embodiments of this disclosure, an integrated circuit (IC) device includes a first substrate, an electrical integrated circuit structure disposed beneath the first substrate, and a photonic integrated circuit structure disposed beneath the electrical integrated circuit structure. The first substrate includes an optical lens on its top surface. The photonic integrated circuit structure includes a second substrate providing a bottom surface of the photonic integrated circuit structure, a photodetector disposed on the second substrate, a grating coupler, and a reverse grating coupler, and a reflector disposed on the top surface of the photonic integrated circuit structure adjacent to the electrical IC structure. The grating coupler is configured to receive first light via the optical lens, the first substrate, and the electrical integrated circuit structure and guide the first light to the photodetector. The reverse grating coupler is configured to receive second light via the back surface of the second substrate and guide the second light to the photodetector. The reflector is configured to receive third light from the reverse grating coupler and guide the third light back to the reverse grating coupler, wherein the reverse grating coupler is also configured to guide the third light to the photodetector.

[0004] According to some embodiments of this disclosure, an integrated circuit device includes an electrical integrated circuit structure, an optical lens disposed adjacent to a front surface of the electrical integrated circuit structure, a photonic integrated circuit structure disposed adjacent to a rear surface of the electrical integrated circuit structure, and a contact. The electrical integrated circuit structure includes a conductive layer. The photonic integrated circuit structure includes a photodetector, a grating coupler optically coupled to the photodetector and configured to guide first light received from the optical lens, a reverse grating coupler optically coupled to the photodetector and configured to guide second light received from the rear surface of the photonic integrated circuit structure to the photodetector, a reflector configured to reflect third light from the reverse grating coupler back to the reverse grating coupler, and a first conductive structure coupling the photodetector to the conductive layer, wherein the reverse grating coupler guides the third light to the photodetector. The contact is disposed adjacent to the rear surface of the photonic integrated circuit structure and coupled to a second conductive structure of the photonic integrated circuit structure, thereby coupling the contact to the conductive layer.

[0005] According to some embodiments of the present disclosure, a method includes providing a substrate for a photonic integrated circuit structure; forming a grating coupler and an inverse grating coupler and a photodetector on the substrate, wherein the grating coupler and the inverse grating coupler are optically coupled to the photodetector; forming a first conductive structure that couples the photodetector to a front surface of the photonic integrated circuit structure; forming a second conductive structure that is coupled to the front surface of the photonic integrated circuit structure; forming a reflector at the front surface of the photonic integrated circuit structure, the reflector being configured to reflect first light received from the inverse grating coupler back to the inverse grating coupler; fabricating an electrical integrated circuit structure including a conductive layer; bonding a back surface of the electrical integrated circuit structure to the front surface of the photonic integrated circuit structure to couple the conductive layer to the first conductive structure and the second conductive structure; and bonding an optical lens to the front surface of the electrical integrated circuit structure, the optical lens being configured to guide second light through the electrical integrated circuit structure to the grating coupler.

[0006] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1A A schematic flowchart illustrating some embodiments of the fabrication of integrated circuit devices that facilitate on-side electrical and optical testing according to this disclosure is shown.

[0009] Figure 1B and Figure 1C Schematic side views and schematic plan views of some embodiments of integrated circuit devices that facilitate same-side electrical and optical testing according to this disclosure are shown respectively.

[0010] Figure 2 A structural side view of some embodiments of an integrated circuit device according to this disclosure that facilitates same-side electrical and optical testing is shown.

[0011] Figures 3A to 3G Side views of some embodiments of an integrated circuit device according to the present disclosure are shown, which facilitates same-side electrical and optical testing at various stages of manufacturing.

[0012] Figure 4 A method for forming an integrated circuit device that facilitates same-side electrical and optical testing, according to some embodiments, is illustrated.

[0013] Figures 5A to 5FCross-sectional views of some embodiments of semiconductor structures including grating couplers and reverse grating couplers and integrated circuit devices according to the present disclosure are shown, which are beneficial for same-side electrical and optical testing.

[0014] Figure 6 The formation according to some embodiments is shown. Figures 5A to 5F Methods for developing semiconductor structures.

[0015] Figures 7A to 7C Plan views of some embodiments of a reverse grating coupler and a reflector for an associated integrated circuit device, which facilitate on-side electrical and optical testing according to the present disclosure, are shown.

[0016] Explanation of reference numerals in the attached figures 100:

[0018] 101: Electrical integrated circuit chips, E-IC chips

[0019] 103: E-IC chip, E-IC die

[0020] 104: Electrical integrated circuit structure, E-IC structure

[0021] 106: Photonic integrated circuit structure, P-IC structure

[0022] 108: Combined Integrated Circuits

[0023] 110: Lens layer

[0024] 112: Integrated circuit devices

[0025] 122: Photodetector

[0026] 123: Reflector

[0027] 123A, 123B, 708: Reflective elements

[0028] 123C: Two-dimensional array

[0029] 124: Grating Coupler

[0030] 126: Reverse grating coupler

[0031] 130, 212A, 212B: Contact

[0032] 202: Lens, Lens Structure

[0033] 204: Substrate

[0034] 206A: First conductive layer, conductive layer

[0035] 206B: Second conductive layer, conductive layer

[0036] 210A, 210B: Conductive pads, solder pads

[0037] 214A, 214B: Bonding pads

[0038] 216: Metal layer

[0039] 218: Interconnect via

[0040] 219: Conductive Structure

[0041] 221: Passivation layer

[0042] 222: Protective layer

[0043] 224, 208A, 208B: Through holes

[0044] 226, 228, 234: Dielectric layers

[0045] 230: Coating

[0046] 232: Dielectric

[0047] 236: Bonding pad metal structure, BPM structure, BPM

[0048] 504: First dielectric layer

[0049] 506: Second semiconductor layer

[0050] 508: Single Area

[0051] 509: Spine

[0052] 510: Ditch

[0053] 511: Sidewall

[0054] 512: Features

[0055] 513: Dielectric materials

[0056] 514: Etching Stop Layer

[0057] 516: Polycrystalline silicon

[0058] 700A, 700B, 700C: Configuration

[0059] 704: Waveguide Detailed Implementation

[0060] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may further include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0061] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0062] With the further integration of optical and related electrical functions into single integrated circuit devices, simultaneously testing both types of functions in a device is considered important from the perspective of wafer acceptance test (WAT) and chip probe (CP). However, such simultaneous testing can be challenging because accessible electrical input / output (I / O) points may be located on opposite sides of the device from the optical I / O locations, and some test equipment and processes may be incompatible with the sides of the accessing integrated circuit device. Providing test optical I / O paths on the opposite sides of the device to the optical I / O paths used during normal operation is possible. However, these test paths may suffer significant optical signal loss due to undesirable diffraction and scattering effects, resulting in lower efficiency for the associated optical tests.

[0063] To address these issues, this disclosure provides several embodiments of integrated circuit devices that facilitate same-side electrical and optical testing. In some embodiments, in addition to a grating coupler that guides light received from an operational optical I / O location to a photodetector, a reverse grating coupler that guides light received from the opposite side of the integrated circuit device to a photodetector can be used in conjunction with a reflector structure that reflects light passing through and / or around the reverse grating coupler back to the reverse grating coupler, which can then guide the reflected light to the photodetector. This structure of the integrated circuit device can enhance optical signal power, thereby enhancing signal integrity during device testing.

[0064] Therefore, the use of certain embodiments of integrated circuit devices can provide more accurate and therefore more useful simultaneous electrical and optical testing capabilities on the same side, which can be performed using currently available test systems. In some embodiments, this testing capability can lead to more accurate determination of chip yield and more precise monitoring of integrated circuit (IC) process health.

[0065] Figure 1A A schematic flowchart illustrating some embodiments of the fabrication of an integrated circuit device 112 facilitating same-side electrical and optical testing according to this disclosure is shown. As described in more detail below, in some embodiments, an electrical integrated circuit (E-IC) wafer 101 (e.g., a semiconductor wafer including one or more circuits) and a photonic integrated circuit (P-IC) structure 106 (e.g., an optical wafer including one or more photonic structures and associated circuits) may be fabricated or provided. After the E-IC wafer 101 is diced into a plurality of E-IC chips 103, the E-IC chips 103 may be bonded or otherwise attached to the P-IC structure 106 and further supplemented to form an E-IC structure 104, which, together with the P-IC structure 106, produces a combined integrated circuit 108. Then, to enable optical operation of the combined integrated circuit 108, a lens structure or lens layer 110 may be bonded or attached to the combined integrated circuit 108 to produce the integrated circuit device 112. Figure 1A As shown, one side (e.g., the top or front side) of the integrated circuit device 112 associated with the lens layer 110 provides an operating optical path, while the other side (e.g., the bottom or back side) of the integrated circuit device 112 facilitates access for same-side testing by providing contacts for electrical probing and test optical paths.

[0066] Figure 1B and 1C Schematic side views and schematic plan views of some embodiments of the integrated circuit device 112 according to this disclosure are shown respectively. Figure 1BAs shown, the E-IC structure 104 (including the E-IC die 103), the P-IC structure 106, and the lens layer 110 are as follows: Figure 1A As shown, they are attached or joined together.

[0067] In some embodiments, the P-IC structure 106 may include a grating coupler 124, a reverse grating coupler 126, a reflector 123, and a photodetector (PD) 122. For example... Figure 1B As shown, the grating coupler 124 can be configured to receive light via the lens layer 110, the E-IC structure 104, and the P-IC structure 106, and then guide this light to the photodetector 122 (e.g., via a waveguide or...). Figure 2 (Similar structures not shown in the figure). In some embodiments, the lens layer 110 may include a lens structure (e.g., at the top side or front surface of the lens layer 110) that guides and / or focuses light received at the lens structure to the grating coupler 124.

[0068] Additionally, in some embodiments, the reverse grating coupler 126 can be configured to receive light via the bottom or back surface of the P-IC structure 106 and guide it to the photodetector 122. Furthermore, in some embodiments, some of the received light may pass through the reverse grating coupler 126. To recover this light, the reflector 123 can be configured to reflect or guide the light received via the reverse grating coupler 126 back to the reverse grating coupler 126, which in turn can be configured to guide the reflected light to the photodetector 122. Therefore, the reflector 123 can amplify the test light signal received on the bottom or back side of the P-IC structure 106 (such as at the photodetector 122) to a useful degree.

[0069] In some embodiments, Figure 1B The diagram also shows a contact 130 electrically connected to the photodetector 122. In some embodiments, contact 130 may be an electrical contact adapted to engage with a circuit probe (CP) test system. In some embodiments, the contact is electrically coupled to the photodetector 122 via one or more conductive structures or layers in the P-IC structure 106 and E-IC structure 104 to facilitate connections through circuitry in the E-IC structure 104 (e.g., circuitry coupled to the photodetector 122). Thus, in some embodiments, contact 130, together with the reverse grating coupler 126, reflector 123, and photodetector 122, can enable simultaneous optical and electrical testing of the integrated circuit device 112 on the same side, while allowing the reception of operational optical signals via the lens layer 110 on the opposite side (e.g., the top or front side) of the integrated circuit device 112.

[0070] Figure 1C The schematic plan view depicts the E-IC die 103 bonded to the top or front surface of the P-IC structure 106. Additionally, in some embodiments, the grating coupler 124 and the reverse grating coupler 126 may be located in different lateral positions within the P-IC structure 106. Therefore, in some embodiments, although the grating coupler 124 and the reverse grating coupler 126 are in... Figure 1B The middle is shown as being in the vertical direction (e.g., in the direction perpendicular to). Figure 1C The grating coupler 124 and the reverse grating coupler 126 may be offset in the direction of the plan view, but they may also be located in the same or similar position range in the vertical direction.

[0071] Figure 2 A structural side view of some embodiments of an integrated circuit device 112 facilitating same-side electrical and optical testing according to this disclosure is shown. (See also...) Figure 1B As shown, the integrated circuit device 112 may include a lens layer 110, an E-IC structure 104 and a P-IC structure 106 bonded together, wherein the lens layer 110 is located on the top side or front side, and the P-IC structure 106 is located on the bottom side or back side of the integrated circuit device 112.

[0072] In some embodiments, lens layer 110 may include a substrate (e.g., a silicon substrate) comprising a lens or lens structure 202 etched or otherwise formed into a top or front surface of the substrate. While lens 202 is depicted as a spherical convex lens to focus light received therein onto grating coupler 124 of P-IC structure 106, other shapes may be provided for lens 202 in other embodiments. Furthermore, in some embodiments, lens layer 110 may be coated or otherwise covered with a protective layer or coating 230. Additionally, in some embodiments, dielectric layer 226 (e.g., silicon dioxide (SiO2), another form of silicon oxide (SiO2) may be used. x (or another dielectric material) can be formed on the bottom or back surface and the top or front surface of the lens layer 110. An E-IC structure 104 is formed to bond the two surfaces together. Moreover, in some embodiments, the lens layer 110 can be about 600-1000 micrometers (μm) thick, and in some embodiments it is about 775 μm thick.

[0073] E-IC structure 104 may include an E-IC die 103 providing electrical and / or electronic circuitry (e.g., providing electrical functions associated with the optical functions of integrated circuit device 112), which may be connected to one or more conductive layers, such as a first conductive layer 206A and a second conductive layer 206B. Figure 1AAs shown, the E-IC die 103 can be one of multiple E-IC chips 103 coupled to the P-IC structure 106.

[0074] To attach the individual E-IC die 103 to the P-IC structure 106, a dielectric layer 228 may be disposed over the P-IC structure 106. Furthermore, in some embodiments, one or more bonding pads 214A and 214B (e.g., aluminum bonding pads (AP)) may extend through the dielectric layer 228 and be formed on top of the dielectric layer 228 to couple to a metal layer 216 (e.g., the uppermost metal layer) of the P-IC structure 106, facilitating bonding between the E-IC structure 104 and the P-IC structure 106. Additionally, in some embodiments, a passivation layer 221 may be disposed over the dielectric layer 228 and the bonding pads 214A and 214B to provide a flat surface for subsequent dielectric layers 226 to be used in conjunction with the corresponding dielectric layers 226 of the E-IC die 103 to bond the E-IC die 103 having the P-IC structure 106.

[0075] Prior to this bonding, in some embodiments, a plurality of vias 224 may be formed in the passivation layer 221 and the dielectric layer 228, and a plurality of associated bond pad metal (BPM) structures 236 (e.g., copper (Cu) or another conductive material) may be formed in the dielectric layer 226. This resulting structure can be used to bond the E-IC die 103 to the P-IC structure 106 (e.g., bonding the dielectric layer 226 at one temperature and annealing the BPM structure 236 at a higher temperature, for example, in a process employed in System-on-Chips (SoIC) technology).

[0076] In some embodiments, after the E-IC die 103 is bonded to the P-IC structure 106, a stable surface can be provided in combination with the E-IC die 103 to form an E-IC structure 104 for applying a dielectric layer 226 (e.g., for bonding to the lens layer 110), such as by filling a dielectric 232 (e.g., SiO2, SiOx, or another dielectric material).

[0077] The P-IC structure 106 described above includes a substrate 204 (e.g., silicon or another material), and the remaining portions of the P-IC structure 106 may be disposed thereon, including the photodetector 122, grating coupler 124, reverse grating coupler 126, and reflector 123 described above. In some embodiments, the photodetector 122, grating coupler 124, and reverse grating coupler 126 may be disposed adjacent to the substrate 204 (e.g., directly above the substrate 204). Figure 2As shown, the photodetector 122, grating coupler 124 and reverse grating coupler 126 are shown in a schematic manner and are not intended to be an accurate physical representation of these structures.

[0078] In some embodiments, photodetector 122 may be a photodiode, a phototransistor, or another photodetector element configured to output an electrical signal representing a received optical signal. Each of grating coupler 124 and reverse grating coupler 126 may be, for example, via a waveguide or other optical structure (…). Figure 2 (Not shown) Optically coupled to photodetector 122. Additionally, photodetector 122 may be coupled to one or more conductive structures 219, which may include multiple metal layers 216 and interconnect vias 218. Although in other embodiments any number of conductive structures 219 may be coupled to photodetector 122, Figure 2 Two such conductive structures 219 are shown that can be individually connected to different parts of the photodetector 122 (e.g., control input and signal output). Thus, the two conductive structures 219 can couple the photodetector 122 to one or more parts of the E-IC die 103 through the via 224, the BPM structure 236, and the conductive layers 206A and 206B.

[0079] In some embodiments, the grating coupler 124 may serve as a diffraction grating, including associated diffraction elements for guiding light received via lens 202 into a waveguide or other optical structure toward photodetector 122 (e.g., typically along the plane defined by P-IC structure 106). Furthermore, in some embodiments, the grating coupler 124 may include diffraction elements of a first material (e.g., epitaxial silicon) and spacings of a second material (e.g., a dielectric material such as SiO2 or SiOx) between them. Additionally, in some embodiments, the diffraction elements may typically extend in the direction in which light is expected to be received (e.g., toward lens layer 110).

[0080] Accordingly, the reverse grating coupler 126 can serve as a diffraction grating, with the associated diffraction elements operating to guide light received via the substrate 204 into a waveguide or other optical structure for transmission to the photodetector 122. In some embodiments, the reverse grating coupler 126 may include diffraction elements of a second material (e.g., the same material used for the spacers between elements of the grating coupler 124, such as SiOx or another dielectric material) and spacers of a third material (e.g., polycrystalline silicon) therebetween. Additionally, the diffraction elements of the reverse grating coupler 126 may extend toward the substrate 204, and thus in a direction substantially opposite to the direction in which the diffraction elements of the grating coupler 124 extend. Therefore, in some embodiments, one or both of the structural materials and orientations of the grating coupler 124 and the reverse grating coupler 126 are opposite or opposite to each other.

[0081] One or more dielectric layers 234 (e.g., interlayer dielectrics (ILDs), such as SiOx or another dielectric material) may be disposed above at least a portion of the grating coupler 124, the reverse grating coupler 126, and the photodetector 122. During fabrication, the dielectric layer 234 may also determine the location of the metal layer 216 of the conductive structure 219.

[0082] In addition to the two conductive structures 219 coupled to the photodetector 122 as described above, two additional conductive structures 219 may be provided in the P-IC structure 106 and coupled to the conductive layers 206A and 206B through the via 224 and the associated BPM 236 to provide an electrical connection for electrical detection through the bottom or back side of the integrated circuit device 112.

[0083] like Figure 2 As shown, the P-IC structure 106 may further include an additional metal layer or structure (MH 220) that, in some embodiments, is closer to the substrate 204 than the various metal layers 216 in the P-IC structure 106 as described above. In some embodiments, MH 220 may be used as a metal heater (e.g., for controlling the temperature of the P-IC structure 106). In some embodiments, MH 220 may be one or more of titanium (Ti), titanium nitride (TiN), tungsten (W), or nickel-chromium (NiCr).

[0084] In some embodiments, reflector 123 may be disposed on or near the top or front surface of P-IC structure 106 and positioned above reverse grating coupler 126. In some embodiments, reflector 123 may be aligned with one of the metal layers (e.g., the uppermost metal layer 216 of P-IC structure 106). Additionally, in some embodiments, in the plan view of integrated circuit device 112, reflector 123 may completely or substantially cover reverse grating coupler 126. The following is combined with... Figures 7A-7C An example of the reverse grating coupler 126 is discussed.

[0085] In some embodiments, reflector 123 may comprise a metal (e.g., titanium (Ti)), a metal alloy (e.g., an aluminum-copper (AlCu) alloy), or another reflective material. Furthermore, in some embodiments, the thickness of reflector 123 may be in the range of 1000 to 14000 angstroms. Additionally, in some embodiments, the width and / or length of reflector 123 in the planar view of integrated circuit device 112 may be in the range of 10 to 200 μm, and in other embodiments, it may be in the range of 20 to 100 μm.

[0086] Similarly, in the P-IC structure 106, in some embodiments, at least one via (e.g., a through-dielectric via, TDV) may be configured to couple the corresponding conductive structure 219 to the bottom or back surface of the P-IC structure 106. Although Figure 2 Two vias 208A and 208B are shown, but other embodiments may employ any number of similar vias. Additionally, each of the corresponding number of pads (e.g., aluminum bonding pads (AP)) 210A and 210B may be disposed above the bottom or back surface of the substrate 204, and one or more corresponding contacts (e.g., controlled-collapse chip connections (C4s)) 212A and 212B may be disposed above the pads 210A and 210B, respectively. In some embodiments, a protective layer 222 may also be disposed above the bottom or back surface of the substrate 204 (e.g., to protect the pads 210A and 210B while exposing a portion of the contacts 212A and 212B, for example, for CP testing). This structure provides one or more electrical connections to the photodetector 122, which can be made through the bottom or back surface of the P-IC structure 106. For example, each of contacts 212A and 212B can be electrically connected to a corresponding portion of E-IC die 103 (e.g., circuitry that provides control signals to photodetector 122 and circuitry that receives output signals from photodetector 122), such that control and monitoring of photodetector 122 can be performed synchronously with the application of a light test signal via the back side of P-IC structure 106.

[0087] Therefore, in some embodiments, using Figure 2The structure of the integrated circuit device 112 shown allows for simultaneous optical and electrical testing of the integrated circuit device 112 on its bottom or back side via the test optical path through the substrate 204, the reverse grating coupler 126, and the reflector 123, as well as via the electrical probe interfaces of contacts 212A and 212B, while providing an operating optical path via the lens 202. Furthermore, in some embodiments, the use of the reflector 123 can enhance the optical signal intensity associated with the optical test path including the reverse grating coupler 126, making the obtained test results useful.

[0088] Figure 3A-3G Cross-sectional views of some embodiments of an integrated circuit device (e.g., integrated circuit device 112) are shown, facilitating back-side optical and electrical testing at various stages of manufacturing. Although Figure 3A-3G The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted in whole or in part.

[0089] Figure 3A This diagram shows a substrate 204 (e.g., a silicon substrate) on which a photodetector 122, a grating coupler 124, and a reverse grating coupler 126 (e.g., as described above) are formed, together with one or more dielectric layers 234 (e.g., SiO2). x (Or another dielectric material), encompassing photodetector 122, grating coupler 124, and reverse grating coupler 126. Embodiments relating to the manufacture of these components will be discussed in detail below. Figures 5A-5F .

[0090] Figure 3B The formation (e.g., deposition) of multiple metal layers 216 between additional dielectric layers 234 and interconnect vias 218 is shown to fabricate one or more conductive structures 219. Figure 3B In this example, two conductive structures 219 are coupled to the photodetector 122. Also as... Figure 3B As shown, in some embodiments, an additional metal layer MH 220 may be formed (e.g., at the level of the lowest metal layer below metal layer 216). Additionally, in some embodiments, reflector 123 is formed (e.g., deposited) on the reverse grating coupler 126. In some embodiments, reflector 123 and... Figure 3B The uppermost metal layer 216 depicted in the image is formed simultaneously, and therefore can be located in conjunction with... Figure 3B The uppermost metal layer 216 shown is in the same plane. Figure 3B The resulting structure shown is the P-IC structure 106 as described above.

[0091] Figure 3C A layer is shown formed on a P-IC structure 106 in preparation for bonding the P-IC structure 106 to an E-IC die 103 of an E-IC structure 104. In some embodiments, a dielectric layer 228 (e.g., SiO2) may be formed (e.g., deposited) above the front surface of the P-IC structure 106. x The dielectric layer 228 is then etched (e.g., by photolithography or another etching process) to expose portions of the topmost one or more metal layers 216 (e.g., those topmost metal layers 216 included in the conductive structure 219 connected to the photodetector 122). Bonding pads 214A and 214B (e.g., aluminum pads (AP)) can then be formed over the respective exposed portions of each metal layer 216, for example by conformally depositing metal (e.g., aluminum or another conductive material) over the dielectric layer 228, followed by etching (e.g., using photolithography) to remove those metal portions not included in the bonding pads 214A and 214B.

[0092] Subsequently, a passivation layer 221 (e.g., a dielectric material) can be deposited over the dielectric layer 228 and the bonding pads 214A and 214B. Furthermore, in some embodiments, a plurality of vias 224 can be formed (by etching and subsequent deposition of a conductive material, such as copper) to extend from the front surface of the passivation layer 221 through the dielectric layer 228 to the uppermost metal layer 216 of the passivation layer 221. A plurality of conductive structures 219 are included, including conductive structures 219 coupled to the photodetector 122.

[0093] A dielectric layer 226 may be formed (e.g., deposited) on top of the passivation layer 221, and a plurality of bonding pad metal (BPM) structures 236 may be formed therein (e.g., via etching and subsequent deposition). In an embodiment, each of a number of BPMs 236 may be formed on and connected to a corresponding via 224. In some embodiments, the upper surface of the resulting dielectric layer 226 and the associated BPMs 236 may be planarized (e.g., via chemical mechanical planarization (CMP)).

[0094] Figure 3C The diagram also shows an E-IC die 103, which includes circuitry on a back surface having a front surface to be bonded to a P-IC structure 106. Figure 3C(Not shown in the diagram). In some embodiments, the E-IC die 103 is coupled to one or more conductive layers 206A and 206B. In some embodiments, a dielectric layer 226 having a plurality of BPMs 236 is formed on the back surface of the E-IC die 103, such that each of at least some of the BPMs 236, the contacts, is one of the conductive layers 206A and 206B. Furthermore, in some embodiments, each of the at least some of the BPMs 236 connected to the E-IC die 103 is laterally aligned to contact a corresponding BPM 236 contact on the front surface of the P-IC structure 106.

[0095] Figure 3D The diagram illustrates the combination (e.g., bonding) of an E-IC die 103 with a P-IC structure 106 (e.g., via SoIC technology as described above). In some embodiments, for example, the dielectric layer 226 of the E-IC die 103 and the P-IC structure 106 may be bonded together (e.g., at a first temperature), and the BPM 236 of the E-IC die 103 and the P-IC structure 106 may be bonded (e.g., at a second temperature above the first temperature) to bond the E-IC die 103 to the P-IC structure 106. In some embodiments, multiple such Figure 3D The E-IC die 103 shown can also be bonded to other portions of the P-IC structure 106. Furthermore, a filler dielectric 232 can be deposited in the voids above the P-IC structure 106 not occupied by the E-IC die 103 (e.g., the remaining space between multiple E-IC dies 103) to form a generally flat surface provided by the E-IC die 103 and the filler dielectric 232. In some embodiments, another dielectric layer 226 can be formed (e.g., deposited) on the generally flat surface, thereby creating an E-IC structure 104 bonded to the P-IC structure 106.

[0096] Figure 3E A lens layer 110 (e.g., a substrate made of silicon or other materials) incorporating a lens 202 is shown. In some embodiments, the lens 202 may be formed (e.g., etched or molded) onto the front surface of the lens layer 110. Although as Figure 3E The lens 202 shown may be a cylindrical convex lens, but in other embodiments, the lens 202 may be shaped as another type of lens. Additionally, in some embodiments, a protective layer or coating 230 may be formed (e.g., deposited) on at least one of the front or back surfaces of the lens layer 110. Furthermore, in some embodiments, a dielectric layer 226 (e.g., SiOx or another dielectric material) may be deposited on the back surface of the lens layer 110 to prepare for bonding with a corresponding dielectric layer 226 at the front surface of the E-IC structure 104.

[0097] Figure 3FThe integrated circuit device 112 is shown after the lens layer 110 is bonded to the E-IC structure 104. Also as... Figure 3F As shown, each of the plurality of vias (e.g., TSVs) 208A and 208B is formed by a conductive material (e.g., copper or another metal material) through the substrate 204 and some dielectric layers 234 (e.g., via etching and subsequent deposition) to electrically connect to the lowest metal layer 216 of the corresponding conductive structure 219, which is connected to the associated conductive layers 206A and 206B of the E-IC structure 104.

[0098] Figure 3G Conductive pads (e.g., aluminum pads (AP)) 210A and 210B are shown formed (e.g., by deposition and subsequent etching) above the back surface of substrate 204, wherein each conductive pad is connected to a corresponding one of vias 208A and 208B. Subsequently, each of a plurality of contacts (e.g., C4) 212A and 212B may be formed over a corresponding one of pads 210A and 210B. In some embodiments, a protective layer 222 (e.g., a dielectric material) may also be disposed above the back surface of substrate 204 (e.g., to protect pads 210A and 210B while exposing a portion of contacts 212A and 212B, for example, for electrical sensing), as described above.

[0099] Figure 4 A method 400 for forming an integrated circuit device (e.g., integrated circuit device 112) that facilitates same-side optical and electrical testing is illustrated according to some embodiments. Although the methods and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that this disclosure is not limited to the shown order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0100] In some embodiments, actions 402 to 420 may correspond, for example, to those previously performed. Figures 3A to 3G The structure shown in the diagram. In action 402, for example, a structure for a photonic integrated circuit (e.g., Figure 3B The substrate of the P-IC structure 106 (e.g., Figure 3A Substrate 204). In action 404, a grating coupler is formed above the substrate (e.g., Figure 3A grating coupler 124), reverse grating coupler (e.g., Figure 3A The reverse grating coupler 126) and the photodetector (e.g., Figure 3A (Photodetector 122). In some embodiments, a grating coupler and a reverse grating coupler are optically coupled to the photodetector. Figure 3A Cross-sectional views corresponding to some embodiments of actions 402 and 404 are shown. Additionally, the following... Figures 5A-5F and Figure 6 A more comprehensive discussion is given of some embodiments of the substrate and the fabrication of grating couplers and reverse grating couplers.

[0101] In action 406, a first conductive structure is formed to couple the photodetector to the front surface of the photonic integrated circuit structure (e.g., ...). Figure 3B The conductive structure 219). In action 408, a second conductive structure is formed to couple the photodetector to the front surface of the photonic integrated circuit structure (e.g., conductive structure 219). Figure 3B Conductive structure 219). Figure 3B Cross-sectional views corresponding to some embodiments of actions 406 and 408 are shown.

[0102] In action 410, a reflector is formed on the front surface of the photonic integrated circuit structure (e.g., Figure 3B (Reflector 123). In some embodiments, the reflector may be configured to reflect the first light received from the reverse grating coupler back to the reverse grating coupler. Figure 3B Cross-sectional views corresponding to some embodiments of action 410 are shown.

[0103] In action 412, a conductive layer is fabricated (e.g., Figure 3C Electrical integrated circuit die (e.g., conductive layer 206A) of the conductive layer 206A Figure 3D (E-IC die 103). In action 414, the back surface of the electrical integrated circuit die is bonded to the front surface of the photonic integrated circuit structure to couple the conductive layer to the first conductive structure and the second conductive structure. Figure 3C and 3D Cross-sectional views corresponding to some embodiments of actions 412 and 414 are shown.

[0104] In action 416, the optical lens (e.g., Figure 3E and 3F The lens layer 110 is bonded to the front surface of an electrical integrated circuit structure (e.g., E-IC structure 104) that includes an electrical integrated circuit die. In some embodiments, the optical lens may be configured to guide second light through the electrical integrated circuit structure to a grating coupler. Figure 3E and 3F Cross-sectional views corresponding to some embodiments of action 416 are shown.

[0105] In action 418, a via is formed in the substrate of the photonic integrated circuit structure through the back surface of the photonic integrated circuit structure (e.g., Figure 3F (through hole 208A). Figure 3F Cross-sectional views corresponding to some embodiments of action 418 are shown.

[0106] In action 420, a contact is formed on the back surface of the photonic integrated circuit structure (e.g., Figure 3G The contact 212A is used to couple the contact to the second conductive structure. Figure 3G Cross-sectional views corresponding to some embodiments of action 418 are shown.

[0107] Figures 5A-5F Cross-sectional views of some embodiments of semiconductor structures including grating couplers and reverse grating couplers for use in integrated circuit devices are shown, which facilitate on-side electrical and optical testing at various stages of manufacturing. Although Figures 5A-5F The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted in whole or in part.

[0108] Figure 5A Substrate 204 is shown (e.g., Figure 3A The substrate 204, which may be referred to as the first semiconductor layer (e.g., silicon), may have a thickness of 500-1000 μm in some embodiments and approximately 775 μm in others. Furthermore, the first dielectric layer 504 (e.g., SiO2) may also have a thickness of 504. x Alternatively, another dielectric material may be disposed above the substrate 204. In some embodiments, the thickness of the first dielectric layer 504 may be in the range of 0.6-3.0 μm, and in some embodiments it may be approximately 2.0 μm. Additionally, in some embodiments, a second semiconductor layer 506 (e.g., epitaxial silicon) may be disposed above the first dielectric layer 504. In some embodiments, the thickness of the second semiconductor layer 506 may be in the range of 2500-3000 angstroms, and in some embodiments it may be in the range of approximately 2750 angstroms.

[0109] Figure 5BThis illustrates forming (e.g., etching) a single region 508, multiple individual trenches 510, and multiple features 512 into a second semiconductor layer 506. In some embodiments, the single region 508 corresponds to an inverse grating coupler 126, the multiple trenches 510 correspond to grating couplers 124, and the multiple features 512 can be coupled to other structures of the P-IC structure 106 (e.g., at least one waveguide couples the grating coupler 124 and / or the inverse grating coupler 126 to...). Figure 2 It is associated with the photodetector 122.

[0110] Figure 5C This illustrates the formation (e.g., deposition) of dielectric material 513 (e.g., SiO2) in a single region 508, multiple independent trenches 510, and multiple features 512. x In some embodiments, the dielectric material 513 may further form a second dielectric layer over each of the single region 508, the plurality of independent trenches 510, and the plurality of features 512, thereby covering the entire second semiconductor layer 506. Furthermore, in some embodiments, an etch stop layer (e.g., silicon nitride (SiN)) 514 may be formed (e.g., deposited) over the dielectric material 513.

[0111] Figure 5D The formation (e.g., etching) of a single region 508 is illustrated, leaving sidewalls 511 of dielectric material 513 and a plurality of individual ridges 509. In some embodiments, the plurality of individual ridges 509 extend partially from the first dielectric layer 504 into the single region 508. In some embodiments, an etch stop layer 514 may be patterned to promote penetration during etching of the single region 508.

[0112] Figure 5E The formation (e.g., deposition) of polysilicon 516 is shown to fill an etched single region 508. In some embodiments, the upper surface of the polysilicon 516 substantially corresponds to the upper surface of the second dielectric layer of the dielectric material 513.

[0113] Figure 5F The removal of the etch stop layer 514 is illustrated, thereby exposing the upper surface of the second dielectric layer of dielectric material 513. Furthermore, in some embodiments, additional dielectric material 513 may be added (e.g., deposited) on top of the previously formed dielectric material 513 and polysilicon 516. In some embodiments, structures in a single region 508 create a reverse grating coupler 126, while structures associated with multiple independent trenches 510 create grating couplers 124.

[0114] Figure 6 The formation according to some embodiments is shown. Figures 5A to 5FThe method of semiconductor structure. Therefore, in some embodiments, actions 602-620 may correspond to Figure 4 Action 404. For example, at action 602, a first dielectric layer (e.g., ...) is formed over the substrate of P-IC 106 (e.g., substrate 204, which includes a first semiconductor substrate). Figure 5A The first dielectric layer 504). Furthermore, in operation 604, a second semiconductor layer is formed over the second semiconductor layer 506 (e.g., ...). Figure 5A The second semiconductor layer 506). Figure 5A Cross-sectional views corresponding to some embodiments of actions 602 and 604 are shown.

[0115] In action 606, a grating coupler (e.g.) is etched into the second semiconductor layer. Figure 2 Multiple independent trenches (e.g., grating coupler 124) that do not reach the first dielectric layer Figure 5B Multiple independent trenches 510). Furthermore, in action 608, an inverted grating coupler (e.g., ...) is etched in the second semiconductor layer extending to the first dielectric layer. Figure 2 A single region (e.g., the reverse grating coupler 126) Figure 5B (Single area 508). Figure 5B Cross-sectional views corresponding to some embodiments of actions 606 and 608 are shown.

[0116] In action 610, a dielectric material (e.g.) is deposited. Figure 5C The dielectric material 513 is used to fill multiple independent trenches and a single region to form a second dielectric layer. Furthermore, in action 612, an etch stop layer (e.g., Figure 5C The etch stop layer 514 is deposited on the second dielectric layer. Figure 5C Cross-sectional views corresponding to some embodiments of actions 610 and 612 are shown.

[0117] In action 614, a single region is etched to leave sidewalls of dielectric material (e.g., ...). Figure 5D The sidewalls 511) and multiple individual ridges (e.g., Figure 5D Multiple individual ridges (509). Figure 5D Cross-sectional views corresponding to some embodiments of action 614 are shown.

[0118] In action 616, polysilicon is deposited (e.g., Figure 5E Polysilicon 516 is used to fill a single etched region. Figure 5E Cross-sectional views corresponding to some embodiments of action 616 are shown.

[0119] In action 618, the etch stop layer can be removed. In some embodiments, this removal can expose the upper surface of the second dielectric layer of the dielectric material. Furthermore, in action 620, in some embodiments, additional dielectric material can be formed over the residual structure. Figure 5F Cross-sectional views corresponding to some embodiments of actions 618 and 620 are shown.

[0120] Figures 7A to 7C The present disclosure shows the method for use Figure 2 A plan view of some embodiments of the reverse grating coupler 126 and associated reflector 123 of the integrated circuit device 112, which facilitates on-side electrical and optical testing. Figures 7A-7C In each of these embodiments, the reverse grating coupler 126 may include a series of semi-circular grating elements (e.g., Figure 5D-5F Each ridge 509 is described as having an overall wedge shape and guides the light received at the reverse grating coupler 126 to a waveguide 704, which is coupled to the tip of the reverse grating coupler 126 (e.g., for transmission to...). Figure 2 (Photodetector 122). However, in other embodiments, other configurations of the reverse grating coupler 126 are also possible.

[0121] exist Figure 7A In some embodiments of configuration 700A, the reflector can be configured to completely or substantially cover a single continuous square reflective element 123A of the reverse grating coupler 126. Figure 7B In some embodiments of configuration 700B, the reflector may be configured as a single, continuous circular reflective element 123B that completely or substantially covers the reverse grating coupler 126. In other embodiments, other shapes (e.g., hexagonal, octagonal, etc.) may be used as the single reflective element of the reflector.

[0122] exist Figure 7C In some embodiments of configuration 700C, the reflector can be configured as a two-dimensional array 123C of independently spaced reflective elements 708. For example... Figure 7C The depicted reflective element 708 is square, but other shapes (e.g., rectangular, circular, etc.) are possible in other embodiments. Figure 7C In this embodiment, the two axes of the two-dimensional array 123C are defined not to be oriented 90 degrees apart, resulting in a tilted alignment of the rows of the two-dimensional array 123C. However, in other embodiments, it is also possible for these axes to be spaced 90 degrees apart.

[0123] Some embodiments relate to integrated circuit (IC) devices. The device includes a first substrate, an electrical integrated circuit structure disposed beneath the first substrate, and a photonic integrated circuit structure disposed beneath the electrical integrated circuit structure. The first substrate includes an optical lens on its top surface. The photonic integrated circuit structure includes a second substrate providing a bottom surface of the photonic integrated circuit structure, a photodetector disposed on the second substrate, a grating coupler, and a reverse grating coupler, and a reflector disposed on the top surface of the photonic integrated circuit structure adjacent to the electrical IC structure. The grating coupler is configured to receive first light via the optical lens, the first substrate, and the electrical integrated circuit structure and guide the first light to the photodetector. The reverse grating coupler is configured to receive second light via the back surface of the second substrate and guide the second light to the photodetector. The reflector is configured to receive third light from the reverse grating coupler and guide the third light back to the reverse grating coupler, wherein the reverse grating coupler is also configured to guide the third light to the photodetector. In one embodiment, the photonic integrated circuit structure further includes a conductive structure having multiple metal layers interconnected with multiple vias, the conductive structure being configured to electrically couple the photodetector to the electrical integrated circuit structure; and the uppermost metal layer of the multiple metal layers being coplanar with the reflector. In one embodiment, the reflector is electrically isolated from the conductive structure. In one embodiment, the reflector comprises at least one of titanium or an aluminum-copper alloy. In one embodiment, the thickness of the reflector ranges from 1000 angstroms to 14000 angstroms. In one embodiment, at least one of the width and length of the reflector ranges from 20 micrometers to 100 micrometers. In one embodiment, in a plan view of the integrated circuit device, the reflector is aligned with the reverse grating coupler. In one embodiment, in a plan view of the integrated circuit device, the reflector is a single continuous reflective element. In one embodiment, the reflector comprises a two-dimensional array of reflective elements spaced apart from each other.

[0124] Some embodiments relate to another integrated circuit device. The device includes an electrical integrated circuit structure, an optical lens disposed adjacent to a front surface of the electrical integrated circuit structure, a photonic integrated circuit structure disposed adjacent to a rear surface of the electrical integrated circuit structure, and a contact. The electrical integrated circuit structure includes a conductive layer. The photonic integrated circuit structure includes a photodetector, a grating coupler optically coupled to the photodetector and configured to guide first light received from the optical lens, a reverse grating coupler optically coupled to the photodetector and configured to guide second light received from the rear surface of the photonic integrated circuit structure to the photodetector, a reflector configured to reflect third light from the reverse grating coupler back to the reverse grating coupler, and a first conductive structure coupling the photodetector to the conductive layer, wherein the reverse grating coupler guides the third light to the photodetector. The contact is disposed adjacent to the rear surface of the photonic integrated circuit structure and coupled to a second conductive structure of the photonic integrated circuit structure, thereby coupling the contact to the conductive layer. In one embodiment, the electrical integrated circuit structure includes an electrical integrated circuit die; and a plurality of electrical integrated circuit chips (dies) include the electrical integrated circuit die; and each of the plurality of electrical integrated circuit chips is bonded to the photonic integrated circuit structure. In one embodiment, the integrated circuit device further includes: a first waveguide configured to optically couple the grating coupler to the photodetector; and a second waveguide configured to optically couple the reverse grating coupler to the photodetector. In one embodiment, in a plan view of the integrated circuit device, the grating coupler, the reverse grating coupler, and the electrical integrated circuit structure do not overlap; and in a plan view of the integrated circuit device, each of the grating coupler, the reverse grating coupler, and the electrical integrated circuit structure overlaps with the photonic integrated circuit structure.

[0125] Some embodiments relate to a method. This method includes providing a substrate for a photonic integrated circuit structure; forming a grating coupler and an inverse grating coupler and a photodetector on the substrate, wherein the grating coupler and the inverse grating coupler are optically coupled to the photodetector; forming a first conductive structure coupling the photodetector to a front surface of the photonic integrated circuit structure; forming a second conductive structure coupled to the front surface of the photonic integrated circuit structure; forming a reflector at the front surface of the photonic integrated circuit structure, the reflector being configured to reflect first light received from the inverse grating coupler back to the inverse grating coupler; fabricating an electrical integrated circuit structure including a conductive layer; bonding a back surface of the electrical integrated circuit structure to the front surface of the photonic integrated circuit structure to couple the conductive layer to the first conductive structure and the second conductive structure; and bonding an optical lens to the front surface of the electrical integrated circuit structure, the optical lens being configured to guide second light via the electrical integrated circuit structure to the grating coupler. In one embodiment, a via is formed in the substrate of the photonic integrated circuit structure via the back surface of the photonic integrated circuit structure; and a contact is formed above the back surface of the photonic integrated circuit structure to couple the contact to the second conductive structure. In one embodiment, the reflector is located in the same plane as each layer of the first conductive structure and the second conductive structure; and the reflector is electrically isolated from the first conductive structure and the second conductive structure. In one embodiment, the substrate includes a first semiconductor layer; and the method further includes: forming a first dielectric layer on the first semiconductor layer; and forming a second semiconductor layer on the first dielectric layer. In one embodiment, forming the grating coupler and the reverse grating coupler includes: etching a plurality of independent trenches of the grating coupler in the second semiconductor layer that do not reach the first dielectric layer; etching a single region of the reverse grating coupler in the second semiconductor layer to the first dielectric layer; depositing a dielectric material to fill the plurality of independent trenches and the single region and forming a second dielectric layer; forming an etch stop layer on the second dielectric layer; etching the single region to leave sidewalls of the dielectric material and a plurality of independent ridges; depositing polysilicon to fill the etched single region; and removing the etch stop layer. In one embodiment, the plurality of independent ridges extend from a portion of the first dielectric layer to the single region. In one embodiment, in a plan view of the photonic integrated circuit structure, the reflector substantially covers the single region.

[0126] It should be understood that in this disclosure and the appended claims, the terms "first," "second," "third," etc., are merely general designations used for ease of description to distinguish different elements of a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the elements and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0127] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various alterations, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, characterized in that, include: A first substrate, including an optical lens on the top surface of the first substrate; An electrical integrated circuit structure is disposed beneath the first substrate; as well as A photonic integrated circuit structure is disposed below the electrical integrated circuit structure, the photonic integrated circuit structure comprising: The second substrate provides the bottom surface of the photonic integrated circuit structure; A photodetector, a grating coupler, and an inverse grating coupler are disposed on the second substrate; and A reflector is disposed on the top surface of the photonic integrated circuit structure and adjacent to the electrical integrated circuit structure; in: The grating coupler is configured to receive first light through the optical lens, the first substrate, and the electrical integrated circuit structure, and to guide the first light to the photodetector. The reverse grating coupler is configured to receive second light via the back surface of the second substrate and guide the second light to the photodetector; and The reflector is configured to receive third light from the reverse grating coupler and guide the third light back to the reverse grating coupler, wherein the reverse grating coupler is also configured to guide the third light to the photodetector.

2. The integrated circuit device according to claim 1, characterized in that, in: The photonic integrated circuit structure further includes a conductive structure having multiple metal layers interconnected with multiple vias, the conductive structure being configured to electrically couple the photodetector to the electrical integrated circuit structure; as well as The uppermost metal layer of the plurality of metal layers is located on the same plane as the reflector, wherein the reflector is electrically isolated from the conductive structure.

3. The integrated circuit device according to claim 1, characterized in that, The thickness of the reflector ranges from 1,000 angstroms to 14,000 angstroms, and at least one of the width and length of the reflector ranges from 20 micrometers to 100 micrometers.

4. The integrated circuit device according to claim 1, characterized in that, In the plan view of the integrated circuit device, the reflector is aligned with the reverse grating coupler.

5. The integrated circuit device according to claim 1, characterized in that, In the plan view of the integrated circuit device, the reflector is a single continuous reflective element.

6. The integrated circuit device according to claim 1, characterized in that, The reflector comprises a two-dimensional array of reflective elements spaced apart from each other.

7. An integrated circuit device, characterized in that, include: Electrical integrated circuit structure, including conductive layers; An optical lens is disposed on the front surface adjacent to the electrical integrated circuit structure; A photonic integrated circuit structure is disposed on the back surface adjacent to the electrical integrated circuit structure, the photonic integrated circuit structure comprising: Photodetector; A grating coupler is optically coupled to the photodetector and configured to guide first light received from the optical lens; An inverted grating coupler is optically coupled to the photodetector and configured to guide second light received from the back surface of the photonic integrated circuit structure to the photodetector; A reflector, configured to reflect a third light from the reverse grating coupler back to the reverse grating coupler, wherein the reverse grating coupler guides the third light to the photodetector; and A first conductive structure, coupling the photodetector to the conductive layer; and A contact is disposed on the back surface of the photonic integrated circuit structure and coupled to the second conductive structure of the photonic integrated circuit structure, thereby coupling the contact to the conductive layer.

8. The integrated circuit device according to claim 7, characterized in that, in: The electrical integrated circuit structure includes an electrical integrated circuit die; and Multiple electrical integrated circuit chips (dice) include the electrical integrated circuit die; and Each of the plurality of electrical integrated circuit chips is bonded to the photonic integrated circuit structure.

9. The integrated circuit device according to claim 7, characterized in that, Including: A first waveguide is configured to optically couple the grating coupler to the photodetector; and The second waveguide is configured to optically couple the reverse grating coupler to the photodetector.

10. The integrated circuit device according to claim 7, characterized in that, in: In the plan view of the integrated circuit device, the grating coupler, the reverse grating coupler, and the electrical integrated circuit structure do not overlap; and In the plan view of the integrated circuit device, each of the grating coupler, the reverse grating coupler, and the electrical integrated circuit structure overlaps with the photonic integrated circuit structure.

Images