Memory chip and electronic device

Abstract

The utility model discloses a storage chip and electronic equipment, and relates to the technical field of chips. The memory chip comprises a memory chip body, a first voltage module, a second voltage module and a capacitor module, the first voltage module, the second voltage module and the capacitor module are all arranged on the memory chip body, and the first voltage module and the second voltage module share the capacitor module; through the design, the product performance is ensured, and the cost is reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more particularly to a memory chip and an electronic device. Background Technology

[0002] With the development of storage chip technology, UFS chips (Universal Flash Storage chips, or UFS for short) are increasingly being used in various electronic devices as one of the core components of computer equipment.

[0003] In the electrical design of UFS chips, the power supply system is a critical component. VCC is the power supply network common to the industry specifications of UFS2.X and UFS3.X, and its voltage value is generally 3.3V (VCC) or 2.5V (FVCC). The two usually need to be electrically connected to select the power supply voltage to ensure normal operation and reliable data access.

[0004] like Figure 1 As shown, in current UFS chips, the VCC and FVCC voltage modules are each connected to a capacitor module, and the signal connection of the power supply network needs to be achieved through traditional wire bonding technology. The choice of wires mainly includes gold, silver, and alloy wires, with gold wire being widely used due to its better conductivity, corrosion resistance, and ductility. However, due to the limitations of the wire's inherent physical properties, it is prone to breakage inside the chip, leading to equipment failure. Furthermore, the material and manufacturing process of gold wire are more expensive, resulting in a higher product cost for UFS chips. Utility Model Content

[0005] The purpose of this application is to provide a memory chip and electronic device that ensure product performance and reduce costs.

[0006] This application discloses a memory chip, which includes a memory chip body, a first voltage module, a second voltage module, and a capacitor module. The first voltage module, the second voltage module, and the capacitor module are all disposed on the memory chip body, wherein the first voltage module and the second voltage module share the capacitor module.

[0007] Optionally, the first voltage module and the second voltage module are arranged opposite to each other, the capacitor module is located below the first voltage module and the second voltage module, and the capacitor module is welded and fixed to the first voltage module and the second voltage module.

[0008] Optionally, the capacitor module has a first pad on the side near the first voltage module, the capacitor module has a second pad on the side near the second voltage module, the first voltage module has a third pad on the side near the capacitor module, and the second voltage module has a fourth pad on the side near the capacitor module. The first pad is soldered to the third pad, and the second pad is soldered to the fourth pad.

[0009] Optionally, the capacitor module includes a first terminal, a second terminal, and a third terminal, with the second terminal located between the first terminal and the third terminal. The first terminal is close to the first voltage module and the second voltage module. The first terminal is sequentially divided into a first block, a second block, and a third block, with the second block located between the first block and the third block. The first pad is disposed in the first block, and the second pad is disposed in the third block. The first voltage module is sequentially divided into a fourth block, a fifth block, a sixth block, and a seventh block, with the fourth block, fifth block, sixth block, and seventh block arranged in a cross shape. The second voltage module... The blocks are sequentially divided into eight, nine, ten, and eleventh blocks, which are arranged in a cross shape. The fifth block is positioned opposite the eighth block, and the sixth block is positioned opposite the eleventh block. The third pad is located on the side of the sixth block closest to the eleventh block, and the fourth pad is located on the side of the eleventh block closest to the sixth block. The sixth block is soldered and fixed to the first block via the third pad and the first pad, and the eleventh block is soldered and fixed to the third block via the fourth pad and the second pad.

[0010] Optionally, the capacitor module includes a first terminal, a second terminal, and a third terminal, with the second terminal located between the first terminal and the third terminal. The first terminal is close to the first voltage module and the second voltage module. The first terminal is sequentially divided into a first block, a second block, and a third block, with the second block located between the first block and the third block. The first pad is disposed in the first block, and the second pad is disposed in the third block. The first voltage module is sequentially divided into a fourth block, a fifth block, a sixth block, and a seventh block, with the fourth block, fifth block, sixth block, and seventh block arranged in a cross shape. The second voltage module... The module is sequentially divided into eight, nine, ten, and eleventh blocks, which are arranged in a cross shape. The fifth block is positioned opposite the eighth block, and the sixth block is positioned opposite the eleventh block. The third pad is located on the side of the fifth block closest to the eighth block, and the fourth pad is located on the side of the eighth block closest to the fifth block. The fifth block is soldered and fixed to the first block via the third pad and the first pad, and the eighth block is soldered and fixed to the third block via the fourth pad and the second pad.

[0011] Optionally, the capacitor module includes a first end, a second end, and a third end. The second end is located between the first end and the third end. The first end is close to the first voltage module and the second voltage module. The first end is sequentially divided into a first block, a second block, and a third block. The second block is located between the first block and the third block. The first pad is disposed in the first block, and the second pad is disposed in the third block. Along the direction from the first voltage module to the second voltage module, the first voltage module is sequentially divided into a fourth region, a fifth region, and a sixth region. The second voltage module is sequentially divided into a seventh region, an eighth region, and a ninth region. The sixth region is positioned opposite to the seventh region. On the side of the sixth region closest to the capacitor module, there are multiple vertically spaced third pads and multiple vertically spaced fourth pads. The multiple third pads are positioned one-to-one with the multiple fourth pads. The first pad is soldered to one of the third pads, and the second pad is soldered to the fourth pad corresponding to one of the third pads.

[0012] Optionally, the spacing between the first voltage module and the second voltage module is 0.15mm-0.25mm.

[0013] Optionally, the storage chip is a UFS chip, the first voltage module is a VCC voltage module, and the second voltage module is an FVCC voltage module.

[0014] Optionally, the memory chip further includes a main controller and a wafer, both of which are disposed on the memory chip body. The main controller and the wafer are disposed opposite to each other. The main controller is signal-connected to the first voltage module and the second voltage module, and the wafer is signal-connected to the second voltage module.

[0015] This application also discloses an electronic device, including the memory chip described above.

[0016] Compared to existing technologies where the VCC and FVCC voltage modules in a UFS chip are each connected to a separate capacitor module, and the signal connection of the power supply network requires traditional wire bonding, the memory chip of this application includes a memory chip body, a first voltage module, a second voltage module, and a capacitor module. The first voltage module, the second voltage module, and the capacitor module are all located on the memory chip body. The first voltage module and the second voltage module share a capacitor module. This allows the capacitor module to replace wire bonding for bridging the power supply network, enabling selection of the power supply voltage. This avoids the breakage problems that are prone to occur with wire bonding, ensuring product performance. Furthermore, the shared capacitor strategy effectively reduces the amount of capacitor used in the production process, further saving costs. Attached Figure Description

[0017] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0018] Figure 1 This is a schematic diagram of the connection structure between the first voltage module and the second voltage module within a memory chip in the prior art;

[0019] Figure 2 This is a block diagram of the electronic device provided in this application;

[0020] Figure 3 This is a schematic diagram of the structure of the memory chip provided in this application;

[0021] Figure 4 This is a schematic diagram of the structure of the first voltage module, the second voltage module, and the capacitor module provided in the first embodiment of this application;

[0022] Figure 5 yes Figure 4 Schematic diagram of the structure after welding;

[0023] Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure along section line A-A';

[0024] Figure 7 This is a schematic diagram of the welding structure of the first voltage module, the second voltage module, and the capacitor module provided in the second embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the structure of the first voltage module, the second voltage module, and the capacitor module provided in the third embodiment of this application;

[0026] Figure 9 This is a schematic diagram of the welding structure of the first voltage module, the second voltage module, and the capacitor module provided in the third embodiment of this application.

[0027] Wherein: 10, Electronic device; 100, Memory chip; 110, Memory chip body; 120, First voltage module; 121, Third pad; 122, Fourth block; 123, Fifth block; 124, Sixth block; 125, Seventh block; 130, Second voltage module; 131, Fourth pad; 132, Eighth block; 133, Ninth block; 134, Tenth block; 135, Eleventh block; 140, Capacitor module; 141, First pad; 142, Second pad; 143, First terminal; 144, Second terminal; 145, Third terminal; 146, First block; 147, Second block; 148, Third block; 149, First conductive bump; 150, Second conductive bump; 160, Main controller; 170, Wafer; 180, Line. Detailed Implementation

[0028] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0029] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean a non-exclusive inclusion, which may include or add one or more other features, integers, steps, operations, units, components, and / or combinations thereof. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0030] Figure 2This is a block diagram of the electronic device provided in this application. Figure 3 This is a schematic diagram of the structure of the memory chip provided in this application, combined with... Figures 2-3 This application discloses an electronic device 10, including a memory chip 100. The memory chip 100 includes a memory chip body 110, a first voltage module 120, a second voltage module 130, and a capacitor module 140. The first voltage module 120, the second voltage module 130, and the capacitor module 140 are all disposed on the memory chip body 110. The first voltage module 120 and the second voltage module 130 share the capacitor module 140.

[0031] Compared to the existing technology where the VCC voltage module and FVCC voltage module in a UFS chip are each connected to a capacitor module 140, and the signal connection of the power supply network needs to be achieved through the traditional wire bonding process 180, the memory chip 100 of this application includes a memory chip body 110, a first voltage module 120, a second voltage module 130, and a capacitor module 140. The first voltage module 120, the second voltage module 130, and the capacitor module 140 are all disposed on the memory chip body 110. Among them, the first voltage module 120 and the second voltage module 130 share the capacitor module 140. In this way, the capacitor module 140 can be used to replace the wire bonding process 180 for bridging the power supply network, so as to realize the selection of the power supply voltage. This avoids the breakage problem that is prone to occur when using the wire bonding method, ensuring product performance. The shared capacitor strategy effectively reduces the amount of capacitor used in the production process, further saving costs.

[0032] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0033] First embodiment:

[0034] The storage chip 100 can be a UFS chip. The first voltage module 120 is a VCC voltage module, and the second voltage module 130 is an FVCC voltage module. VCC mainly provides power to the core logic circuit of the UFS device, and FVCC is specifically designed to provide power to the NAND flash memory to meet its specific voltage requirements. The capacitor module 140 is connected to the first voltage module 120 and the second voltage module 130 respectively, and is used to stabilize the power supply to provide voltage to the first voltage module 120 and the second voltage module 130.

[0035] like Figure 3As shown, the memory chip 100 also includes a main controller 160 and a wafer 170. Both the main controller 160 and the wafer 170 are disposed on the memory chip body 110, and are positioned opposite each other. The main controller 160 is signal-connected to the first voltage module 120 and the second voltage module 130, and the wafer 170 is signal-connected to the second voltage module 130. Since the first voltage module 120 and the second voltage module 130 may be connected under certain circumstances, a capacitor module 140 is needed to connect the first voltage module 120 and the second voltage module 130. The main controller 160 switches between the first voltage module 120 and the second voltage module 130 according to the voltage signal to meet the power supply requirements of the wafer 170. The signal transmission and the connection control of the main controller 160 and the wafer 170 are consistent with the existing memory chip 100 and will not be described in detail here.

[0036] Figure 4 This is a schematic diagram of the structure of the first voltage module, the second voltage module, and the capacitor module provided in the first embodiment of this application. Figure 5 yes Figure 4 Schematic diagram of the structure after welding. Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure along section line A-A', combined with... Figures 4-6 The first voltage module 120 and the second voltage module 130 are arranged opposite to each other. The capacitor module 140 is located below the first voltage module 120 and the second voltage module 130, and the capacitor module 140 is welded and fixed to the first voltage module 120 and the second voltage module 130. In this way, the power connection is completed during SMT production, which can further optimize the production process and improve production efficiency.

[0037] like Figure 4 As shown, combined with Figures 5-6 The capacitor module 140 has a first pad 141 on the side near the first voltage module 120, a second pad 142 on the side near the second voltage module 130, a third pad 121 on the side near the first voltage module 120, and a fourth pad 131 on the side near the second voltage module 130. The first pad 141 is soldered to the third pad 121, and the second pad 142 is soldered to the fourth pad 131.

[0038] Specifically, the capacitor module 140 includes a first end 143, a second end 144, and a third end 145. The second end 144 is located between the first end 143 and the third end 145. The first end 143 is close to the first voltage module 120 and the second voltage module 130. The first end 143 is sequentially divided into a first block 146, a second block 147, and a third block 148. The second block 147 is located between the first block 146 and the third block 148. The first pad 141 is disposed in the first block 146, and the second pad 142 is disposed in the third block 148. The first voltage module 120 is sequentially divided into a fourth block 122, a fifth block 123, a sixth block 124, and a seventh block 125. The fourth block 122, the fifth block 123, the sixth block 124, and the seventh block 125 are arranged in a cross shape. The two voltage modules 130 are sequentially divided into an eighth block 132, a ninth block 133, a tenth block 134, and an eleventh block 135, which are arranged in a cross shape. The fifth block 123 is positioned opposite the eighth block 132, and the sixth block 124 is positioned opposite the eleventh block 135. The third pad 121 is located on the side of the sixth block 124 near the eleventh block 135, and the fourth pad 131 is located on the side of the eleventh block 135 near the sixth block 124. The sixth block 124 is welded and fixed to the first block 146 via the third pad 121 and the first pad 141, and the eleventh block 135 is welded and fixed to the third block 148 via the fourth pad 131 and the second pad 142.

[0039] The distance between the first voltage module 120 and the second voltage module 130 is 0.15mm-0.25mm. The capacitor module 140 uses C0201 capacitors. Therefore, this distance is slightly smaller than the width of the capacitor module 140 to facilitate soldering.

[0040] Second embodiment:

[0041] Figure 7 This is a schematic diagram of the welding structure of the first voltage module, the second voltage module, and the capacitor module provided in the second embodiment of this application, as shown below. Figure 7As shown, in the second embodiment of this application, this embodiment differs from the first embodiment in that the third pad 121 is disposed on the side of the fifth block 123 near the eighth block 132, and the fourth pad 131 is disposed on the side of the eighth block 132 near the fifth block 123. The fifth block 123 is soldered and fixed to the first block 146 via the third pad 121 and the first pad 141, and the eighth block 132 is soldered and fixed to the third block 148 via the fourth pad 131 and the second pad 142. That is, after soldering the first voltage module 120, the second voltage module 130, and the capacitor module 140, almost half of the space occupied by the capacitor module 140 is between the first voltage module 120 and the second voltage module 130, which saves the area occupied by the capacitor module 140, allowing the overall area of ​​the memory chip 100 to be made relatively smaller.

[0042] Third embodiment:

[0043] Figure 8 This is a schematic diagram of the structure of the first voltage module, the second voltage module, and the capacitor module provided in the third embodiment of this application, as shown below. Figure 8 As shown, as a third embodiment of this application, this embodiment differs from the first and second embodiments in that, along the direction from the first voltage module 120 to the second voltage module 130, the first voltage module 120 is sequentially divided into a fourth region, a fifth region, and a sixth region, and the second voltage module 130 is sequentially divided into a seventh region, an eighth region, and a ninth region. The sixth region is arranged opposite to the seventh region. On the side of the sixth region near the capacitor module 140, there are multiple vertically spaced third pads 121 and multiple vertically spaced fourth pads 131. The multiple third pads 121 and multiple fourth pads 131 are arranged opposite to each other. The first pad 141 is soldered to one of the third pads 121, and the second pad 142 is soldered to the fourth pad 131 corresponding to one of the third pads 121. That is, the first pad 141 of the capacitor module 140 can be soldered to any one of the third pads 121 of the first voltage module 120, and the position of the fourth pad 131 on the second voltage module 130 soldered to the second pad 142 corresponds to the position of the soldered third pad 121. In this way, the soldering position of the capacitor module 140 can be selected according to the size of the memory chip 100, which is more convenient.

[0044] Fourth embodiment:

[0045] Figure 9This is a schematic diagram of the welding structure of the first voltage module, the second voltage module, and the capacitor module provided in the third embodiment of this application, as shown below. Figure 9 As shown, as a third embodiment of this application, this embodiment differs from the first, second, and third embodiments in that the chip further includes a first conductive bump 149 and a second conductive bump 150. The first conductive bump 149 and the second conductive bump 150 have conductive properties. The first conductive bump 149 is disposed on the side of the first pad 141 near the first voltage module 120, and the second conductive bump 150 is disposed on the side of the second pad 142 near the second voltage module 130. The area of ​​the first conductive bump 149 projected onto the capacitor module 140 is larger than the area of ​​the first pad 141 projected onto the capacitor module 140; the area of ​​the second conductive bump 150 projected onto the capacitor module 140 is larger than the area of ​​the second pad 142 projected onto the capacitor module 140. This facilitates operation when the first pad 141 is soldered to the third pad 121 via the first conductive bump 149, and when the second pad 142 is soldered to the fourth pad 131 via the second conductive bump 150, thus avoiding soldering failure.

[0046] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0047] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A memory chip, characterized in that, The memory chip includes a memory chip body, a first voltage module, a second voltage module, and a capacitor module, wherein the first voltage module, the second voltage module, and the capacitor module are all disposed on the memory chip body. The first voltage module and the second voltage module share the capacitor module.

2. The memory chip according to claim 1, characterized in that, The first voltage module and the second voltage module are arranged opposite to each other, and the capacitor module is located below the first voltage module and the second voltage module, and the capacitor module is welded and fixed to the first voltage module and the second voltage module.

3. The memory chip according to claim 2, characterized in that, The capacitor module has a first pad on the side closest to the first voltage module, a second pad on the side closest to the second voltage module, a third pad on the side closest to the capacitor module, and a fourth pad on the side closest to the capacitor module. The first pad is soldered to the third pad, and the second pad is soldered to the fourth pad.

4. The memory chip according to claim 3, characterized in that, The capacitor module includes a first end, a second end, and a third end. The second end is located between the first end and the third end. The first end is close to the first voltage module and the second voltage module. The first end is divided into a first block, a second block, and a third block in sequence. The second block is located between the first block and the third block. The first pad is disposed in the first block, and the second pad is disposed in the third block. The first voltage module is sequentially divided into a fourth block, a fifth block, a sixth block, and a seventh block, which are arranged in a cross shape; the second voltage module is sequentially divided into an eighth block, a ninth block, a tenth block, and an eleventh block, which are arranged in a cross shape. The fifth block is positioned opposite to the eighth block, and the sixth block is positioned opposite to the eleventh block. The third pad is positioned on the side of the sixth block closest to the eleventh block, and the fourth pad is positioned on the side of the eleventh block closest to the sixth block. The sixth block is soldered and fixed to the first block via the third pad and the first pad, and the eleventh block is soldered and fixed to the third block via the fourth pad and the second pad.

5. The memory chip according to claim 3, characterized in that, The capacitor module includes a first end, a second end, and a third end. The second end is located between the first end and the third end. The first end is close to the first voltage module and the second voltage module. The first end is divided into a first block, a second block, and a third block in sequence. The second block is located between the first block and the third block. The first pad is disposed in the first block, and the second pad is disposed in the third block. The first voltage module is sequentially divided into a fourth block, a fifth block, a sixth block, and a seventh block, which are arranged in a cross shape; the second voltage module is sequentially divided into an eighth block, a ninth block, a tenth block, and an eleventh block, which are arranged in a cross shape. The fifth block is positioned opposite to the eighth block, and the sixth block is positioned opposite to the eleventh block. The third pad is positioned on the side of the fifth block closest to the eighth block, and the fourth pad is positioned on the side of the eighth block closest to the fifth block. The fifth block is fixed to the first block by welding the third pad and the first pad, and the eighth block is fixed to the third block by welding the fourth pad and the second pad.

6. The memory chip according to claim 3, characterized in that, The capacitor module includes a first end, a second end, and a third end. The second end is located between the first end and the third end. The first end is close to the first voltage module and the second voltage module. The first end is divided into a first block, a second block, and a third block in sequence. The second block is located between the first block and the third block. The first pad is disposed in the first block, and the second pad is disposed in the third block. Along the direction from the first voltage module to the second voltage module, the first voltage module is sequentially divided into a fourth region, a fifth region, and a sixth region, and the second voltage module is sequentially divided into a seventh region, an eighth region, and a ninth region. The sixth region is positioned opposite to the seventh region. On the side of the sixth region closest to the capacitor module, there are multiple vertically spaced third pads and multiple vertically spaced fourth pads. The multiple third pads are positioned one-to-one with the multiple fourth pads. The first pad is soldered to one of the third pads, and the second pad is soldered to the fourth pad corresponding to one of the third pads.

7. The memory chip according to claim 4, 5, or 6, characterized in that, The distance between the first voltage module and the second voltage module is 0.15mm-0.25mm.

8. The memory chip according to claim 4, 5, or 6, characterized in that, The storage chip is a UFS chip, the first voltage module is a VCC voltage module, and the second voltage module is an FVCC voltage module.

9. The memory chip according to claim 1, characterized in that, The memory chip also includes a main controller and a wafer. The main controller and the wafer are both disposed on the memory chip body. The main controller and the wafer are disposed opposite to each other. The main controller is signal-connected to the first voltage module and the second voltage module, and the wafer is connected to the second voltage module.

10. An electronic device comprising a memory chip as described in any one of claims 1-9.

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